Abstract: A component incorporating module includes an insulation resin layer, a plurality of lands arranged to mount components and wiring patterns connected to the plurality of lands, which are arranged along a first main surface of the resin layer, and circuit components connected to the lands to mount components. The circuit components are embedded in the resin layer. The plurality of lands have thicknesses that are greater than those of the wiring patterns adjacent to the corresponding lands.

Abstract: A circuit board assembly which includes an electrically insulating layer, a conductive printed wiring layer formed on the surface of the electrically insulating layer and includes a plurality of conductive paths, a conductive trace on the electrically insulating layer and apparatus for dissipating a transient in addition to a surface mount resistor fixed in relation to the trace. In some forms of the invention the surface mount resistor has opposed generally planar lips. The trace may also be generally planar. In some cases the lower lips and the trace are generally parallel. The generally planar lips of the surface mount resistor may be closer to the trace than the thickness of the surface mount resistor. A single geometric plane may extend through substantially all of the lips and all of the trace. In some cases the lower surface of the lips and the lower surface of the trace are substantially coplanar.

Abstract: A power interconnection system comprising a plurality of z-axis compliant connectors passing power and ground signals between a first circuit board to a second circuit board is disclosed. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance interconnect.

Abstract: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including a semiconductor chip (10), mounted on the substrate (12). Each of the plurality of semiconductor packages (11a, 11b) includes a first radio communication element (16) for transmitting and receiving a signal between the semiconductor chips (10) in the plurality of semiconductor packages (11a, 11b) by radio communication, and the first radio communication element (16) is constituted independently of the semiconductor chip (10).

Abstract: A capacitor including a substrate; a conductive layer provided on the substrate and containing conductive particles; a valve metal sheet having a dielectric part formed throughout an entire surface of the conductive layer; a protection layer covering the valve metal sheet; a first electrode terminal electrically connected to the conductive layer and partially exposed from an external surface of the protection layer; and a second electrode terminal electrically connected to a surface of the valve metal sheet which is opposite to a surface of the valve metal sheet on which the dielectric part is provided, and the second electrode terminal partially exposed from the external surface of the protection layer; wherein the dielectric part is made of an oxide of a metallic material of the valve metal sheet, the dielectric part is formed with a corrugated surface on the conductive layer, and the conductive particles of the conductive layer are in contact with the corrugated surface of the dielectric part.

Abstract: A printed circuit board includes a first signal layer, a first reference layer, a second reference layer, and a second signal layer. An integrated circuit mounted on the first signal layer includes a power supply terminal connected to a first power supply via. The second signal layer includes a filter and a power supply wire. The filter includes a power terminal connected to the first power supply via, and a ground terminal connected to the second reference layer. The first power supply via is connected to the first reference layer through the power supply wire and a second power supply via. A void defined in the second reference layer is at least partially vertically overlapping with the power supply wire, and enables the first reference layer to function as a reference plane for the power supply wire, to increase impedance of the power supply wire.

Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.

Abstract: The formation of an assembled unit consisting of an annular capacitor [a wound, metallized dielectric capacitor in the shape of a closed path ring] with other power conversion components arranged and attached in manners uniquely allowed by the ring design will allow higher density converter designs [power/unit volume]. The resulting short connection paths between the capacitor element and the switching semiconductors also provide a very low inductance path that minimizes voltage spikes on the switching semiconductors as a result of turn-off di/dt. The capacitor serves as a short time current source and sink for the switching semiconductors. With the described configuration the RMS current seen by the capacitor can be made more volumetrically uniform enabling more uniform capacitor rise. The single capacitor configured as described also mitigates bus resonance problems often observed in prior art when multiple discrete capacitors are connected in parallel.

Abstract: Improved noise isolation for high-speed digital systems on packages and printed circuit boards is provided by the use of mixed alternating impedance electromagnetic bandgap (AI-EBG) structures and a power island configured to provide ultimate noise isolation. A power island is surrounded by a plurality of mixed AI-EBG structures to provide a power distribution network. In this structure, the gap around the power island provides excellent isolation from DC to the first cavity resonant frequency which is determined by the size of the structure and dielectric material. One AI-EBG structure provides excellent isolation from the first cavity resonant frequency of around 1.5 GHz to 5 GHz. The other AI-EBG structure provides excellent noise isolation from 5 GHz to 10 GHz. Through use of this novel configuration of AI-EBG structures, a combination effect of the hybrid AI-EBG structure provides excellent isolation far in excess of 10 GHz.

Abstract: A power conversion apparatus comprising a base which includes a first fixation portion and a second fixation portion that are coupled to each other at a desired angle, wherein power modules are fixed on the first fixation portion of the base, a control circuit board is fixed with its first principal surface held in direct or indirect touch with the second fixation portion of the base, and components constituting a control circuit are packaged on the second principal surface of the control circuit board. Owing to the configuration, a versatility for the installation of the power conversion apparatus on a vehicle becomes high, the vibration-proofness of the control circuit board is enhanced, and heats generated by the electronic components, etc. packaged on the control circuit board are sufficiently emitted.

Abstract: Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract: The present invention describes methods for enhancing the performance of two-capacitor low-pass filters. In certain embodiments of the invention, the capacitors are placed on opposite sides of a PCB board.

Abstract: A display device includes a display panel on which an image is displayed, and a driving board. The driving board includes a substrate, a first multi-layer ceramic condenser disposed on the substrate and to which a first current is supplied, and a second multi-layer ceramic condenser disposed substantially parallel with the first multi-layer ceramic condenser and to which a second current is supplied. The first current and the second current are supplied to the first multi-layer ceramic condenser and the second multi-layer ceramic condenser, respectively, in opposite directions.

Abstract: In a DC-DC converter module, a first through-hole conductor provided in a substrate as a first lead for electrically connecting a terminal as a voltage output terminal of an IC and a first terminal of an inductor component to each other and a second through-hole conductor provided in the substrate as a second lead for electrically connecting a terminal as a switching terminal of the IC and a second terminal of the inductor component to each other oppose each other in a direction intersecting a direction in which the first and second terminals oppose each other in the inductor component (i.e., the longitudinal direction of the substrate and inductor component).

Abstract: A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

Abstract: A chip element according to this invention can reduce the influence of parasitic capacitance and parasitic inductance when used in a GHz band. A substrate is formed of a low permittivity material having a permittivity low enough to reduce parasitic capacitance in a GHz band. Parasitic capacitance inherent to the chip element is reduced.

Abstract: An electronic substrate includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed.

Abstract: A pre-drilled hole, providing a passageway between an upper and a lower surface of a printed circuit board layer, receives a passive component, for example a resistor or a capacitor. In one embodiment the component is cylindrical, with an electrically conductive contact point at each end. The hole diameter is approximately the same as the diameter of the cylindrical component. The hole is similar to a via in a printed circuit board, except that the hole is not plated through (such would cause an electrical short). Electrically conductive lines are provided to the openings of the hole on the upper and the lower surfaces of the PCB. The area of the exposed end of the cylindrical component and the termination of the conducting line is less than the area of a surface mounted component equivalent to the cylindrical component.

Abstract: An electronic component mounted structure has: a circuit board; two semiconductor elements that are mounted on the circuit board; and an AC coupling capacitor that is operable to cut off signals with a predetermined frequency or less and is provided between the two semiconductor elements. The AC coupling capacitor is mounted on the circuit board such that a part or a whole of the AC coupling capacitor is away from the surface of the circuit board.

Abstract: A flex circuit is populated on one or both sides with plural integrated circuit die. In a preferred mode, the flex circuit is populated with flip-chip die. One side of the flex circuit has a connective facility implemented in a preferred mode with edge connector contacts. The flex circuit is disposed about a substrate to form a circuit module that may be inserted into an edge connector such as ones typically found on a computer board.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: The present invention provides a conductive module used for assembling a magnetic element and an electronic component. The conductive module includes a conductive base, an electronic component and a plurality of conductive units. The electronic component is electrically connected to the conductive base and disposed on one side of the conductive base. The conductive units have respective hollow portions. The conductive units are spaced from each other and fixed on the conductive base such that the hollow portions of the conductive units are aligned with each other to define a channel.

Abstract: Printed wiring boards for communications connectors are provided that include a mounting substrate having at least first through third input terminals and first through third output terminals. A first conductive path connects the first input terminal to the first output terminal, a second conductive path connects the second input terminal to the second output terminal and a third conductive path connects the third input terminal to the third output terminal. A first inductor and a first capacitor are coupled between the first conductive path and the second conductive path, where the first inductor and the first capacitor are arranged in series to provide a first series inductor-capacitor circuit. A second capacitor is coupled between the third conductive path and the second conductive path through the first inductor to provide a second series inductor-capacitor circuit that shares the inductor of the first series inductor-capacitor circuit.

Abstract: A printed circuit board includes a source interconnect and a ground interconnect, and the circuit board has a two-dimensional geometry having a corner. Protruding portions are provided in circumferences of the source interconnect and the ground interconnect in regions except the corner in plan view, and the source interconnect and the ground interconnect are connected to a common first decoupling capacitor in each of the protruding portions.

Abstract: A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.

Abstract: A circuit board including a first patterned metal layer and a second patterned metal layer is provided. The first patterned metal layer has metal blocks and spiral structures. A gap is kept between any two adjacent metal blocks. Each of the spiral structures is electrically connected between any two adjacent metal blocks. The second patterned metal layer is disposed beside the first patterned metal layer and has jumper segments. Each of the jumper segments has a first end and a second end opposite to the first end. Each of the spiral structures has an outer end and an inner end. The outer end is connected to one of the two adjacent metal blocks. The inner end is electrically connected to the first end of one of the jumper segments, and the second end of the jumper segment is electrically connected to the other one of the two the metal blocks.

Abstract: A semiconductor memory card includes a semiconductor memory, a controller, input/output terminals, resistive elements, first wires, and second wires. The semiconductor memory is mounted on one surface of a substrate. The controller is mounted on the other surface of the substrate and controls the semiconductor memory. The input/output terminals input and output signals to and from the semiconductor memory via the controller. The resistive elements electrically connect input/output terminals to the controller. The first wires connect one-side ends of each of the resistive elements to the controller and each of which has a wire length of 4.0 mm or less. The second wires connect the other-side ends of each of the resistive elements to the input/output terminals.

Abstract: This invention provides a small package board integrated with power supply capable of supplying a low level of voltage and high level of current to an IC while achieving a low height of its power supply. It becomes hard to saturate an inductor magnetically when the surface of a copper wire is coated with a magnetic layer, and the inductor can accordingly be provided with a sufficient degree of inductance. A multiplicity of inductors can be provided within a confined space by arranging a multiplicity of inductors in parallel, and by fixing them with resin so as to form an inductor array, thereby making it possible to divide a power supply. The number of power supply lines is increased by dividing the power supply so as to reduce the level of current in an individual power supply line, so that a high level of current can be supplied to an IC chip.

Abstract: A touch panel includes a light-transmissible upper board, a lower board, an upper resistor layer on a lower surface of the upper board, a lower resistor layer provided on an upper surface of the lower board and facing the upper resistor layer with a predetermined space between the resistor layers, a wiring board having an end located between the upper board and the lower board, plural wiring patterns provided on the wiring board and connected to the upper resistor layer and the lower resistor layer, respectively, and an insulating cover sheet provided on the wiring board and covering the wiring patterns. The cover sheet extends to an inside beyond at least one of respective ends of the upper board and the lower board. This touch panel can be electrically connected to an electronic circuit stably.

Abstract: A copper-clad laminate with a capacitor, a printed circuit board having the same and a semiconductor package having the printed circuit board are presented. The copper-clad laminate with the capacitor includes a first and second conductive layers, a film body, and thickness uniformity improving members. The first and second conductive layers are aligned to be substantially in parallel to each other and thus oppose each other. The film body is interposed between the first and the second conductive layer. The thickness uniformity improving members are also interposed between the first and second conductive layers and are inserted within the film body. The thickness uniformity improving members have one end connected to the first conductive layer and have the opposing ends connected to the second conductive layer.

Abstract: The embedded capacitor of the present invention contains a power plate, a ground plate, and a dielectric layer vertically sandwiched between the power and ground plates. Both the power and ground plates are divided laterally into a number of smaller plates with appropriate gaps therebetween; and, as such, cracks in the dielectric layers are limited to happen between gaps only. The smaller plates are then electrically connected by connectors in the gaps. The connectors for the power plate and the connectors for the ground plate are not vertically overlapped so that they do not appear simultaneously at the two ends of the cracks simultaneously.

Abstract: A solderless electronic component or capacitor mount assembly including a housing having a base portion and a cover portion. The cover portion and base portion being couplable to each other so as to secure a capacitor to the housing. The assembly further including at least one connector configured to couple the assembly to a printed circuit board, and at least one electrical contact configured to contact a respective at least one lead of the capacitor and provide an electrical connection for the capacitor.

Abstract: A printed circuit board (‘PCB’) with a capacitor integrated within a via of the PCB, the PCB including layers of laminate; a via that includes a via hole traversing layers of the PCB, the via hole characterized by a generally tubular inner surface; a capacitor integrated within the via, the capacitor including two capacitor plates, an inner plate and an outer plate, the two plates composed of electrically conductive material disposed upon the inner surface of the via hole, both plates traversing layers of the laminate, the inner plate traversing more layers of the laminate than are traversed by the outer plate; and a layer of dielectric material disposed between the two plates.

Abstract: An assembly integrating commercially available capacitors into filtered feedthroughs. A feedthrough assembly comprises a plurality of Input/Output (I/O) conductors, wherein the I/O conductors pass through a hermetic seal such that a first end of the I/O conductors reside on a non-hermetic side of the hermetic seal and a second end of the I/O conductors reside on a hermetic side of the hermetic seal, a printed circuit interconnect substrate residing on the hermetic side of the hermetic seal, and a plurality of ceramic chip capacitors mounted on the printed circuit interconnect substrate, wherein a first end of each capacitor is connected via the interconnect to the second end of an I/O conductor and a second end of each capacitor is connected via the interconnect to a constant voltage level.

Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.

Abstract: A stable electrical component includes a carrier substrate and a chip (2) mounted thereon. The component has a reactance element and a supporting element, which are at least partly arranged between the carrier substrate and the chip. The reactance element is at least partly realized by means of at least one conductor track. The reactance element includes a coil, a capacitor or a transmission line.

Abstract: A chip package structure with a shielding cover includes a substrate, a chip, a pair of first passive components, a pair of second passive components, and a shielding cover. The chip, the pair of first passive components, the pair of second passive components, and the shielding cover are disposed on the substrate. The chip is electrically connected to the substrate. The shielding cover covers the chip and has leads connected to the substrate. The leads include a first lead and a second lead. The first lead connected to a portion of the substrate is located between the pair of first passive components and arranged along a first axis with the pair of first passive components. The second lead connected to a portion of the substrate is located between the pair of second passive components and arranged along a second axis with the pair of second passive components.

Abstract: A method for conserving space in a circuit or on a printed circuit board by integrating a plurality of electronic components so that the plurality of electronic components collectively take up a smaller amount of space on a substrate than the plurality of electronic components would if the plurality of electronic components were not integrated.

Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

Abstract: A coreless substrate includes a stiffener material (110, 210, 620) having a plated via (120, 320) formed therein, an electrically insulating material (130, 230, 830) above the stiffener material, and an electrically conductive material (140, 240, 840) in the electrically insulating layer. In the same or another embodiment, a package for a microelectronic device includes a stiffener material layer (115, 215, 615) having plated vias (120, 320) formed therein and further having a recess (118, 218) therein, build-up layers (150, 350, 850) over the stiffener material layer, and a die (370) attached over the build-up layers. The stiffener material layer and the build-up layers form a coreless substrate (100, 380, 910, 920) of the package. The coreless substrate has a surface (381), and the die covers less than all of the surface of the coreless substrate such that the surface has at least one exposed region (382).

Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: A DC-DC converter comprising a soft-magnetic, multi-layer substrate provided with a laminated coil constituted by connecting pluralities of conductor lines, and a semiconductor integrated circuit device comprising a switching device and a control circuit, which are mounted on the soft-magnetic, multi-layer substrate; the semiconductor integrated circuit device comprising an input terminal, an output terminal, a first control terminal for controlling the ON/OFF of the switching device, a second control terminal for variably controlling output voltage, and pluralities of ground terminals; the soft-magnetic, multi-layer substrate comprising first external terminals formed on a first main surface, first connecting wires formed on the first main surface and/or on nearby layers, second connecting wires formed between the side surface of the multi-layer substrate and a periphery of the laminated coil, and second external terminals formed on a second main surface; and terminals of the semiconductor integrated circuit

Abstract: Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Abstract: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including a semiconductor chip (10), mounted on the substrate (12). Each of the plurality of semiconductor packages (11a, 11b) includes a first radio communication element (16) for transmitting and receiving a signal between the semiconductor chips (10) in the plurality of semiconductor packages (11a, 11b) by radio communication, and the first radio communication element (16) is constituted independently of the semiconductor chip (10).

Abstract: A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract: An IC device has a compact design. Capacitors, resistances and inductances are directly integrated in the IC device without packaging in advance. Thus, the IC device obtained has a slim size and an electric apparatus using the IC device has a big space for use.