Abstract: An edge connector includes, a multilayer printed board having an inner layer and a connector edge, an electronic circuit disposed on the multilayer printed board, an electrical terminal on the multilayer printed board and spaced by a predetermined clearance from the connector edge, an electrical conductor on the multilayer printed board and connected between the electronic circuit and the electrical terminal, a via connected to the electrical terminal and extending to the inner layer of the multilayer printed board, and a lead conductor on the inner layer of the multilayer printed board and connected at one end to the via, another end of the lead conductor being exposed at the connector edge. The electrical terminal is plated. The sum of the length of the via and the length of the lead conductor is less than one-sixth of the wavelength of an electrical signal transmitted.

Abstract: A process used during manufacture of printed circuit boards comprises protecting metal pads and/or through-holes to provide a tarnish-resistant and solderable coating. In the method, the pads and/or through-holes are bright-etched, metal plated, preferably by an immersion process, and treated with a tarnish inhibitor. The tarnish inhibitor may be incorporated into the immersion plating bath. The metal plating is usually with silver or bismuth and the pads and/or through-holes comprise copper.

Abstract: A multi-layered circuit board is provided having a buried capacitive layer and a device-specific embedded, localized, non-discrete, and distributive capacitive element. A printed circuit board is provided including (1) a first dielectric layer, (2) a first conductive layer coupled to a first surface of the first dielectric layer, (3) a second conductive layer coupled to a second surface of the first dielectric layer, and (4) a localized distributive non-discrete capacitive element adjacent the first conductive layer, wherein the capacitive element occupies a region that approximately coincides with a location over which a device to be coupled to the capacitive element is to be mounted. The embedded, localized, non-discrete, and distributive capacitive element may provide device-specific capacitance to suppress voltage/current noise for a particular device.

Abstract: An assembly includes a substrate, a chip mounted on the substrate, a voltage controlled oscillator circuit including an inductor and further circuit elements. The inductor is mounted on or in the substrate, and the further circuit elements are mounted on or in the chip. An assembly is disclosed that includes a substrate including a first metallization plane and a second metallization plane, a chip mounted on the substrate, and an inductor mounted on or in the substrate. The inductor includes a first inductor portion in the first metallization plane and a second inductor portion in the second metallization plane. An assembly is also disclosed including a substrate, a chip mounted onto the substrate, and a transformer formed at least in part on or in the substrate.

Abstract: Provided in some embodiment is a thermocouple system that includes a printed circuit board having a terminal component connection to couple to a connector of a terminal component, a temperature sensing component connection to couple to a connector of a temperature sensing component, a signal plane thermally coupled to the terminal component connection, and a thermal plane thermally coupled to the temperature sensing component connection and electrically isolated from the terminal component connection and the signal plane. The surface area of the thermal plane overlaps a substantial portion of a surface area of the signal plane.

Abstract: A circuit arrangement is provided that includes at least one semiconductor component, at least one filter arrangement, which has at least two discretely made coil elements, which are disposed adjacent to one another with parallel aligned magnetic field axes, and a contacting unit, which has electrical traces for an electrically conductive connection of the semiconductor component to the filter arrangement. A thickness of the semiconductor component is at least 20% of a thickness of the coil elements.

Abstract: A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material.

Abstract: A power converter apparatus that includes a substrate, plate-like positive and negative interconnection members, capacitors, and a cover is disclosed. Pairs of groups of switching elements are mounted on the substrate. The cover is arranged over the substrate to encompass the switching elements, the positive interconnection member, the negative interconnection member, and the capacitor. The positive interconnection member and the negative interconnection member each have a terminal portion that is joined to a circuit pattern on the substrate by ultrasonic bonding.

Abstract: One embodiment of the present invention provides a system that reduces power consumption by using capacitive coupling to perform a majority detection operation. The system starts by driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. Next, the system feeds signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The system then uses the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by the computer system.

Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Abstract: According to one embodiment, a module includes a circuit substrate having a circuit pattern which is formed of a first conductor and which includes a signal circuit, a bonding member formed of a second conductor different from the first conductor, a passive element and an active element bonded to the circuit pattern with the bonding member to implement the circuit substrate, and a detection circuit provided separately from the signal circuit on the circuit substrate. The detection circuit includes a detector having the first conductor and the second conductor which are provided on the circuit substrate and which are electrically connected to each other, a power source configured to supply current to the detector, and a measuring instrument interposed between one of the first and the second conductors in the detector and the power source and configured to measure electrical characteristics between the first and the second conductors.

Abstract: A power conversion apparatus comprising a base 110 which includes a first fixation portion 110a and a second fixation portion 110b that are coupled to each other at a desired angle, wherein power modules IPM1, IPM2 and IPM3 are fixed on the first fixation portion 110a of the base 110, a control circuit board 10 is fixed with its first principal surface 10a held in direct or indirect touch with the second fixation portion 110b of the base 110, and components constituting a control circuit are packaged on the second principal surface 10b of the control circuit board 10. Owing to the configuration, a versatility for the installation of the power conversion apparatus on a vehicle becomes high, the vibration-proofness of the control circuit board is enhanced, and heats generated by the electronic components, etc. packaged on the control circuit board are sufficiently emitted.

Abstract: In a structure for mounting a first feedthrough capacitor and a second feedthrough capacitor on a mounting surface of a substrate, the first and second feedthrough capacitors are disposed so as to be substantially parallel and to face each other in their partial regions, and a current in the partial region of the first feedthrough capacitor flows in a direction opposite to that in the partial region of the second feedthrough capacitor.

Abstract: A passive RF tag has an advantage of being compact and lightweight. However, the driving power is limited. In order to increase the maximum communication distance and the number of objects simultaneously identified, power consumption should be efficient and reduced. The semiconductor device includes an antenna circuit, a modulation circuit electrically connected to the antenna circuit, a filter circuit electrically connected to the modulation circuit, and a logic circuit electrically connected to the filter circuit, in which the modulation circuit includes a first resistor and a transistor, the filter circuit includes a capacitor, one terminal of the first resistor is electrically connected to one of a source and a drain of the transistor, the other terminal of the first resistor is electrically connected to the antenna circuit, and a gate of the transistor is electrically connected to one terminal of the capacitor and the logic circuit.

Abstract: An encapsulated buck converter module includes a low side transistor and a control integrated circuit bonded to a first section on a first side of a leadframe, a first clip between a source of the low side transistor and a second section, a source contact of a high side transistor attached to the first section on a second side of the leadframe with a gate contact of the high side transistor attached to a third section, a conductive member attached to the first and second sections on the second side of the leadframe wherein the first side of the conductive member attached to the second conductive member forms a conductive path with a portion of a second side of the conductive member while any portion of the first side of the conductive member attached to the first component attachment section is insulated from the first side of the conductive member, a first plate of a capacitor attached to a drain contact of the high side transistor and a second plate of the capacitor attached to the second side of the conduc

Abstract: An electronic circuit is obtained that has reduced EMI levels. The circuit includes an integrated circuit, which is a source of noise, a bypass capacitor, and a circuit substrate on which they are mounted. An electronic circuit one electrode terminal of the bypass capacitor and one connecting electrode of the integrated circuit are connected through a first wire interconnect formed in the circuit substrate, and, additionally, another electrode terminal of the bypass capacitor and another connecting electrode of the integrated circuit are connected through a second wire interconnect, and the gap between the first wire interconnect and the second wire interconnect is made smaller than either the gap between the one connecting electrode and the other connecting electrode on the integrated circuit or the gap between the one electrode terminal and the other electrode terminal of the bypass capacitor.

Abstract: A power converter apparatus includes a substrate 22 on which switching elements Q, Q1 to Q6 are mounted, positive and negative terminal interconnection members 27, 28 mounted on the substrate, and a capacitor 17 having a positive terminal 17a connected to the main body of the positive terminal interconnection member 27 and a negative terminal 17b connected to the main body of the negative terminal interconnection member 28. The interconnection members each have a plate-like main body 27a, 28a that is located above and parallel to the substrate 22. The main bodies of the interconnection members are stacked to be close to each other while being electrically insulated from each other. Each of the positive terminal interconnection member and the negative terminal interconnection member further includes a plate-like extension 27b, 28b that extends from the corresponding main body toward the substrate, and a terminal portion 27c, 28c that extends from the extension and is joined to the substrate.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated.

Abstract: An exemplary patch panel includes a printed circuit board having a plurality of input terminals and output terminals. An amount of the input terminals is equal to an amount of the output terminals. The input terminals are connected to the output terminals respectively. The printed circuit board further includes a plurality of standby terminals. Each of the input terminals is connected to the standby terminals via switches respectively. The standby terminals can be used to selectively replace a number of the input terminals or the output terminals, should they become inoperable, by operating the switches.

Abstract: A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.

Abstract: A multilayer circuit board (1) includes resin bases (101 to 10N) stacked while placing separators (121 to 12N?1) in between, interconnect patterns (111 to 11N) respectively formed on one surface of each of the resin bases (101 to 10N), and electro-conductive bumps (201 to 20N?1) which electrically connect the interconnect patterns (111 to 11N). The resin bases (101 to 10N) and the separators (121 to 12N?1) are heat-bonded, the separators (121 to 12N?1) are composed of a first thermoplastic resin material having a first glass transition temperature, and the resin bases (101 to 10N) are composed of a second thermoplastic resin material having a second glass transition temperature higher than the first glass transition temperature.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: Embodiments of the present invention provide an electronic device. The electronic device includes a circuit board. A first circuit is disposed on a first side of the circuit board. The first circuit is connected to a first ground plane of the circuit board. A second circuit is disposed on a second side of the circuit board. The second side is opposite the first side, and the second circuit is connected to a second ground plane of the circuit board. Moreover, the first and second ground planes respectively lie in different planes of the circuit board and are electrically interconnected by a conductive trace disposed within the circuit board.

Abstract: A mountable electronic circuit module which produces appropriate characteristics without a complicated structure can be a DC-DC converter including a baseboard made of a magnetic material. A helical electrode is provided in the baseboard so as to function as a smoothing inductor device. Capacitor devices in addition to a DC-DC converter IC are mounted on a main surface of the baseboard. A circuit electrode arranged to connect the circuit devices is provided to enable the circuit devices to function as the DC-DC converter. The DC-DC converter is mounted on a motherboard through external connection electrodes of the capacitor devices.

Abstract: A method having a socket for coupling signals between an electrical component and a circuit board or equivalent has a mechanism that, when activated, attaches the electrical component to the socket so that it is not possible to remove the electrical component without damaging it. The mechanism may include a clamshell lid with a one-time locking mechanism, a pin contact mechanism that, after initial locking, will detach the pins of the electrical component if further disturbed, or a moat around the base of the electrical component for disposing an epoxy fastener. The moat may include a heating element to cure the epoxy or other glue. The socket may include an electrical component that allows detection of tampering with the socket.

Abstract: A semiconductor memory module having a reverse mounted chip resistor, and a method of fabricating the same are provided. By reverse mounting the chip resistor on the semiconductor memory module, the resistive material is protected, thereby preventing open circuits caused by damage to the resistive material. Also, a chip-resistor connection pad of a module substrate is formed to extend higher from the module substrate than other connection pads connected to other elements. Thus, the resistive material of the chip resistor does not contact the module substrate, thereby preventing poor alignment and defective connections.

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 id constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

Abstract: A passive component incorporating interposer includes a double-sided circuit board (1) having a wiring layer (8) on both sides, a passive component (2) mounted on the wiring layer (8) on one surface of the double-sided circuit board (1), a second insulating layer (3) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the surface of the double-sided circuit board (1) mounted with the passive component (2), a first insulating layer (4) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the other surface of the double-sided circuit board (1) not mounted with the passive component (2), first and second wiring layers (5, 6) formed on the first and second insulating layers (3, 4), and a through hole (7) for electrically connecting the wiring layers (8) disposed on both surfaces of the double-sided circuit board (1) and the first and second wiring layers (5, 6), where the first wiring layer (5) is formed to enable mounting

Abstract: A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips.

Abstract: A package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract: Electrical components, such as packaged integrated circuit devices that are mountable on a substrate surface, are provided with at least one exposed electrical contact on a side surface of the component that will be substantially perpendicular to the substrate surface when the component is mounted. Two such components can be mounted side-by-side on the substrate surface with the above-mentioned contacts close to one another between the above-mentioned side surfaces. An electrical connection between the contacts can be made (or perfected) by depositing an electrically conductive connector material in contact with both of the contacts between the above-mentioned side surfaces.

Abstract: A tape circuit substrate includes a base film with first wiring and second wiring disposed on the base film. The first wiring extends into a chip mount portion through a first side and bends within the chip mount portion toward a second side. The second wiring extends into the chip mount portion through a third side and bends within the chip mount portion toward the second side. The first, second, and third sides are different sides of the chip mount portion. Thus, size and in turn cost of the base film are minimized by arranging wirings within the chip mount portion for further miniaturization of electronic devices, such as a display panel assembly, using the tape circuit substrate.

Abstract: A compatible circuit for integrated circuits (ICs) includes three input terminals coupled to corresponding pins of an IC, and three function terminals corresponding to the three input terminals. Each input terminal coupled to the three function terminals via three transmission lines, each transmission line has an open segment, and each input terminal is electrically coupled to a corresponding function terminal by selectively mounting a connection component on the open segment of the corresponding transmission line according to a specification of the IC.

Abstract: An electronic component mounting structure which can reduce the ESL while saving the space when mounting electronic components is provided. A first electronic component 7 is electrically connected to surface-mounted electrode parts 11A, 12A at metal terminals 26, 27 such that a first capacitor 24 having a greater capacitance and a mounting surface 4a of a multilayer substrate 4 are separated from each other. A second electronic component 8 is arranged between the first capacitor 24 and the mounting surface 4a and electrically connected to surface-mounted electrode parts 12B, 11B at second terminal electrodes 32, 33. The second electronic component 8 overlaps the first capacitor 24 when seen in the laminating direction. The first electronic component 7 is mounted to the multilayer substrate 4 such that first terminal electrodes 22, 23 oppose each other in a predetermined direction D1.

Abstract: Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground.

Abstract: A multilayer capacitor 1 comprises a capacitor element body 2 constituted by a plurality of dielectric layers 10; inner electrodes 3, 4, disposed within the capacitor element body 2, having main electrode parts 31, 41 separated by a distance Wg from third and fourth side faces 2c, 2d; and terminal electrodes 5, 6 disposed on respective end faces 2e, 2f and a part of first to fourth side faces 2a to 2d. The inner electrodes 3, 4 are alternately laminated with the dielectric layer 10. The distance Cv between the inner electrode 3, 4 at the outermost layer on each of the first and second side face 2a, 2b sides and the first or second side face 2a, 2b adjacent to the inner electrode 3, 4 is shorter than the distance Wg between the main electrode part 31, 41 and the third or fourth side face 2c, 2d.

Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates.

Abstract: A printed circuit board includes a board body, a number of filtering capacitors, and a chip. The board body includes a chip mount area. The chip mount area includes a first area and a second area. The first and second areas each include a number of pads. The second area is surrounded by the first area. The pads of the second area are electrically connected to pins of the number of filtering capacitors. The pads of the first area are electrically connected to pins of the chip. The number of filtering capacitors is sandwiched between the chip and the second area.

Abstract: An apparatus and method of improving power noise of a Ball Grid Array (BGA) package are provided. The method includes securing a space for a passive element mounting pad, on which a passive element can be mounted, adjacent to a power pad on a Printed Circuit Board (PCB) corresponding to a power pin of the BGA package, mounting the passive element on the passive element mounting pad, and mounting the BGA package at a position on the PCB, wherein the position on the PCB overlaps the passive element and further wherein the BGA package is mounted above the passive element.

Abstract: An exemplary circuit board includes a plate body and a multilayer capacitor installed on a surface of the plate body. The multilayer capacitor includes a multilayer body and two outer electrodes located at the two opposite ends of the multilayer body. The multilayer body includes a plurality of ceramic layers and a plurality of internal electrodes alternately arranged. The two outer electrodes are connected to the plate body, and a stacking direction of the multilayer body is substantially parallel to the surface of the plate body.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: A manufacturing technique for constructing passive electronic components in vertical configurations is disclosed. Electrically passive components are constructed in a structure that is substantially perpendicular to target platform including a first plane to provide a larger electrode contact area and a smaller physical dimension. Passive components structured to be substantially perpendicular to a plane associated with a target platform can be directly connected to pad contacts of an integrated circuit or substrate or can be embedded in a package to reduce the area overhead of a passive component while improving the effectiveness of the passive components in their applications.

Abstract: A manufacturing method for manufacturing an electronic device is disclosed. Conductive elastomers comprising of various configurations and resistivity are coupled to contact pads of an electronic device. The conductive elastomers are also coupled to substrate contacts on a substrate, allowing the conductive elastomers to function as electrical connection from device to substrate as well as to embed one or more passive components at the contact pads of the electronic device.

Abstract: Variably oriented capacitive elements for printed circuit boards (PCBs) and method of manufacturing the same. In one form the disclosure, a PCB can include a first multiple-layered capacitor including a first orientation and placed along a surface operable to mount electronic components. The PCB can also include a second multiple-layered capacitor including a second orientation different from the first. The second multiple-layered capacitor can be placed along the surface near the first multiple-layered capacitor.

Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.

Abstract: There is provided a variable device circuit according to the present invention, including: a substrate; at least one movable switch device formed on a first principal surface of the substrate; at least one fixed capacitor device formed on the first principal surface of the substrate; at least one variable capacitor device formed on the first principal surface of the substrate; at least one variable inductor device formed on the first principal surface of the substrate; and wiring lines for electrically connecting the devices to one another, the wiring lines being formed on the first principal surface of the substrate; wherein electrical connections among the devices can be selected by operation of the movable switch device, whereby achieving stable, low-loss circuit characteristics with lower manufacturing cost.

Abstract: An interposer with which the manufacturing steps are able to be simplified and which shows superior high frequency characteristics is provided. The interposer includes: a substrate having a front face and a rear face; a wiring that is formed on the front face side of the substrate and is electrically connected to a semiconductor chip; an electric device connected to the wiring; and a concave section that is formed from the rear face side of the substrate in a position corresponding to the electric device.