Having Passive Component Patents (Class 361/782)
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Publication number: 20120147579Abstract: A printed circuit board includes a high-speed differential signal control chip, first to eighth coupling capacitor pads, first to fourth connector pads, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, first to eighth transmission lines, two ninth transmission lines, first and second vias, and first to fourth sharing pads. The printed circuit board is operable to selectively support multiple connectors.Type: ApplicationFiled: December 24, 2010Publication date: June 14, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHENG-HSIEN LEE, YUNG-CHIEH CHEN, SHOU-KUO HSU, SHIN-TING YEN
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Publication number: 20120147580Abstract: A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.Type: ApplicationFiled: February 16, 2012Publication date: June 14, 2012Applicant: CANON KABUSHIKI KAISHAInventor: Seiji Hayashi
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Patent number: 8198538Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.Type: GrantFiled: February 25, 2009Date of Patent: June 12, 2012Assignee: Industrial Technology Research InstituteInventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang, Ray-Fong Hong
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Patent number: 8194412Abstract: A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ? 8 ? Wpad + 10 ? T 0.8 ? Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.Type: GrantFiled: December 25, 2009Date of Patent: June 5, 2012Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Hua-Li Zhou, Chia-Nan Pai, Shou-Kuo Hsu
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Patent number: 8194415Abstract: A light-emitting diode element including a through hole and a thermal via hole is mounted. An electrical connection region and a heat radiation region with respect to a plurality of packages or substrates are separately mounted on a printed circuit board. Electrical connection is made in the printed circuit board, and a driver, a resistance, a capacitor, and the like are connected. Heat is diffused and radiated by heat transport to a heat radiation base material connected to the printed circuit board.Type: GrantFiled: October 10, 2008Date of Patent: June 5, 2012Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventor: Toshiaki Tanaka
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Patent number: 8184448Abstract: A PCB having an embedded bare chip includes an insulated substrate having a penetration hole formed therein; a filler filling up an inside of the penetration hole; a bare chip embedded in the filler such that electrode pads formed on one side thereof are exposed at the surface of the filler; and an electrode bump attached to a surface of the electrode pads and protruded to be exposed to the outside.Type: GrantFiled: February 8, 2007Date of Patent: May 22, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kyung-Jin Han, Hyung-Tae Kim, Moon-Il Kim, Jae-Kul Lee, Doo-Hwan Lee
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Patent number: 8179688Abstract: An electric device includes: a first electric element; a second electric element capable of flowing large current therethrough so that heat is generated in the second electric element; a heat sink; and a first wiring board and a second wiring board, which are disposed on one side of the heat sink. The large current in the second electric element is larger than that in the first electric element. The first wiring board and the second wiring board are separated each other. The first electric element is disposed on the first wiring board, and the second electric element is disposed on the second wiring board.Type: GrantFiled: October 19, 2010Date of Patent: May 15, 2012Assignee: DENSO CORPORATIONInventors: Yutaka Fukuda, Mitsuhiro Saitou, Toshihiro Nagaya, Kan Kinouchi, Sadahiro Akama, Koji Numazaki, Norihisa Imaizumi
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Patent number: 8174842Abstract: A light-emitting diode (LED) module includes a plurality of LED units and a converter having a first side. The LED units respectively include a circuit board having a second side perpendicular to the first side and a third side parallel to the first side, a plurality of LEDs positioned on the circuit board, and a connector positioned on the second side proximal to the converter. The LED module further includes a plurality of flexible flat cables (FFCs) used to electrically connect the connectors to the converter, respectively.Type: GrantFiled: July 1, 2009Date of Patent: May 8, 2012Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Hung-Yi Ou Yang, Wen-Yu Lin
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Publication number: 20120106110Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.Type: ApplicationFiled: November 29, 2011Publication date: May 3, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shinji MORIYAMA, Tomio YAMADA
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Patent number: 8169790Abstract: An electromagnetic bandgap structure and a printed circuit board having the electromagnetic bandgap that intercepts the transfer of a signal ranging a frequency band are disclosed. The electromagnetic bandgap structure includes a metal layer; a dielectric layer, stacked on the metal layer; at least two metal plates, stacked on the same planar surface of the dielectric layer; and a stitching via, connecting the adjacent metal plates. The stitching via passes through the dielectric layer, and a part of the stitching via is placed on the same planar surface of the metal layer. With the present invention, the electromagnetic bandgap can decrease the noise of a particular frequency by having a compact size and a low bandgap frequency.Type: GrantFiled: January 25, 2008Date of Patent: May 1, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Han Kim, Je-Gwang Yoo, Chang-Sup Ryu
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Publication number: 20120099288Abstract: An electrical component for surface mounting, such as a DC-DC power converter includes a body portion including one or more surface mounting pins to connect the body portion to a circuit board, and first and second circuit boards including respective circuit elements mounted thereon. The first and second circuit boards are mounted on the body portion, such that sides of the first and second circuit board on which the circuits are mounted face the interior of the device and the reverse sides of the first and second circuit boards define an exterior surface of the component. In this way, no separate housing for the component is required. The size of the electrical component can therefore be kept small, and protection provided to the circuit elements by the reverse side of the circuit board.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Applicant: MURATA POWER SOLUTIONS (MILTON KEYNES) LIMITEDInventor: Scott PARISH
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Publication number: 20120092350Abstract: This disclosure provides systems, methods and apparatus for a combined sensor device. In some implementations, a combined sensor device includes a wrap-around configuration wherein an upper flexible substrate has patterned conductive material on an extended portion to allow routing of signal lines, electrical ground, and power. One or more integrated circuits or passive components, which may include connecting sockets, may be mounted onto the flexible layer to reduce cost and complexity. Such implementations may eliminate a flex cable and may allow a bezel-less configuration.Type: ApplicationFiled: October 11, 2011Publication date: April 19, 2012Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.Inventors: Srinivasan Kodaganallur Ganapathi, Nicholas Ian Buchan, Kurt Edward Petersen, Ravindra V. Shenoy, Peng Cheng Lin, Ericson Cheng
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Patent number: 8159832Abstract: A folded EBG structure has a plurality of cells arranged in a two-dimensional array. Each of the cells has an electrically conductive patch and an electrically conductive via coupled between the patch and a ground plane. In one dimension of the folded EBG structure, at least one patch in that dimension is folded into three sections located in different planes. In general, both ends of the folded EBS structure have folded patches. Via walls having electrically conductive vias are provided on both ends of a folded EBG structure for connecting the cell vias to the ground plane. The distance between each via wall and the folded EBGs is substantially equal to the length of the vias connected to patches.Type: GrantFiled: September 21, 2007Date of Patent: April 17, 2012Assignee: Nokia CorporationInventors: Ali Nadir Arslan, Mikko Ville Samuli Hurskainen
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Publication number: 20120081869Abstract: There is provided a printed circuit board for reducing crosstalk, having a capacitive impedance component connected between signal and ground patterns, the printed circuit board including: signal patterns including a first signal pattern transferring low frequency signals and a second signal pattern transferring high frequency signals; ground patterns including a first ground pattern connected to the first signal pattern and a second ground pattern connected to the second signal pattern which are separated from each other; and a conductive shielding film connected between the first and second ground patterns and shielding electromagnetic waves generated from the printed circuit board. Accordingly, crosstalk between the low and high frequency signals may be reduced.Type: ApplicationFiled: October 3, 2011Publication date: April 5, 2012Inventors: Yoon Dong KIM, Hee Soo Yoon, Jong Lae Kim, Su Bong Jang, Dong Hwan Lee, Kyoung Ho Lee
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Publication number: 20120081870Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.Type: ApplicationFiled: November 9, 2011Publication date: April 5, 2012Applicant: Kemet Electronics CorporationInventors: Michael S. Randall, Garry Renner, John D. Prymak, Azizuddin Tajuddin
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Patent number: 8149585Abstract: Means for Solution: This interposer (10) comprises the silicon substrate (12), a plurality of through-hole conductors (20) formed on the above-described silicon substrate, and a capacitor (15) formed with the upper electrodes (14) and the lower electrodes (18) formed by extending the land portions of the above-described through-hole conductors and the dielectric layer (16) formed between the both electrodes. The rewiring layers (23-1, 23-2) formed as desired are formed on the layers other than the above-described capacitor layer.Type: GrantFiled: September 24, 2007Date of Patent: April 3, 2012Assignee: Ibiden Co., Ltd.Inventor: Shuichi Kawano
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Publication number: 20120074521Abstract: A method of manufacturing a capacitor includes forming a first ceramic film on a first base made of a metal, forming a second ceramic film on a second base made of a metal, forming a first copper electrode pattern and a first copper via-plug on a surface of one of the first and second ceramic films, the electrode pattern and the via-plug being separate from each other, bonding the first and second ceramic films together with the first electrode pattern and the via-plug therebetween, by applying a pulsed voltage between the first base and the second base while the first base and the second base are pressed so that the first ceramic film and the second ceramic film are pressed on each other, and removing the second base.Type: ApplicationFiled: September 8, 2011Publication date: March 29, 2012Applicant: FUJITSU LIMITEDInventors: Yoshihiko Imanaka, Hideyuki Amada, Fumiaki Kumasaka
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Publication number: 20120075820Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Applicant: AMERICAN TECHNICAL CERAMICS, CORP.Inventor: John Mruz
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Patent number: 8144481Abstract: A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.Type: GrantFiled: December 8, 2009Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Joo Park, Ki-Hyun Ko, Myung-Hee Sung
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Patent number: 8143696Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.Type: GrantFiled: March 18, 2009Date of Patent: March 27, 2012Assignee: Agere Systems Inc.Inventors: Weiwei Mao, Shahriar Moinian, Kenneth Wade Paist, William B. Wilson
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Patent number: 8130510Abstract: Disclosed herein is a printed circuit board assembly of an electronic appliance including a plurality of boards on which electrical parts to perform functions necessary for the electronic appliance are separately arranged according to the specification of the electronic appliance. The printed circuit board assembly is divided into a plurality of boards, such that electrical parts having a common specification and electrical parts having different specifications are arranged on different boards, thereby optimizing the printed circuit board assembly and configuring the boards according to the specification of the electronic appliance without loss. Microprocessors are arranged on the boards, and the boards are connected to each other in a serial communication, thereby reducing the number of wiring harnesses (W/H) and thus configuring the printed circuit board assembly with high reliability.Type: GrantFiled: April 29, 2009Date of Patent: March 6, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Wook Jang, Matsumoto Satoru
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Publication number: 20120051012Abstract: A display device including a front cover and a rear cover coupled to each other in order to receive a display panel, drive board and power supply board, is provided. A shield case mounted on the power supply board and coupled to the rear cover removes noise conducted to the rear cover. The shield case serves to disperse and absorb noise conducted to the rear cover, enabling removal of the noise. A frame ground terminal of a socket is connected to the shield case in order to allow the shield case to be used as a ground, resulting in an increased ground area. Further, the shield case may reduce radiation noise and conduction noise generated during driving of a plurality of drive units provided in the display device.Type: ApplicationFiled: June 28, 2011Publication date: March 1, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Yong JOO, Won Myung WOO, Sung Bum JUNG
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Patent number: 8125058Abstract: An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device. For example, the first Faraday cage portion may include a first conductive portion of a Faraday cage enclosure surrounding the at least one circuit device, and a second Faraday cage portion may include a second conductive portion of the Faraday cage enclosure surrounding the at least one circuit device. Further, for example, the first Faraday cage portion may include a connection surface having one or more conductive contact portions terminating the first conductive portion of the Faraday cage enclosure the second Faraday cage portion may include a connection surface having one or more conductive contact portions terminating the second conductive portion of the Faraday cage enclosure. An electrical connection may be provided between the conductive contact portions of the first and second Faraday cage portions.Type: GrantFiled: September 29, 2009Date of Patent: February 28, 2012Assignee: Medtronic, Inc.Inventors: Tyler Mueller, Larry E. Tyler, Geoffrey Batchelder, Paul F. Gerrish, Michael F. Mattes, Anna J. Malin
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Patent number: 8120925Abstract: A circuit device includes a dielectric substrate including a first face and a second face opposite side of the first face; a coplanar line including a first line, a second line and ground electrodes, the first line and the second line being decupled mutually, the ground electrodes formed around the first line and the second line, the first line, the second line and the ground electrodes formed on the first face of the dielectric substrate; a capacitor for connecting the first line and the second line; a termination resistor connecting the second line; a microstrip line formed on the second face of the dielectric substrate; and a conducting portion formed in the dielectric substrate and electrically connecting the first line and the microstrip line.Type: GrantFiled: March 20, 2009Date of Patent: February 21, 2012Assignee: Fujitsu LimitedInventor: Takehito Tanaka
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Patent number: 8110896Abstract: A capacitor components embedded substrate structure comprises a substrate, capacitor components, a first and second dielectric layers, and a circuit layer. The substrate includes a first surface, a second surface, and a hole penetrating the first and the second surfaces. The capacitor components whose surface is pretreated with a roughness process is received in the hole of the substrate, such that at least one surface of the capacitor components is disposed with a plurality of electrode pads. The first and the second dielectric layers are formed on the surface of substrate and the surface of the capacitor components respectively such that the capacitor components are secured in position in the hole of the substrate. The first and the second dielectric layers have a plurality of openings to expose the electrode pads of the capacitor components.Type: GrantFiled: June 21, 2006Date of Patent: February 7, 2012Assignee: Unimicron Technology Corp.Inventor: Shih-Ping Hsu
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Patent number: 8111524Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates.Type: GrantFiled: February 12, 2008Date of Patent: February 7, 2012Assignee: Kemet Electronics CorporationInventors: Michael S. Randall, Garry Renner, John D. Prymak, Azizuddin Tajuddin
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Publication number: 20120026707Abstract: A printed circuit board includes first and second layers, a control chip, bonding pads, and several electronic elements. The bonding pads can be selectively applied to interconnect the first and second layers, and the control chip with any of the electronic elements in a simple layout.Type: ApplicationFiled: August 31, 2010Publication date: February 2, 2012Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.Inventors: SHI-PIAO LUO, CHIA-NAN PAI, SHOU-KUO HSU
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Patent number: 8107248Abstract: A flexible device and a flexible pressure sensor. The present flexible device includes: a first flexible substrate formed of a flexible material to have a flexibility; an active element formed to have a predetermined thickness and a flexibility, and being attached on the first flexible substrate; and a second flexible substrate formed of a flexible material to have a flexibility, and being deposited on the active element. The flexible device and the flexible pressure sensor have a high flexibility, so that they may be applied for a medical treatment such as implantation to a living body, a human body and so forth. In addition, the flexible device has a high flexibility, so that it may be inserted to a curved surface, which contributes to remove the limit of space where the semiconductor package device may be inserted.Type: GrantFiled: May 5, 2009Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-ho Shin, Chang-youl Moon, Yong-jun Kim
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Publication number: 20120020043Abstract: A printed circuit board includes a signal layer, a power layer, and a ground layer. The signal layer includes an analog audio input/output (I/O) port and an audio chip. The audio chip includes a main body, a first group of signal pins connected to the analog audio I/O port and a second group of signal pins connected to a control chip. The power layer and the ground layer each is divided into two unconnected parts, an audio part and a digital part, by a dividing groove. The two audio parts act as a whole reference plane for traces between the analog audio I/O port and the first group of signal pins of the audio chip. The two digital parts act as reference planes for traces between the control chip and the second group of signal pins of the audio chip.Type: ApplicationFiled: July 26, 2010Publication date: January 26, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: CHENG-SUNG WANG
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Publication number: 20120020041Abstract: A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board.Type: ApplicationFiled: July 12, 2011Publication date: January 26, 2012Applicant: ELPIDA MEMORY, INCInventor: Koji HOSOKAWA
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Publication number: 20120020042Abstract: One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.Type: ApplicationFiled: July 21, 2010Publication date: January 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nickolaus J. Gruendler, Paul M. Harvey, Tae Hong Kim, Sang Y. Lee, Michael J. Shapiro
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Patent number: 8102669Abstract: A chip package structure with a shielding cover includes a substrate, a chip, a pair of first passive components, a pair of second passive components, and a shielding cover. The chip, the pair of first passive components, the pair of second passive components, and the shielding cover are disposed on the substrate. The chip is electrically connected to the substrate. The shielding cover covers the chip and has leads connected to the substrate. The leads include a first lead and a second lead. The first lead connected to a portion of the substrate is located between the pair of first passive components and arranged along a first axis with the pair of first passive components. The second lead connected to a portion of the substrate is located between the pair of second passive components and arranged along a second axis with the pair of second passive components.Type: GrantFiled: July 29, 2009Date of Patent: January 24, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsin-Chieh Lu, Chin-Feng Chou
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Patent number: 8102671Abstract: A first riser card of an apparatus in an example substantially axially connects with a first serial connection external interface of a printed circuit board (PCB) and at least in part laterally connects with a parallel connection external interface of a first memory module. The first riser card supports the first memory module with avoidance of abutment of the first memory module with a second memory module supported by a second riser card that is adjacent to the first riser card.Type: GrantFiled: April 25, 2007Date of Patent: January 24, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Martin Goldstein, Hau Jiun Chen, Mun Hoong Tai, Choon Pheng Tan
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Publication number: 20120014079Abstract: An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.Type: ApplicationFiled: July 19, 2011Publication date: January 19, 2012Applicant: CYNTEC CO. LTD.Inventors: Da-Jung CHEN, Chau-Chun WEN, Chun-Tiao LIU
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Patent number: 8094460Abstract: A land pattern, a method of manufacturing a printed circuit board (PCB) and a PCB incorporating a land pattern. In one embodiment, the land pattern includes: (1) a quadrilateral component outline area having diagonally opposed first and second corners and diagonally opposed third and fourth corners, defined according to a body configuration of a particular component type and located on a surface of a substrate and (2) first and second exposed conductive pads located within said area respectively proximate said first and second corners, coupled to respective first and second circuit conductors of said substrate, configured according to a terminal configuration of said type and separated from said third and fourth corners such that a component of said particular component type may be placed on the land pattern in multiple orientations without causing a short circuit.Type: GrantFiled: January 12, 2009Date of Patent: January 10, 2012Assignee: Alcatel LucentInventors: Brad G. Magnani, Raymond Eng, Susan M. Plul
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Patent number: 8094461Abstract: A printed board includes a printed board body having a first side, a second side opposing the first side, and a through-hole; a printed conductor disposed on the first side of the printed board body; and a bus bar disposed on the second side of the printed board body, the bus bar including a terminal that extends through the through-hole. The terminal includes a plurality of branched terminal portions at a position corresponding to an interior of the through-hole, and at least one of the branched terminal portions is bent and attached to the printed conductor.Type: GrantFiled: August 24, 2007Date of Patent: January 10, 2012Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Masahiro Tagano, Teruyuki Kitahara
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Patent number: 8094462Abstract: Disclosed is a high frequency tuner module, including: a circuit component; signal lines; a GND line; and a multilayer board formed by laminating a plurality of layers, wherein the circuit component is placed on a top layer surface of the multilayer board; the signal lines and the GND line are formed inside the multilayer board; and among the signal lines, high frequency signal transmitting signal lines to transmit a high frequency signal are formed on a single layer inside the multilayer board.Type: GrantFiled: November 28, 2007Date of Patent: January 10, 2012Assignee: Mitsumi Electric Co., Ltd.Inventors: Shozo Miyamoto, Makoto Abe
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Publication number: 20120002388Abstract: To provide a microwave/milliwave band high-frequency pulse signal generating device that enables realization of structural simplification, high performance, compact integration, easy design, low power consumption, and low cost.Type: ApplicationFiled: October 6, 2009Publication date: January 5, 2012Applicants: COMMUNICATIONS RESEARCH LABORATORY, INC., NATIONAL INS. OF INFO. AND COMMUNICATIONS TECH.Inventors: Hitoshi Utagawa, Toshiaki Matsui
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Publication number: 20110317387Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: QUALCOMM IncorporatedInventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Patent number: 8085549Abstract: The circuit device includes a first transmitting inductor, a first insulating layer, a first receiving inductor, and a second receiving inductor. The first transmitting inductor is constituted of a helical conductive pattern and receives a transmitted signal. The first receiving inductor is located in a region overlapping the first transmitting inductor through the first insulating layer. The first receiving inductor is constituted of a helical conductive pattern, and generates a received signal corresponding to the transmitted signal input to the first transmitting inductor. The second receiving inductor is connected in series to the first receiving inductor, and constituted of a helical conductive pattern. The second receiving inductor generates a voltage in an opposite direction to that generated by the first receiving inductor, in response to a magnetic field of the same direction.Type: GrantFiled: June 5, 2009Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Masaya Kawano, Yasutaka Nakashiba
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Patent number: 8085547Abstract: An electronic elements carrier includes a body, at least an electronic element and a filler. The body includes a substrate having a plate and a dam formed on the peripheral of plate, a conductive layer mounted on a surface of the dam, and at least a cavity defined by the plate and the dam of the substrate. The electronic element is disposed in the cavity of the body. The filler is received in the cavity of the substrate for encapsulating, sealing and protecting the electronic element.Type: GrantFiled: November 30, 2007Date of Patent: December 27, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Cheng Wu, Kun-Hsiao Liu
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Patent number: 8085551Abstract: The present invention is to provide an electronic component where positional accuracy for arranging members constituting a circuit element such as a resistor element and the like is mitigated and corrosion of a terminal electrode caused by sulfur in the atmosphere is reduced.Type: GrantFiled: March 18, 2008Date of Patent: December 27, 2011Assignee: KOA CorporationInventors: Seiji Karasawa, Koji Fujimoto
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Publication number: 20110310579Abstract: An inductor is formed on a wafer by attaching a first core structure to the wafer with a pick and place operation, forming a coil with one or more thick metal layers over the first core structure, and then attaching a second core structure to the first core structure with the pick and place operation after the coil has been formed. In addition, the pick and place operation can also be used to attach one or more integrated circuits to the wafer to form an integrated inductive device.Type: ApplicationFiled: June 16, 2010Publication date: December 22, 2011Inventors: Peter Smeys, Andrei Papou
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Patent number: 8081485Abstract: A component assembly includes an electric component with a body and a carrier substrate on which the component is fixed by means of a conductive adhesive layer. External electrical contacts that have a planar surface are arranged on the lower side of the body. The conductive adhesive acts upon the body in at least one contact region that is devoid of the external electrical contacts.Type: GrantFiled: May 12, 2009Date of Patent: December 20, 2011Assignee: EPCOS AGInventor: Volker Wischnat
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Publication number: 20110304997Abstract: A printed wiring board includes an insulating resinous substrate having an aperture unit, a first terminal unit and a second terminal unit consisting of a conductor and formed on top of the resinous substrate, and a fuse unit that electrically couples the first terminal unit and the second terminal unit to each other. At least a part of the fuse unit is disposed over the aperture unit, and in addition, is covered by a porous inorganic covering material having insulating properties.Type: ApplicationFiled: June 9, 2011Publication date: December 15, 2011Applicant: IBIDEN CO., LTD.Inventors: Yasuji Hiramatsu, Yuki Terada, Tetsuya Muraki
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Patent number: 8077477Abstract: An electronic component, including: a first terminal group including a plurality of functional terminals provided along a first side of the electronic component; a second terminal group including a plurality of functional terminals provided along a second side of the electronic component opposing the first side; and an element that is connected to at least one of the functional terminals of the first terminal group and to at least one of the functional terminals of the second terminal group. The first terminal group includes a first dummy terminal in at least one space between the functional terminals of the first terminal group; the second terminal group includes a second dummy terminal in at least one space between the functional terminals of the second terminal group; and the first and second dummy terminals are not connected to any element inside the electronic component.Type: GrantFiled: December 12, 2008Date of Patent: December 13, 2011Assignee: Panasonic CorporationInventors: Takatoshi Ueyama, Toshiyuki Kajimura
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Patent number: 8072772Abstract: An apparatus includes a two-dimensional array of single-chip modules (SCMs) and at least one component. A respective SCM in the array includes at least a semiconductor die that is configured to communicate data signals by capacitive coupling using one or more proximity connectors in a first set of proximity connectors. The first set of proximity connectors are coupled to the semiconductor die. A second set of proximity connectors is coupled to at least the one component. At least the one component is coupled to semiconductor dies in two or more SCMs using one or more proximity connectors in the second set of proximity connectors thereby enabling communication of the data signals by capacitive coupling.Type: GrantFiled: February 22, 2006Date of Patent: December 6, 2011Assignee: Oracle America, Inc.Inventor: Arthur R. Zingher
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Patent number: 8072773Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.Type: GrantFiled: April 4, 2008Date of Patent: December 6, 2011Inventor: John Mruz
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Publication number: 20110292626Abstract: In a lower-face electrode type solid electrolytic multilayer capacitor and a mounting member having the same according to the present invention, fillet forming portions are formed by forming an electrode substrate cutting portion at a predetermined portion of an edge face in longer direction or in shorter direction of an electrode substrate, and a covering resin cutting portion on an edge face of a covering resin in a staircase pattern so that the electrode substrate cutting portion is surrounded by the covering resin cutting portion. According to the present invention, it is possible to provide the lower-face electrode type solid electrolytic multilayer capacitor and the mounting member having the same, in which the productivity is excellent, the volume efficiency can be improved to achieve the high capacitance, and the stable fillet can be formed on mounting.Type: ApplicationFiled: November 19, 2010Publication date: December 1, 2011Applicant: NEC TOKIN CORPORATIONInventors: Akihiro KAWAI, Kenji ARAKI
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Publication number: 20110292627Abstract: Improved inductive electronic apparatus and methods for manufacturing the same. In one exemplary embodiment, the apparatus comprises an inductive device module comprising N inductors and N+1 core elements. The core elements comprise ferrite core pieces that are optionally identical to one another. These core elements are stacked (e.g., in a longitudinal coaxial arrangement) such that the back of one core element associated with a first inductor provides a magnetic flux path for a second inductor. Form-less (bonded) windings are also optionally used to simplify the manufacture of the device, reduce its cost, and allow it to be made more compact (or alternatively additional functionality to be disposed therein). One variant utilizes a termination header for mating to a PCB or other assembly, while another totally avoids the use of the header by directly mating to the PCB.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Inventor: Timothy Craig Wedley