Stacked Patents (Class 361/790)
  • Patent number: 11102917
    Abstract: The disclosed embodiments are directed to a casing for housing electronic components, comprising a casing wall structure surrounding a casing interior region for accommodating the electronic components, the casing wall structure defining a fluid flow passageway for thermal regulation fluid, the fluid flow passageway extending within the casing wall structure separated from said casing interior region from an inlet to and an outlet at the casing wall structure, characterized in that the casing wall structure completely encloses the casing interior region to make it a closed interior volume, and that the casing wall structure is double-walled by including an inner shell and an outer shell which form a space in between in communication with the inlet and the outlet such that between the inner and outer shells the fluid flow passageway is defined as a continuous and coherent flow space which completely encloses the interior volume of the casing wall structure.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 24, 2021
    Assignee: PREH GMBH
    Inventor: Laura Kvarnstrand
  • Patent number: 11102884
    Abstract: An optical module includes: a first substrate with a first surface, the first substrate having some first pads on the first surface; a second substrate with a second surface, the second substrate having some second pads on the second surface, each of the first pads and a corresponding one of the second pads being opposed to each other and constituting an opposed pair of pads; a first insulation wall between an adjacent pair of the first pads, and in contact with the first surface of the first substrate; and a second insulation wall between an adjacent pair of the second pads, and in contact with the second surface of the second substrate. The first insulation wall and the second insulation wall overlap with none of the opposed pair of pads and are adjacent to each other in a direction along the first surface and the second surface.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 24, 2021
    Assignee: CIG PHOTONICS JAPAN LIMITED
    Inventors: Shigeru Mieda, Hirofumi Nakagawa, Daisuke Murakami
  • Patent number: 10985097
    Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 20, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Fei Guo, Feng Zhu, Julius Din, Anwar Kashem, Sally Yeung
  • Patent number: 10953825
    Abstract: The invention relates to an electrical busbar (400) intended for electrically connecting an electrical component, said electrical busbar (400) including: at least one electrically conductive part (410); a coating (420) made of electrically insulating material covering said part (410) at least in a main plane of the busbar (400), the electrically conductive part (410) including: a first end forming an electrical connection terminal; a planar portion extending so as to follow said main plane; and an electrically conductive cylinder (414) which extends away from a first surface of the planar portion in a transverse direction relative to the main plane, the inner wall of the cylinder extending away from an opening located in the planar portion so as to receive a rod in order to rest the distal end (414a) of the cylinder (414) on a terminal of the electrical component.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: March 23, 2021
    Assignee: VALEO SIEMENS EAUTOMOTIVE FRANCE SAS
    Inventors: Guillaume Sanvito, Pierre Smal
  • Patent number: 10263351
    Abstract: In accordance with one embodiment, an electrical connector system can include an electrical signal connector and an electrical power connector. The electrical signal connector and the electrical power connector can be mounted on opposed surfaces of a printed circuit board. The electrical power connector can be constructed as a hermaphroditic power connector that includes at least one header power contact supported by a connector housing, and at least one receptacle power contact supported by the connector housing.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: April 16, 2019
    Assignee: FCI USA LLC
    Inventors: Rupert Fry, Jr., Charles Copper
  • Patent number: 10256568
    Abstract: Electrical connectors, electrical modules, and systems are provided. In one aspect, an electrical connector includes a housing defining a side surface, an electrical conductor supported by the housing and including an engagement portion proximate the side surface of the housing. The engagement portion is adapted to engage another electrical conductor of another electrical connector. The connector also includes a magnet supported by the housing proximate the side surface of the housing, a projection extending from the side surface of the housing, and a receptacle defined in the side surface of the housing. In other aspects, an electrical module includes at least one of these electrical connectors. In further aspects, a system includes a plurality of these modules and the modules are selectively couplable together.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 9, 2019
    Assignee: littleBits Electronics Inc.
    Inventor: Aya Bdeir
  • Patent number: 10188011
    Abstract: A backplane system for a high-speed network element includes a main backplane including a plurality of traces for data and control connectivity, high-speed data connectors, and a power connector, wherein the high-speed data connectors and the power connector are configured to engage one or more modules; and a power backplane for power connectivity separate from the main backplane connected to the power connector, wherein the power backplane is coupled to a power source to provide supply and return current to the one or more modules through the power connector.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 22, 2019
    Assignee: Ciena Corporation
    Inventors: Adrianus P. Van Gaal, Robert L. Bisson, Andrew Douglas Thuswaldner, Timothy David Mombourquette
  • Patent number: 9986639
    Abstract: An integrated electronic component assembly can include an electrically-conductive structure comprising two or more electrically-conductive terminals accessible on an exterior of the integrated electronic component assembly, a first component attachment region for a first component within the integrated electronic component assembly, and a second component attachment region for a second component within the integrated electronic component assembly. The integrated electronic component assembly can include an electrically-conductive magnetically-permeable shield coupled to or defined by the electrically-conductive structure, the electrically-conductive magnetically-permeable shield located between the first and second component attachment regions, including a portion extending in a direction out of a plane defined by the first and second component attachment regions, to suppress magnetic coupling between the first and second components.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 29, 2018
    Assignee: Analog Devices Global
    Inventors: Aldrick S. Limjoco, Michael Cusack, Donal G. O'Sullivan, Patrick John Meehan, Thomas Conway
  • Patent number: 9676611
    Abstract: Sensor device packages and related fabrication methods are provided. An exemplary sensor device package includes a first structure having a sensing arrangement thereon, a second structure having circuitry thereon, and a conductive structure within the first structure and coupled to the circuitry to provide an electrical connection to the circuitry through the first structure. Thus, circuitry on the second structure may be electrically connected to an interface of the sensor device package through the first structure.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 13, 2017
    Assignee: NXP USA, Inc.
    Inventors: Stephen R. Hooper, Philip H. Bowles
  • Patent number: 9634415
    Abstract: In order to facilitate the vertical placement of modules (104, 106) within a PLC (100) and thus decrease the size of the PLC (100) without reducing the capability of the PLC (100), modules (104, 106) of the PLC (100) each includes a printed circuit board (PCB) (200, 202, 204), a spring loaded pin connector (214) supported by and in electrical communication with a first surface (206, 208) of the PCB (200, 202, 204), and a receptacle (216) supported by and in electrical communication with a second surface (206, 208) of the PCB (200, 202, 204). The spring loaded pin connector (214) and the receptacle (216) are in electrical communication with each other via the PCB (200, 202, 204).
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 25, 2017
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Wenmin Ye, Ned Cox
  • Patent number: 9559480
    Abstract: A method, system and apparatus for making an interconnection between power cables and signal cables. A single electrical interface in mid- or backplane applications is introduced to accommodate a wide range of board thickness variations while maintaining a desired interface relationship, using a connector plug bushing, a male connector having a sliding fit with the bushing, a first coaxial connector plug, a female connector plug with a housing width sized to provide a sliding fit within the connector plug bushing inner opening, and a second coaxial connector plug in the free end of the female connector plug for connection to the power and signal cables. A constant impedance connector is used with the interconnection of the RF signal and power cables.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 31, 2017
    Assignee: The Phoenix Company of Chicago, Inc.
    Inventors: Robert M. Bradley, James R. Balistreri, John E. Maturo
  • Patent number: 9551984
    Abstract: A system, method and control unit for determining an order of a plurality of stacked electronic devices randomly ordered in a stack, for taking inventory of the devices, and for programming the devices according to the determined order. Each of the electronic devices is assigned a unique serial number, and the electronic devices are configured to report their serial numbers to the control unit in sequence, either upward or downward, in the stack. The control unit is configured to determine an order of the plurality of electronic devices in the stack based on the sequence in which the identifiers are received, to compare the sequence numbers to a known list to determine if any devices are missing, and to program the devices according to the determined order.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 24, 2017
    Assignee: TEZ Presto, LLC
    Inventor: Kenneth J. Lovegreen
  • Patent number: 9516755
    Abstract: Embodiments of the invention describe a motherboard PCB having a memory bus to receive signal data from a channel of memory chips/devices of a memory module. Electrical contacts, communicatively coupled to the memory bus, securely couple the PCB to the memory chips/devices of the memory module. Embodiments of the invention further include a receiving housing that includes said electrical contacts and has a height less or equal to the height of the memory module. Embodiments of the invention further describe a memory module having a memory card housing, first and second pluralities of memory chips/devices included in the housing, and first and second pluralities of memory module electrical EO terminals for coupling the first and second pluralities of memory chips/devices to PCB, respectively. In embodiments of the invention, the above described first and second pluralities electrical EO connectors are disposed on different sides of the housing.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Hue V. Lam, Loc V. Doan
  • Patent number: 9429724
    Abstract: A function-specific network interface module is provided which includes a housing and a connection interface at opposing ends of the housing configured to connect to another function-specific network interface module in a cascaded manner. The function-specific network interface module further includes one or more circuit components operable to provide a dedicated network function so that a plurality of different network functions is provided when the function-specific network interface module is connected to the other function-specific network interface module via the connection interface.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: August 30, 2016
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Martin Julien, Robert Brunner
  • Patent number: 9385468
    Abstract: The invention relates to a joint connector assembly including first and second connectors connected to each other by a circuit board and connected to third connectors by connection terminals. The circuit board is mounted at the center of the third connectors below the first and second connectors located in an upper region of a main body housing and is integrally formed with the main body housing in a lower region thereof. The upper region of the main body housing defines first and second connector receptacles for the first and second connectors. A cover member is attached to a lower surface of the circuit board to cover the circuit board. The joint connector assembly has a reduced volume because the connectors are connected to one another without lines and all the connectors are inserted in the main body housing, allowing the joint connector assembly to be installed in a small space.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: July 5, 2016
    Assignee: Tyco Electronics Amp Korea Ltd.
    Inventor: Chul-Sub Lee
  • Patent number: 9330345
    Abstract: A memory card includes a card body, an interface terminal and an attachment mechanism for detachably mounting the card to an adaptor of an electronic device. The interface terminal is disposed at a central portion of a major surface of the card body. The attachment mechanism is located at an outer peripheral portion of the card body that surrounds the central portion. The adaptor has a recess whose shape complements that of the major surface of the card body, and socket exposed at a central portion of the bottom of the recess. Thus, the memory card may be inserted face down into the adaptor.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jin Park, Il-Guy Jung
  • Patent number: 9257818
    Abstract: Computational enclosures may be designed to distribute power from power supplies to load units (e.g., processors, storage devices, or network routers). The architecture may affect the efficiency, cost, modularity, accessibility, and space utilization of the components within the enclosure. Presented herein are power distribution architectures involving a distribution board oriented along a first (e.g., vertical) axis within the enclosure, comprising a power interconnect configured to distribute power among a set of load boards oriented along a second (e.g., lateral) axis and respectively connecting with a set of load units oriented along a third (e.g., sagittal) axis, and a set of power supplies also oriented along the third axis. This orientation may compactly and proximately position the loads near the power supplies in the distribution system, and result in a comparatively low local current that enables the use of printed circuit boards for the distribution board and load boards.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: February 9, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eric C. Peterson, Shaun L. Harris
  • Patent number: 9214455
    Abstract: A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 15, 2015
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni
  • Patent number: 9192008
    Abstract: A light-emitting diode (LED) light module is provided, comprising: a single-piece printed circuit board (PCB) comprising the following integrated on the PCB: a plurality of LEDs in each of a plurality of LED groups; a power supply converter; a controller module comprising a processor, memory, operational program stored in the memory and executable by the processor; input/output (I/O) circuitry, and an LED driver that drives the LEDs; the module further comprising: a single metallic housing that contains the PCB; a heat sink that conducts heat from components on the PCB to the housing; and a lens for diffusing or directing lights from the LEDs.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 17, 2015
    Assignee: B/E AEROSPACE, INC.
    Inventors: David P. Eckel, Eric Johannessen, Erick Palomo, Jonathan Brosnan
  • Patent number: 9184147
    Abstract: A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: November 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin Ho Bae, Ki Young Kim, Jong Hyun Nam
  • Patent number: 9179570
    Abstract: The subject invention is directed to a new and useful line replaceable unit (LRU) including an LRU case defining an interior compartment for housing critical function circuit card assemblies and including a back plane wall and opposed interface wall. At least one critical function circuit card assembly (CCA) is housed within the LRU case. The critical function CCA includes an input output connector mounted in proximity to the interface wall, as well as a backplane connector. The LRU includes a backplane CCA operatively connected to each backplane connector of the at least one critical function CCA. The backplane CCA is configured and adapted to provide operative communication among multiple critical function CCA's. The critical function CCA's can be mounted to the LRU case proximate the interface wall and the backplane wall to be mechanically and electrically isolated from one another except for connections provided by the backplane CCA.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: November 3, 2015
    Assignee: Simmonds Precision Products, Inc.
    Inventor: Robbie William Hall
  • Patent number: 9166327
    Abstract: An inline connector is coupled to a first substrate and operable to receive at least one prong. A second receptacle is coupled to a second substrate and operable to receive the prong. A plug having an elongated prong that, when inserted through the first receptacle and into the second receptacle operates to provide electrical connections between the substrates. The substrates may be circuit boards and the receptacle may be mounted along the edges of the circuit board to allow for easier installation. Some embodiments may provide for identical receptacle providing for lower costs and easier installation.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 20, 2015
    Assignee: Vode Lighting LLC
    Inventor: Scott S. Yu
  • Patent number: 9152917
    Abstract: Methods and systems for the evolution of electronic neural assemblies toward directed goals. A compact computing architecture includes electronics that allows users of such an architecture to create autonomous agents, in real or virtual world and add intelligence to machines. An intelligent machine is composed of four basic modules: one or more sensors, one or more motors, a (Reward Input Output System) RIOS and a cortex. A number of genetically evolved detectors can project both to cortex and RIOS. At first the neurons within the cortex evolve to predict the structure of the sensory data followed by the structure of proprioceptive activations of its own motor system. Finally, once the cortex has learned its sensory and motor programs, it evolves to predict the reward signals, which comes in multiple channels but is dominated by the detection of the acquisition of free-energy.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: October 6, 2015
    Assignee: KnowmTech, LLC
    Inventor: Alex Nugent
  • Patent number: 9089058
    Abstract: A stackable electronic device with latching bumper includes a housing, an electrical connector, a latching mechanism having a linking module, a latching module and a button. The housing has a bottom board, a side board formed with a button hole, and a bumper disposed on the bottom board formed with a latching hole. The linking module is disposed on an inner side of the side board, and has a first end extended into the button hole and a second end extended into the bumper. The latching module is movably disposed in the bumper between a locking position and an unlocking position. The second end is connected to the latching module. The button can be pressed for driving the first end to move the second end corresponding to the locking position and the unlocking position. The present disclosure also provides a stackable electronic device system.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 21, 2015
    Assignee: WISTRON CORP.
    Inventors: Jyun-Shuo Liang, Hung-Li Chen
  • Publication number: 20150146400
    Abstract: A connector system includes a first substrate, a second substrate, and a standoff arranged between the first substrate and the second substrate. The standoff includes a first part with an external threading and a second part with an internal threading configured to engage with the external threading of the first part. The first part is configured to engage with the first substrate, the second part is configured to engage with the second substrate, and the external threading of the first part and the internal threading of the second part are configured such that the first part and the second part are configured to be unscrewed from each other to cause the distance between the first and second substrates to increase.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 28, 2015
    Inventors: James Robert HUFFMAN, Cody Logan GRAF, David Lynn DECKER, William Chieng OUYANG
  • Patent number: 9042115
    Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
  • Patent number: 9042116
    Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 26, 2015
    Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Kuan Wu, Hou-Yuan Chou
  • Patent number: 9029713
    Abstract: A printed wiring board including a rigid multilayer board, a first substrate having multiple conductors, and a second substrate having multiple conductors electrically connected to the conductors of the first substrate. The conductors of the second substrate have an existing density which is set higher than an existing density of the conductors of the first substrate, and the first substrate and/or the second substrate is embedded in the rigid multilayer board.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventor: Michimasa Takahashi
  • Patent number: 9030838
    Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Ho You, Heeseok Lee, Chiyoung Lee, Yun-Hee Lee
  • Patent number: 9013892
    Abstract: A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: April 21, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chang-Chih Liu, Hsun Yu, Peng-Shu Chen, Shih-Hsien Wu
  • Patent number: 9007776
    Abstract: An electronic module includes a first circuit board having a first surface, a second circuit board having a second surface, first electronic components on the first surface, second electronic components on the second surface, a first conductive fence, and a second conductive fence. The first conductive fence encloses the first electronic components and has a first opening exposing the first electronic components. The second conductive fence encloses the second electronic components and has a second opening exposing the second electronic components. The first opening of the first conductive fence joints the second opening of the second conductive fence, such that the first electronic components and the second electronic components are surrounded by the first circuit board, the second circuit board, the first conductive fence, and the second conductive fence. At least one of the first electronic components is higher than the first conductive fence.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 14, 2015
    Assignee: HTC Corporation
    Inventors: I-Cheng Chuang, Chien-Hung Chen, Chih-Hung Li, Cheng-Te Chen
  • Patent number: 8988893
    Abstract: A link device for three-dimensional integrated structure may include a module having a first end face designed to be in front of a first element of the structure, and a second end face designed to be placed in front of a second element of the structure. The two end faces may be substantially parallel, and the module including a substrate having a face substantially perpendicular to the two end faces and carrying an electrically conducting pattern formed in a metallization level on top of the face and enclosed in an insulating region. The electrically conducting pattern may include a first end part emerging onto the first end face and a second end part emerging onto the second end face and connected to the first end part.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: March 24, 2015
    Assignee: STMicroelectronics SA
    Inventors: Pierre Bar, Sylvain Joblot, Jean-Francois Carpentier
  • Patent number: 8983399
    Abstract: Provided is an in-millimeter-wave dielectric transmission device. The in-millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of in-millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Hirofumi Kawamura, Yasuhiro Okada
  • Patent number: 8975525
    Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim, Rohan Mandrekar
  • Patent number: 8971056
    Abstract: A hermetically sealed HF front end (e.g. a transmission/reception module) in a multilayer structure that includes electronic components is provided. The multilayer structure contains a plurality of substrates stacked one above the other and carrying the components. Grooves are formed in the substrates and sealing elements are provided between the substrates, which sealing elements engage in the grooves, and the substrates are soldered together.
    Type: Grant
    Filed: September 18, 2010
    Date of Patent: March 3, 2015
    Assignee: EADS Deutschland GmbH
    Inventors: Heinz-Peter Feldle, Bernhardt Schoenlinner, Ulrich Prechtel, Joerg Sander
  • Patent number: 8964219
    Abstract: An image forming apparatus includes an installation section, a control board, a first connection terminal provided on an outer surface of the control board, a first electrical connection member provided on the installation section and electrically connected to a point of reference potential, a substrate installable in the installation section in a thickness direction of the control board, an external connection terminal provided on the substrate and externally exposed, a second connection terminal provided on a first surface of the substrate and connected to the first connection terminal when the substrate is installed into the installation section, and a second electrical connection member provided on a second surface of the substrate. The second electrical connection member makes contact with the first electrical connection member and is electrically connected to the point of reference potential via the first electrical connection member when the substrate is installed into the installation section.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: February 24, 2015
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Tetsuo Ishizuka
  • Patent number: 8947888
    Abstract: A substantially cable-free board connection assembly may include a plurality of printed circuit boards (PCBs) forming an interconnect plane for a plurality of electronic devices respectively attached to a plurality of plane boards included in the interconnect plane. An insertion direction for substantially all connectors is substantially perpendicular to a face of the interconnect plane. At least a portion of the board connection assembly is mounted to a support structure via a flexible connection.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 3, 2015
    Assignee: Microsoft Corporation
    Inventors: Eric C. Peterson, David T. Harper
  • Patent number: 8942009
    Abstract: A power switch assembly includes a flip-chip type integrated circuit chip and a lead-frame with a plurality of spaced apart parallel lead sections. The flip-chip type integrated circuit chip includes a distributed transistor, and first and second pluralities of flip-chip interconnects connected to source and drain regions, respectively. The first and second lead sections at least partially overlap along the first axis. Each of the plurality of lead sections includes a contact portion and an extended portion extending laterally from the contact portion. The extended portions of the first and second lead section extend from the contact portion in opposite directions. The first side of the first and second lead section contacts at least two of the first and plurality of flip-chip interconnects, respectively. The second side of the first and second lead are configured to contact a first and second contact area on a printed circuit board, respectively.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Efren M. Lacap, Ilija Jergovic
  • Patent number: 8921703
    Abstract: A circuit board, structural units and a manufacturing method are provided, wherein one or more high temperature lamination processes are conducted for laminating the structural units and form a multi-layered circuit board.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: December 30, 2014
    Assignee: HTC Corporation
    Inventors: Chin-Wei Ho, Hui-Ling Tsai
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Patent number: 8902598
    Abstract: A programmable logic controller (PLC) assembly includes a bottom housing with a base, a first plurality of elongate alignment features extending from the bottom housing transverse to the base, and a first connection feature. The PLC assembly includes a central processing unit with a circuit board and at least two receptacles therethrough configured to engage and slide along at least two of the first plurality of alignment features. The at least two of the first plurality of alignment features are positioned asymmetrically with respect to the base. The PLC assembly includes an upper housing with a second connection feature configured to slidably couple with the first connection feature and a second plurality of elongate alignment features configured to slidably engage at least two of the first plurality of alignment features, which are positioned asymmetrically with respect to the base.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 2, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Karen Chin, Chee Lim Wong
  • Patent number: 8897000
    Abstract: A server includes a casing, a motherboard, a power supply unit and a pair of expansion modules. The motherboard is disposed in the casing, and the motherboard includes two slots disposed in the casing. The power supply unit is disposed in the casing and under the motherboard. The expansion modules are disposed in the casing, and each of the expansion modules includes a connecting card and a plurality of expansion cards. When the connecting card is electrically coupled to one of the slots of the motherboard, the expansion modules are disposed at two opposite sides of the motherboard correspondingly.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: November 25, 2014
    Assignee: ASUSTeK Computer Inc.
    Inventor: Chih-Wei Chou
  • Patent number: 8891247
    Abstract: A conductive circuit containing a polymer composite, which contains at least one polymer and a modified graphite oxide material, containing thermally exfoliated graphite oxide having a surface area of from about 300 m2/g to 2600 m2/g, and a method of making the same.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 18, 2014
    Assignee: The Trustees of Princeton University
    Inventors: Robert K. Prud'Homme, Ilhan A. Aksay
  • Patent number: 8891246
    Abstract: An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: November 18, 2014
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Vijay K. Nair
  • Patent number: 8873244
    Abstract: A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: October 28, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Hsiao-Jen Hung, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8873245
    Abstract: An embedded chip-on-chip package includes a printed circuit board having a recessed semiconductor chip mounting unit constituted by a recess in the printed circuit board and a circuit pattern at the bottom of the recess, a first semiconductor chip embedded in the recessed semiconductor chip mounting unit and electrically connected to the circuit pattern at the bottom of the recess, and a second semiconductor chip mounted to the recessed semiconductor chip mounting unit and electrically connected to the first semiconductor chip and the printed circuit board independently of each other.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Kim, Hee-seok Lee
  • Patent number: 8873247
    Abstract: A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 28, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Koji Hosokawa
  • Patent number: 8872324
    Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. Farrar, Hussein I Hanafi
  • Patent number: 8869387
    Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
  • Patent number: 8861217
    Abstract: This relates to systems and methods for providing one or more vias through a module of an electrical system. For example, in some embodiments, the module can include one or more passive elements and/or active of the electrical system around which a packaging has been plastic molded. The module can be stacked under another component of the electrical system. Vias can then be provided that extend through the module. The vias can include, for example, electrically conductive pathways. In this manner, the vias can provide electrical pathways for coupling the component stacked on top of the module to other entities of an electronic device including the electrical system. For example, the component can be coupled to other entities such as other components, other modules, printed circuit boards, other electrical systems, or to any other suitable entity.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 14, 2014
    Assignee: Apple Inc.
    Inventors: Gloria Lin, William Bryson Gardner, Jr., Joseph Fisher, Jr., Dennis Pyper, Amir Salehi