Abstract: A wiring board and method of forming the wiring board. The wiring board includes a first substrate, and a second substrate having a smaller mounting area than a mounting area of the first substrate. A base substrate is laminated between the first substrate and the second substrate such that the first substrate extends beyond an edge of the second substrate, and at least one via formed in at least one of the first substrate or the second substrate. A thickness of a portion of the base substrate that is sandwiched between the first substrate and the second substrate is greater than a thickness of a portion of the base substrate that is not sandwiched between the first substrate and the second substrate.

Abstract: A package for providing electromagnetic shielding for microwave circuits. The package includes a top board having an upper surface, a lower surface opposite to the upper surface and a side surface joining the upper surface and the lower surface, and a bottom board having an upper surface attached to the lower surface of the top board, a lower surface opposite to the upper surface and an outer side surface joining the upper surface and the lower surface. The top board further includes at least one ground layer formed therein and a first metal coating formed on at least part of the side surface of the top board. The bottom board includes an inner side surface extending from the upper surface of the bottom board toward the lower surface of the bottom board and an inner lower surface joining the inner side surface, thereby providing an inner space for accommodating the microwave circuit.

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

Abstract: Interconnect substrate (1) that connects at least the first circuit board and the second circuit board. Interconnect substrate (1) includes housing (1) and connecting terminal electrodes for connecting the top and bottom faces of housing (10). Housing (10) has protrusion (11) on its outer periphery and opening (13) in its inner periphery.

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

Abstract: Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.

Abstract: Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.

Abstract: A semiconductor system in a package separates those circuits in a field programmable gate array (FPGA) into two substrates. In particular, the logic elements are formed in a first semiconductor substrate and certain non-logic elements are formed in a second semiconductor substrate that is in mechanical and electrical connection with the first substrate. The two substrates are enclosed in a suitable protective package and electrical connections are provided between one or both substrates and the exterior. The non-logic elements formed in the second substrate are located in circuits that would have a signal propagation delay in a conventional FPGA that is more than approximately twice the interconnect delay between the two substrates.

Abstract: A multiprocessor system is provided, comprising a baseboard, for arranging peripheral equipments; and a plurality of processor modules, each equipped with a processor and a board-to-board connector; wherein the plurality of processor modules are stacked up, with board-to-board connectors being electrically connected between the processor modules and between the processor modules and the baseboard; the processors communicate with the peripheral equipments in accordance with a specific bus specification; and the operations of the plurality of processor modules are coordinated by routes provided between the processor modules and between the processor modules and the baseboard.

Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability.

Abstract: A stacked microelectronic assembly is disclosed, as are different embodiments related to the same. The stacked microelectronic assembly includes a plurality of stackable microelectronic units each having a semiconductor element mounted on a substrate, and also includes alignment elements which align and stack the units one atop another. The aligned assembly may be heated to melt or to reflow the conductive bonding material between the units, thereby electrically coupling and bonding corresponding conductive terminals on each unit.

Abstract: An electronic device is provided that includes a main printed circuit board (PCB) having a top surface, a bottom surface, and a hole extending between the top surface and the bottom surface. The electronic device further includes a module PCB having at least one electrical component mounted on a top surface of the module PCB, wherein the module PCB is inverted and assembled adjacent the main PCB such that the top surface of the module PCB faces the top surface of the main PCB, and the at least one electrical component extends into the hole. In addition, the electronic device includes a cover on the bottom surface of the main PCB that substantially covers the hole.

Abstract: Electrical components, such as packaged integrated circuit devices that are mountable on a substrate surface, are provided with at least one exposed electrical contact on a side surface of the component that will be substantially perpendicular to the substrate surface when the component is mounted. Two such components can be mounted side-by-side on the substrate surface with the above-mentioned contacts close to one another between the above-mentioned side surfaces. An electrical connection between the contacts can be made (or perfected) by depositing an electrically conductive connector material in contact with both of the contacts between the above-mentioned side surfaces.

Abstract: A crash-hardened memory device in which only a single electronic component, such as a memory chip, mounted on a small printed circuit board (PCB), is protected against an impact. The portion of the PCB containing the electronic component is wrapped in fire-retardant material. The wrapped PCB assembly is placed in a rigid, hardened enclosure which provides an environmental seal for the portion of the PCB containing the electronic component. A portion of the PCB extends outside of the enclosure to allow electrical connections to be made to the electronic component contained inside. A score line is created on the PCB to create an acceptable shear point between the internal and external portions of the PCB in the event of a crash. Threaded fasteners extend through and beyond both enclosure halves to provide a means for mounting the crash-hardened memory device on an external surface.

Abstract: An object of the present invention is to provide a wiring module that enables dense mounting and a reduction in wiring distance. The wiring module in accordance with the present invention includes a base material, a plurality of electronic circuit parts, insulating portions, and conductive portions connected to the electronic circuit parts, the plurality of electronic circuit parts, the insulating portions, and the conductive portions being integrally held on the base material. Wires are composed of a stack of the conductive portions and extend in a direction crossing a surface of the base material and in a direction crossing a direction perpendicular to the base material surface to electrically connect the plurality of electronic circuit parts together.

Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Abstract: A circuit board with a simple structure is manufactured. A circuit board 19 has thereon a foil circuit 21 provided on a synthetic resin plate 20 formed by injection molding, made of a copper foil, and having a pattern different for circuit board 19. Anchor pins 20a projecting upward are provided on the resin plate 20 and passed through pinholes made in the foil circuit 21. The foil circuit 21 are positioned and secured to the resin plate 20. In a required portion of the resin plate 20, a terminal insertion hole 20c is provided, and receiving terminal 22 is secured to the required portion of the terminal insertion hole 20c and connected to the foil circuit 21.

Abstract: The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.

Abstract: An intercoupling component is provided that electrically connects the device leads of an integrated circuit package to a substrate. The package includes external device leads, each device lead having a downwardly extending section proximate a side of the package body, and the intercoupling component includes an insulating support member. The support member includes a first surface including first electrical attachment sites, each configured for making an electrical connection with a corresponding one of the device leads of the package. The support member also includes an opposite second surface including second electrical attachment sites in electrical contact with the first electrical attachment sites, each of the second electrical attachment sites including a plurality of solder balls associated with each device lead. The plurality of solder balls are used to form an electrical connection between each surface mount pad on the substrate and the corresponding conductive pad of the intercoupling component.

Abstract: A plurality of film substrates (2) having a bare chip (1) mounted on one side or both sides are joined into a laminated state by joint portions (3) and are attached to a motherboard (4) through junction by a joint portion (8) at a location off the mounting areas of the bare chips (1), thereby achieving a lower profile, higher lamination, and higher capacity.

Abstract: Provided is an electronic circuit device in which the bonding state of electrodes can be detected easily with high precision. The electronic circuit device has a stack structure in which a plurality of electronic circuit boards (1a, 1b, 100a, 100b, 100c) are stacked in three or more layers through ball electrodes (10a, 10b, 20a, 20b) bonded to electrode pads (30a, 30b, 40b, 50a, 60a), wherein the electrode pads are disposed such that transmission shaded images of a pair of the electrode pads provided between adjacent layers partially overlap each other and have a non-overlapping region in which the transmission shaded images of the pair of electrode pads are free from overlapping and such that the transmission shaded image of the non-overlapping region is at least partially free from overlapping with transmission shaded images of all the other electrode pads.

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract: A method of manufacturing an electronic component includes the steps of a) forming a plurality of wiring boards that include first through holes penetrating through a semiconductor substrate and conductive material buried in the first through holes; b) providing conductive projections on the conductive material of any of the plurality of wiring boards; and c) bonding the plurality of wiring boards to each other and electrically connecting the conductive material of the respective wiring boards by the projections.

Abstract: A function expansion datacard including a main board, a connector, a housing and a holder is provided. Several chips and the connector are disposed on a surface of the main board. The connector is situated near the edge of the main board. The housing disposed on the main board covers the chips and exposes a connection surface of the connector. The holder movably disposed at the housing is moved in and out the housing. The holder is situated over the connector and moves in a direction perpendicular to the connection surface.

Abstract: First and second housings of a metal sheet are superposed over each other and fixed to each other by bolts to form an element receiving space. An antenna is fixed to the second housing by a bolt so as to be adjacent to the first housing. A hook section is fixed to the first housing. The hook section is inserted in a hole of the antenna, a step-shaped forward lower step section of the hook section is engaged with the peripheral edge of the hole in the antenna, and thus the first housing and the antenna are fixed to each other. The antenna is embedded in resin and covered by the resin.

Abstract: The invention provides a warpage-proof circuit board structure, including: an inner layer circuit board; at least one dielectric layer formed on at least one surface of the inner layer circuit board; at least one first groove formed in the at least one dielectric layer corresponding in position thereto; a solder mask formed on the surface of the dielectric layer, a second groove formed in the solder mask and corresponding in position to the first groove formed in the dielectric layer; and a metal frame formed in the first and second grooves and protruding from the surface of the solder mask, thereby strengthening the circuit board to prevent it from warping in thermal processing and further using the metal frame as a heat-dissipating means for the package structure.

Abstract: An integrated circuit package system including: providing a substrate; mounting an integrated circuit above the substrate; mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step molded in the inner stacking module encapsulation, above the integrated circuit; and encapsulating the inner stacking module, and the integrated circuit with an encapsulation.

Abstract: A stacked mounting structure includes a first substrate, a second substrate, and an intermediate substrate which has a space accommodating therein components to be mounted. A first contact (connecting) terminal and a second contact (connecting) terminal are formed on the first substrate and the second substrate, and have a wire which is formed on a side surface of the intermediate substrate. By formation of the intermediate substrate to be on an inner side than an edge surface of the substrates, a part of the two contact terminals respectively are exposed. One end of the wire is connected to an exposed portion of the first contact terminal, and the other end of the wire is connected to an exposed portion of the second contact terminal.

Abstract: A multilayered module board with mounted high-frequency electronic components such as a CPU and a graphic circuit is mounted on one face of a base board with mounted low-frequency electronic components. The multilayered module board is a squared multilayered board smaller than the base board. The electronic components are wired with an inner layer-wiring pattern. Connector terminals are solder-jointed to four sides of the multilayered module board. The multilayered module board is mounted to the base board via the connector terminal.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.

Abstract: In a controller, in particular for motor vehicle transmissions, having a holder (1) on which an electronic circuit component (2) and at least one flexible printed-circuit film (3) connected to the electronic circuit component (2) by means of electric connection means (7) are arranged, it is proposed to arrange on the holder (1) a frame component (5) which surrounds the electronic circuit component (2), and to connect the electric connection means (7) connected to the electronic circuit component electrically to the at least one flexible printed-circuit film (3), through at least one opening (15) in the frame component (5).

Abstract: A grounding apparatus for connecting electrical equipment to ground comprises a plate comprising a top surface, a bottom surface and first and second end portions. Typically, the plate is connected to opposing support legs, such that an open space is provided under the bottom surface of the plate. The top surface of the plate may comprise one or more raised surfaces and also define a plurality of apertures for use in securing one or more lugs to the plate. The grounding apparatus optionally comprises a port connected thereto and comprising an exterior surface defining an opening for receiving a plug.

Abstract: An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Abstract: Stacking of electronics modules, boards or cards, hereinafter referred to as cards is described. Each card in a stack is connected logically to a host via a single physical bus slot, and can detect its relative position in the stack on initial power on and make use of that information to grab an appropriate resource pool. In one embodiment, a top most card is used as a reference and the rest of the cards in the stack derive a relative address with respect to the top most card. A few lines are dedicated between neighboring cards through which the cards can share their relative address information with succeeding cards and automate resource allocation based on the address information.

Abstract: In a power drive unit having power modules (three-phase inverter circuits) connected to a control circuit board, bus bars extending from the power modules and a current sensor each installed near the bus bars and including a sensing element that detects currents outputted from the bus bars, there are provided a sensor board on which the sensing element is mounted, and lead pins each connecting the sensor board to the control circuit board and having a bowed shape whose one end is connected to the sensor board and other end once extends away from the circuit board and then turns back toward the circuit board. With this, the circuit board and current sensors can be connected through the lead pins without increasing the distance therebetween and stress produced in the lead pins can be alleviated, thereby enabling the unit to be minimized in size and utilized in a harsh service environment.

Abstract: A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

Abstract: A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

Abstract: A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process.

Abstract: An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

Abstract: A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

Abstract: An electronic apparatus includes an outer cover member, an internal structure member, first and second external connection connectors, and first and second printed circuit boards. The first printed circuit board has a first surface on which the first external connector is mounted thereon, a signal pattern of the first external connector is formed on the first surface, and a second surface. The second printed circuit board has a first surface on which the second external connector is mounted thereon, a signal pattern of the second external connector is formed on the first surface, and a second surface. Ground patterns are formed on the second surfaces of the printed circuit boards. The first and second external connectors overlap and are arranged in a space surrounded by the outer cover member and the internal structure member so that the second surfaces of the first and second printed circuit boards face each other.

Abstract: Electronic circuit device (100) is structured so that a substrate module unit that are formed by stacking substrate modules made of a first resin sheet with electronic component (190) embedded thereinto is inserted into housing (150) including connecting terminal (120), control circuit (130), and first wiring pattern (140), where the substrate modules are connected to each other electrically and mechanically. This electronic circuit device (100) dispenses with a mother substrate. Further, with slimming down of a substrate module, a substrate module unit with a large number of substrate modules stacked can be loaded in a limited packaging space, thus mounting greater storage capacity and higher functionality.

Abstract: A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates.

Abstract: A circuit carrier assembly includes a plurality of substrates directly secured together by an electrically conductive securing substance. In one example, the securing substance is a conductive epoxy. In another example, the electrically conductive securing substance is solder. Still another example includes a combination of solder and conductive epoxy. A non-conductive epoxy provides further mechanical connection and thermal conductivity between the substrates while also electrically isolating selected portions of the substrates in one example. The electrically conductive securing substance not only mechanically secures the substrates together and provides thermal conductivity between the substrates, which increases the thermal capacitance of the assembly, but also establishes at least one electrically conductive path between the substrates.

Abstract: The present invention can relate to an electronic device having one or more support tabs that protect a circuit board disposed inside the device from externally applied compressive forces. In particular, when a force is applied to a housing of the device, the support tabs can buttress the housing of the device, either directly or through other intervening components disposed within the device, to reduce the likelihood that the housing or intervening components will contact and damage the circuit board. The present invention also can relate to methods for manufacturing such an electronic device.

Abstract: The present invention can relate to multiple-connector assemblies for use in, for example, electronic devices. Each of the connectors are constrained to another connector by aligning one or more complementary sets of reference features. A locating bracket may be used to couple multiple connectors together. Alternatively, the connectors may be coupled to each other directly. The electronic device also may include a retainer coupled to the connectors (either directly or indirectly through the locating bracket). The retainer and a surface of one of the connectors may form a single plane to which an end cap of the housing may be coupled, thereby accurately locating the end cap with respect to the connectors. The present invention also can relate to methods of manufacturing such an electronic device.

Abstract: A semiconductor package, includes: element substrate having first surface, including: functional element on first surface, and extracting electrode on first surface and configured to output a signal of functional element, extracting electrode being disposed around functional element; rim substrate shaped into a frame, and configured to have first junction with element substrate to surround functional element, rim substrate including: first through hole through rim substrate, and connecting electrode which is: formed by packing first through hole with first conductor material, configured to seal signal extracting aperture of extracting electrode, and configured to electrically connect signal extracting aperture with takeout electrode; and cover substrate configured to have second junction with rim substrate to block aperture of rim substrate, cover substrate including: second through hole through cover substrate, and takeout electrode which is: formed by packing second through hole with second conductor materi

Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Abstract: First sheet-like substrate is arranged at a region surrounded by first terminals of male connector and first circuit substrate, and second sheet-like substrate is arranged at a region surrounded by second terminals of female connector and second circuit substrate, and male connector and female connector are fitted together so that a first passive element of first sheet-like substrate and a second passive element of second sheet-like substrate configure a filter circuit.