Abstract: An electronic package and method of making the electronic package is provided. The package includes a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip.

Abstract: A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers comprise a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing line terminates in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip.

Abstract: A substrate assembly and method of forming the substrate assembly having a very thin form factor and a large amount of manufacturing flexibility. A flexible tape has a number of device blocks. Devices, passive or active, are joined to the device blocks forming a flexible tape assembly and the flexible tape assembly is electrically tested. Substrates are formed having cavities matching the device blocks. The flexible tape assembly is then joined to the substrate such that the devices fit into the cavities, thereby forming a substrate assembly having a very thin form factor. The flexible tape can be stored on a reel and the substrates can be formed in an array and cut to the desired size providing manufacturing flexibility.

Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 &mgr;m thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.

Abstract: Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.

Abstract: An assembly including a magnetic head for recording information using a chip based assembly. The assembly includes a chip mounted on a base where a printed circuit with conducting tracks underneath is passed through the base to come into contact with the chips's connection studs. Also disclosed is the process for the manufacture of chip based assemblies.

Abstract: A printed wiring board includes a core substrate including a laminated capacitor. The laminated capacitor includes a plurality of composite dielectric layers and a plurality of metal layers stacked alternately. Three types through-hole conductors are provided which extend between the upper and lower surfaces of the core substrate. The first through-hole conductors are directly connected to first metal layers serving one electrode of the laminated capacitor, the second through-hole conductors are directly connected to second metal layers serving the other electrode of the laminated capacitor, and the third through-hole conductors are not connected to any of the first and second metal layers. The first and second through-hole conductors are used for establishing electrical connections between power supply and ground lines and an IC chip mounted on the printed wiring board. The third through-hole conductor is used as a signal line.

Abstract: A sheet metal component (8) for pattern conduction comprises a lead portion (8a) that is connected to an end portion of a first portion (8c1) of a ceiling portion (8c) by a coupling portion (8d) forming a first bend (R1); and a portion to be soldered (8b) that is bent inwardly from an end portion (8c2E, 8c3E) of a longitudinally protruding second portion (8c2, 8c3) of the ceiling portion (8c), which is connected to the first portion (8c1), so as to form a second bend (R2).

Abstract: A circuit board (1) for use in a connector between cables of a data transmission system has at least one array of input terminals (T1-T8) for incoming signals, at least one array of output terminals (t1-t8) for outgoing signals, and a respective conductive track (5) connecting each input terminal to a respective output terminal. Closed loops (6, 7, 8) of conductive material are connected to at least some of the terminals or conductive tracks, the loops being positioned on the circuit board to reduce crosstalk from the levels which would exist within the connector in the absence of such closed loops. The loops associated with one terminal will be positioned on the board opposite loops associated with another terminal or terminals to produce coupling therebetween. The invention is particularly applicable to RJ45 plug and jack systems.

Abstract: An electrode spacing conversion adaptor is formed of a plurality of sheet elements having top and bottom electrodes arrayed at different intervals along upper and lower ends of each sheet element, respectively, wherein the top electrodes are individually connected to their corresponding bottom electrodes by intermediate conductors. The individual sheet elements are angled such that the upper portions of the sheet elements carrying the top electrodes are stacked at intervals different from intervals at which the lower portions carrying the bottom electrodes are stacked. The individual sheet elements may be stacked to form laminated pieces in such a way that the bottom electrodes are concentrated in a small area while the top electrodes are distributed over a larger area at greater intervals in two horizontal directions.

Abstract: A multilayer, monolithic electrical interconnection device includes a substrate and a plurality of overlaying, alternating conducting and insulating layers deposited atop the substrate and one another. The layers are deposited by thermal spraying of respective insulating or conducting material through defined apertures in respective spray masks. Interlayer electrical connections are intrinsically formed by direct metallurgical bonding between the conducting material of an overlaying layer and the conducting material of a previously sprayed layer.

Abstract: Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.

Abstract: A multilayer printed wiring board prevents unnecessary emission of electromagnetic waves. The board includes at least two signal wiring layers, at least one ground layer, at least one power source layer, and a ground plane. The board further includes ground wiring adjacent to signal wiring in a signal wiring layer farther apart from said ground layer, the ground wiring being in the signal wiring layer. The ground wiring serves as a return current path for a signal current flowing in the signal wiring. In this structure, the return current path is reserved adjacent to the signal current path and the signal wiring is lower in impedance than the ground plane. The current can be fed back through a shorter closed loop. It is therefore possible to form a small loop to pass a signal current returning to a ground point and flowing through each signal wiring arranged in the board and a return current of the signal current. This minimizes unnecessary emission of electromagnetic waves.

Abstract: Multilayer printed wiring board capable of effectively solving the swelling of the conductor layer resulting from residual solvent and lowering of adhesion property between a resin insulating layer and a conductor. The multilayer printed wiring board can be formed by laminating resin insulating layers and conductor layers on a substrate, wherein, among conductor layers at least constituted with signal layer and power layer, a conductor pattern of the power layer is of lattice-shaped form.

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 &mgr;m in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract: A printed wiring board reduced in weight by reducing the size and the thickness of a substrate in its entirety. The printed wiring board includes a rigid substrate 2, comprised of a core material 11 at least one side of which carries a land 23, and flexible substrates 3, 4, 5 and 6 comprised of core materials 33, 36 on at least one surface of which a bump 32 for electrical connection to the land 38 is formed protuberantly. The rigid substrate 2 and the flexible substrates 3 to 6 are molded as one with each other, with the interposition of an adhesive in-between, so that the land and the bump face each other.

Abstract: A semiconductor device includes a ball grid array substrate including an upper insulating layer of laminated insulating layers, an intermediate insulating layer, and a lower insulating layer of laminated insulating layers; lines on each top surface of the insulating layers included in the upper insulating layer, the intermediate insulating layer, and the lower insulating layer, respectively; and a semiconductor chip having electrodes connected to the lines, the semiconductor chip being connected with solder balls through via holes in each of the insulating layers, the solder balls being located on an outermost surface of the lower insulating layer.

Abstract: In printed circuit board fabrication, processing steps for components on one section of the board are sometimes incompatible with processing steps for components on another section of the board. The method of the invention provides for physically separate printed circuit board sections that are processed separately and joined together following processing. To provide electrical connection between a first component on a first printed circuit board section and a second component on a second printed circuit board section, the method of the invention includes the steps of connecting the first and second components to conducting regions disposed on edges of their respective printed circuit board sections. The two printed circuit board sections are then joined together so that the two conducting regions contact each other.

Abstract: A printed circuit board includes a plurality of dielectric substrates. Each of the dielectric substrates includes a first and a second surface and has a first conductive layer formed on the first surface of the respective dielectric substrate. A first pattern of lands is formed in the conductive layer of at least two of the dielectric substrates. The pattern of lands of each dielectric substrate is substantially the same. An opening is formed through each of the lands to expose the respective dielectric substrate. Each of the openings in a respective pattern of lands has a diameter different than at least a portion of the other openings in the same pattern. The plurality of dielectric substrates are laminated in stacked relationship.

Abstract: The present invention provides a multilayer print circuit board having at least an inner print circuit pattern and an outer print circuit pattern which are laminated on a substrate through an insulation layer and being electrically connected to each other through a blind hole provided in the insulation layer. The insulation layer is composed of a resin insoluble in an oxidization agent and inorganic powder dispersed in the resin. The inorganic powder is soluble in the oxidization agent. The surface of insulation layer and the wall of the blind hole are roughed by the oxidization agent before the outer print circuit pattern is formed on the surface of the insulation layer by plating, whereby the inorganic powder exposed to the oxidization agent is melted therein, resulting in the roughed surface of the insulation layer and the wall of the blind hole.

Abstract: The present invention provides a multilayer print circuit board having at least an inner print circuit pattern and an outer print circuit pattern which are laminated on a substrate through an insulation layer and being electrically connected to each other through a blind hole provided in the insulation layer. The insulation layer is composed of a resin insoluble in an oxidization agent and inorganic powder dispersed in the resin. The inorganic powder is soluble in the oxidization agent. The surface of insulation layer and the wall of the blind hole are roughed by the oxidization agent before the outer print circuit pattern is formed on the surface of the insulation layer by plating, whereby the inorganic powder exposed to the oxidization agent is melted therein, resulting in the roughed surface of the insulation layer and the wall of the blind hole.

Abstract: A compact thick film substrate for filtering, shielding, and routing multiple lines of dc and control signals between isolated ports of a microwave integrated circuit. The substrate circuit includes a dielectric substrate having upper and lower substrate surfaces and first and second side surfaces. A first ground plane layer is formed on the upper substrate surface.

Abstract: An integrated circuit chip package which has improved bond strength formed between an IC die and a printed circuit board or an interposer is provided. The improved bond strength is achieved by providing a roughened surface on the printed circuit board or the interposer such that a mechanical interlocking effect is achieved between the IC die and the PCB or the interposer. The roughened surface can be provided by a multiplicity of recesses in a top surface of the PCB or the interposer such as a multiplicity of dimples or surface grooves provided by either a chemical etching method or a mechanical abrasion method. The depth of the multiplicity of recesses should be such that a desirable mechanical interlocking effect is achieved between the components to be bonded together in the IC package.

Abstract: A multilayer wiring board comprising a mother wiring board and a carrier wiring board, in which all of the composing layers have IVH structure. The mother wiring board (11) is formed in the manner that a plurality of resin-impregnated-fiber-sheets having mother wiring layers (13) and first inner-via-hole conductors (14) for connecting the wiring layers (13) each other are laminated. The mother wiring board (11) comprises a base board (11a) and container board (11b) having an opening for forming a cavity (15). The carrier wiring board (16) has lands (17) for mounting LSI bare chips, wirings (18), a plurality of carrier-board-wiring-layers (19) and second inner-via-hole conductors (20) for connecting the wiring layers (19) each other.

Abstract: An electronic circuit package assembly of the present invention and implemented by a TAB (Tape Automated Bonding) system includes a sheet formed of thermosetting resin. The sheet intervenes between a substrate and an organic insulating film carrying an LSI (Large Scale Integrated circuit) chip thereon. Solder is buried in the sheet beforehand. The assembly is heated to cause the solder to melt and connect wiring electrodes formed on the substrate and outer leads provided on the organic insulating film. The assembly has high reliability as to connection using solder and migration.

Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.

Abstract: Semiconductor chips, such as photosensor arrays in a full-width scanner, are mounted on printed wiring boards. The printed wiring boards are in turn mounted on a second layer of printed wiring board material. The two layers of printed wiring board material are attached so that the seams between adjacent printed wiring boards in each layer alternate in a brick-like fashion. This structure enables arrays of semiconductor chips to be constructed in relatively long lengths, with minimal risk of damage caused by thermal stresses.

Abstract: A circuit board substrate assembly includes a generally planar circuit board substrate material having a longitudinal axis extending along a length of the substrate material between a first end and a second end thereof. The circuit board substrate material further has a first edge and a second edge extending along the length of the circuit board substrate material between the first end and the second end. A plurality of openings are defined in the substrate material. Each opening extends between a first distance from the first edge of the circuit board substrate and a second distance from the second edge of the circuit board substrate. Further, each opening separates adjacent circuit forming regions lying along the longitudinal axis and has first and second opposing end portions.

Abstract: A multilayer type electronic part includes a laminated structure formed by stacking a plurality of first and second ceramic layers, the first ceramic layers being provided with internal electrode patterns on top thereof, the second ceramic layers having no internal electrode pattern and being located at a top and a bottom portions of the laminated structure, respectively, the internal electrode patterns being connected to each other to form a coil inside the laminated structure, a pair of external electrodes provided at two opposing sides of the laminated structure and connected to the coil. The multilayer type electronic part further includes one or more third ceramic layers, each of the third ceramic layers not including internal electrode pattern and being interposed between the first ceramic layers, and means for connecting the internal electrode patterns formed on the first ceramic layers to form the coil.

Abstract: An assembly including a printed-circuit electronics card mounted on a metal substrate, and in electronic communication with the same, includes a capsule which is crimped into a cavity in the metal substrate and which extends through a hole in the electronics card, the edges of said hole being metallised, the capsule being soldered to the metallised area of the edges.

Abstract: A multilayer circuit board includes multiple conductor path planes arranged one above another and separated by insulating material layers. The multilayer circuit board includes at least one electronic component (in particular an LCCC) placed on one of the two outer sides of the multilayer circuit board. The multilayer circuit board includes at least one core substrate arranged in the multilayer circuit board between the outer insulating material layers. The core substrate largely adapts the thermal expansion properties of the multilayer circuit board, at least in the coverage area of the electronic component, to the thermal expansion properties of the component. In order to achieve a reduction in the weight of the multilayer circuit board, an inner layer portion, equipped with a recess, is provided between the two outer insulating material layers.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects.

Abstract: A structure for reducing cross-talk in VLSI circuits is disclosed. By filling voltage and ground metal lines in free or unused channels of VLSI chips and connecting them efficiently to the regular power image of the chip, the line to line coupling through vertical layers is reduced almost to zero and in-layer line to line coupling is also drastically reduced.

Abstract: A cooling system for a circuit board employs a heat-conducing channel within the board. The channel is thermally coupled to an electrical device mounted on the board, and leads to an edge of the board. The edge of the board is coupled to a heat-dissipating can. The use of channels leading to the edges of the board allows a single can to dissipate heat for a plurality of boards and a plurality of devices.

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

Abstract: In the glass-ceramic composition, a weight ratio of a glass and a ceramic is 40 to 60:60 to 40. The glass is composed of 40 to 60 wt % of SiO2, 5 to 9 wt % of Al2O3, 1 to 10 wt % of B2O3, 3 to 5 wt % of Na2O+K2O, 3 to 15 wt % of CaO+MgO+ZnO, and 15 to 40 wt % of PbO, and does not contain Li2O. A softening point of the glass is 650 to 780° C. The circuit substrate includes a laminate substrate formed by laminating insulating substrates, and a conductor circuit formed on a surface of each insulating substrate. The insulating substrate is formed of the glass-ceramic composition. A wiring layer and a via hole conductor are provided inside the laminate substrate.

Abstract: A flexible printed circuit unit includes a flexible printed circuit board having one or more electronic parts mounted on a front surface thereof. A reverse side reinforcing plate is provided at a location of the reverse side of the flexible printed circuit board corresponding to a region in which the electronic parts are mounted. An upper reinforcing structure is provided on the front surface of the flexible printed circuit board for covering at least one of the electronic parts.

Abstract: A multi-layer circuit board formed by laminating a plurality of circuit boards each having lands arranged in many number in the form of a lattice or in a staggering manner on the side of the mounting surface and having circuit patterns with the ends on one side thereof being connected to said lands and with the ends on the other side thereof being drawn toward the outside from a region where said lands are arranged; wherein the lands for drawing the circuit patterns in a number not less than a+1 are arranged on the oblique lines of an isosceles triangle having a base formed by consecutive lands of a number of n and having oblique lines in the diagonal directions, the value n satisfying m≧k+1 of the two values of: m={(land pitch)×(n−1)−(land diameter)−(space between patterns)}÷(pattern width+space between patterns), k=a(n−1)+(n−2), wherein “a” is the number of the circuit patterns that can be arranged betwe

Abstract: A substrate for reducing electromagnetic emissions is provided. The substrate may include a plurality of ground layers, signal layers and power layers. All of the layers other than the ground layer are provided with a ground ring that may extend around the perimeter of the layer. The ground rings are electrically coupled together by ground stitching or vias that are randomly spaced. The random spacing of the ground stitching is based on the operating frequencies of the integrated circuit devices mounted on the substrate. Additional shielding may be provided by providing a cover assembly made of any conductive material that is coupled to the exposed ground rings on the uppermost and lowermost surfaces of the substrate. The cover assembly is coupled to the exposed ground rings in a randomized pattern. The device provides a virtual electrical ground cage in which the internal signal layers are totally enclosed, thereby reducing electromagnetic emissions.

Abstract: Disclosed is a multilayer (e.g., 4-layer) printed circuit board and method of manufacture thereof. The multilayer printed circuit board has at least one inner substrate (inner core) that includes a phenolic resin (e.g., a phenolic resin-laminated paper). Outer insulating layers of the multilayer printed circuit board can have a low dielectric constant (e.g., 3.8-4.4) and a high Tg (e.g., 180°-200° C.). The multilayer printed circuit board can be provided by steps including forming electrical circuit patterns from a copper foil on the inner substrate, to form a printed circuit board, forming a stack of at least one printed circuit board and outer copper foil layers, with insulating layers of, e.g., a semi-cured resin (e.g., prepreg layers) interposed between adjacent conductive metal layers, and then laminating the stack.

Abstract: An information handling system is provided which comprises: a metal enclosure; at least one circuit assembly positioned within said metal enclosure, said circuit assembly including a circuitized substrate having at least one dielectric interior layer including a first surface and at least one hole therein; means for providing electrical power to said circuitized substrate within said metal enclosure; a filler material, wherein said filler material substantially fills said at least one hole within said at least one dielectric interior layer; a first wiring layer positioned on said first surface of said at least one dielectric interior layer, wherein said first wiring layer substantially covers said at least one hole having said filler material therein, said first wiring layer assisting in retaining said filler material within said at least one hole in said at least one dielectric interior layer; a first dielectric photoresist layer positioned on said first wiring layer and on said first surface of said at lea

Abstract: First to fourth power wiring conductors and first to fourth ground wiring conductors are arranged on first to fourth insulating layers, respectively, and a first signal wiring conductor is arranged on the first or second insulating layer and a second signal wiring conductor is arranged on the third or fourth insulating layer.

Abstract: A system involving an active (i.e. electrical) technique for the verification of: 1) close tolerance mechanical alignment between two component, and 2) electrical contact between mating through an elastomeric interface. For example, the two components may be an alumina carrier and a printed circuit board, two mating parts that are extremely small, high density parts and require alignment within a fraction of a mil, as well as a specified interface point of engagement between the parts. The system comprises pairs of conductive structures defined in the surfaces layers of the alumina carrier and the printed circuit board, for example. The first pair of conductive structures relate to item (1) above and permit alignment verification between mating parts. The second pair of conductive structures relate to item (2) above and permit verification of electrical contact between mating parts.

Abstract: A board mount assembly. The assembly comprises a panel, a board mount and a circuit board. The panel is generally arranged in a plane. The board mount has an attachment portion operably connected to the panel and parallel thereto, and has a support portion extending from the first portion at a non-perpendicular angle relative to the plane of the panel. The circuit board has a first standoff engaged with the board mount.

Abstract: Ceramic circuit substrate which is sintered at 900 to 1,050.degree. C. and have low relative dielectric constant, thermal expansion coefficient comparable to that of silicon, and high bending strength, and a method of manufacturing are provided by using a glass with a softening point of 850 to 1,100.degree. C., that is, a glass having a composition included in an area in FIG. 1 (triangular composition diagram of SiO.sub.2 --B.sub.2 O.sub.3 --R.sub.2 O, a composition is represented by the position of a small circle, the number in a small circle represents the composition number) defined with lines connecting points representing the first, third, tenth, eleventh, and fourth compositions respectively as raw material.

Abstract: Under one aspect of the invention, the invention includes a multilayered substrate. The substrate includes a primary side having a first group of connection points, including a first connection point, having a first layout to interface with a first chip. The substrate also includes a secondary side having a second group of connection points, including a second connection point, having a layout identical to the first layout, to interface with a second chip. The substrate also includes an intermediate connection point coupled to the first and second connection points through first and second branch traces each having substantially the same electrical length.

Abstract: A connector is provided which can simplify the path for heat radiation between electronic devices, ease restrictions in the structures of the electronic devices and in the arrangement of parts on the printed circuit boards, and reduce work for the highly precise setting of mounting intervals between connecting components. A connecting structure between electronic devices using the above connector is also provided. Heat from electronic parts 71 on a printed circuit board 61 which is provided in an electronic device 11 is conducted to a radiating plate 41. The heat is conducted to a male connecting component 20 by metallic portions 51 which are provided in the back of the male connecting component 20. Then, the heat is conducted from the male connecting component 20 to a female connecting component 30. The heat is conducted from the female connecting component 30 to a radiating plate 42 by metallic portions 52 which are provided in the back of the female connecting component 30, and radiated.

Abstract: An article comprising a molded circuit for providing a path for electrical current is disclosed. The molded circuit is formed of a first material layer and a second material layer. The first material layer is an electrically insulating material. The second material layer is an electrically conductive material. In an alternate embodiment, the second material layer is surrounded between two layers of the first material layer. The molded circuit can be formed using multi-material injection molding such as co-injection molding or two-shot injection molding. A printed circuit board can comprise the molded circuit.

Abstract: A universal multi-chip interconnect system using a set of at least two types of standardized interconnect components is disclosed. One of the component types comprises a chip carrier capable of holding at least one IC chip in a first portion thereof and providing a plurality of standardized interconnections from the first portion to one or more second portions of the carrier, where one or more interconnect components of a different type may be connected. Another of the component types comprises a bridge connector which is capable of connecting to two or more chip carriers at their second portions. Each bridge connector has at least two interconnect portions which are capable of connecting to chip carriers at their second portions, and a standardized pattern of interconnect wires between the interconnect portions.