Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: A multilayer wiring board comprising a plurality of conductor patterns stacked with an insulating layer composed of a thermosetting resin interposed between adjacent conductor patterns, wherein the insulating layers are each formed of a pair of film-like thermosetting resin layers and a resin film having a lower coefficient of linear expansion than, and sandwiched between, the thermosetting resin layers, and wherein the electrical connection between the stacked conductor patterns is established by vias formed through the insulating layers. A method of fabricating such a multilayer wiring board is also disclosed.

Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads while the second wiring layer includes a plurality of second pads. The interconnection-wiring layer is set between the first and second wiring layer. In this case, at least one of the second pads isn't electrically connected with anyone of the first pads, and other second pads that located adjacent to this second pad, which is not electrically connected with the first pads, electrically connect to the interconnection-wiring layer. Furthermore, this invention also discloses a semiconductor device including the substrate.

Abstract: A system and method for providing high voltage resistance capability in a receptacle apparatus for accepting a high-density compliant pin connector. A plurality of high-density compliant pin through-holes are formed in a printed circuit board for receiving the pins of the high-density compliant pin connector. The through-holes are plated using an electrically conductive material, whereby conductive pads are formed around the plated through-holes on at least one side of the printed circuit board. Thereafter, the conductive pads around the plated through-holes on the printed circuit board are removed by controlled depth back-drilling so as to increase the inter-pad clearance of the through-holes for withstanding foreign voltages.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Abstract: An electronic device includes a primary circuit board, a secondary circuit board, and a plurality of metallic balls electrically connected between the primary circuit board and the secondary circuit board for transmitting signals between the primary circuit board and the secondary circuit board.

Abstract: The present invention comprises a plurality of laminating double-side circuit boards and a plurality sheets of prepreg for interlayer connection that are placed one on another. Via holes extend from the circuit on one side of each laminating double-side circuit board to the circuit on the other side thereof. Each via hole is filled with electro-conductive material to connect the circuits on both sides of the laminating double-side circuit board. The pad on a laminating double-side circuit board and the pad on another laminating double-side circuit board are laminated via a sheet of prepreg for interlayer connection so that the respective pads are opposed to each other via the through hole filled with electro-conductive material formed through the sheet of prepreg for interlayer connection. Thereby, the respective pads on the laminating double-side wiring circuit boards are electrically connected with one another.

Abstract: A chip carrier is coupled to a printed circuit board by leads so that the chip carrier stands off from the printed circuit board. A spacer is provided between the chip carrier and the printed circuit board. The spacer reduces g forces on the leads.

Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Abstract: Against a first resin film formed on a first metal film are pressed bumps on a second metal film so that the bumps are embedded into the first resin film. Either one of the first metal film or the second metal film or both is (are) patterned while the bumps are in contact with the first metal film, and the first resin film is heat-treated while the top of the first resin film is partially exposed to discharge the solvent or moisture from the exposed zone, and cure the first resin film. After curing, the bumps and the first metal film may be ultrasonically bonded to each other. A second resin film and a third metal film may be further layered to form a multilayer structure.

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract: A powerplane for use in a backplane power distribution system. The backplane includes a conductive sheet for distributing power from a power source to a load. The powerplane further includes source locations and load locations for coupling the conductive sheet to a power source and a load. The conductive sheet has resistances with appropriate spacing and dimensions so that the resistance near the source locations is greater than the resistance farther away from the source locations. Thus, current is shared more evenly between all the load locations, and the voltage difference between distant load locations and near load locations is reduced to near zero.

Abstract: A wire bond-less electronic component is for use with a circuit external to the wire bond-less electronic component. The wire bond-less electronic component includes a support substrate (110, 410), an electronic device (130) over the support substrate, and a cover (140, 440, 540) located over the electronic device and the support substrate. The cover includes an interconnect structure (141, 441, 541) electrically coupled to the electronic device and adapted to electrically couple together the electronic device and the circuit for providing impedance transformation of an electrical signal between the electronic device and the circuit.

Abstract: A plurality of one-sided conductive pattern films made of resin films are piled up to form a pile with sandwiching in a given region a release film that is easily released from the resin films. The pile is then heated and pressurized to form a multi-layer board. After components are mounted on the surface of the multi-layer board, the multi-layer board and the release film are separated from each other. At least one separation board is then folded at an angle relative to a position prior to being separated. Components are mounted on the released surfaces of the separation boards. Thus, newly mounting the components on the released surfaces of the separation boards enables high-density mounting without enlarging the superficial dimensions of the multi-layer itself and adding a new board.

Abstract: The memory module includes a substantially rigid first circuit board having at least one memory chip disposed thereon. The memory module also includes a substantially rigid second circuit board having an array of electrical contact points disposed on a planar surface thereof. A flexible connector electrically couples the first circuit board to the second circuit board, such that the memory chip is electrically connected to the array of electrical contact points. Alternatively, the memory module that rigid/flex circuit board. The rigid/flex circuit board includes a substantially rigid first section having at least one memory chip disposed thereon, and a substantially rigid second section having an array of electrical contact points disposed on a planar surface thereof. The rigid/flex circuit board also includes a flexible third section in-between the first section to the second section.

Abstract: The invention provides a magnetic head capable of positively preventing electrostatic breakdown of an MR magnetic head device, and a method of manufacturing the magnetic head. A circuit board comprises at least a pair of leads for constructing a circuit, lands connected respectively to the leads, and solder bumps formed respectively on the lands. The solder bumps are arranged in an adjacent relationship and, when the solder bumps are crushed, peripheral portions of the solder bumps are pressed or spread so as to overlap with each other. The magnetic head includes the circuit board.

Abstract: A surface-mounting substrate, for mounting thereon a part such as a semiconductor device, which comprises a core substrate, a plurality of layers of patterned wiring lines, which are separated from each other by an insulation layer interposed therebetween, vias piercing through the insulation layer to connect the wiring lines at the adjacent layers to each other, and a layer of connecting terminals to mount a part on the surface-mounting substrate, each of the connecting terminals connecting with the wiring line at the outermost layer of wiring lines, wherein the connecting terminal is filled in an outermost insulation layer provided at the surface of the surface-mounting substrate, and has a surface exposed at substantially the same level as the level of the surface of the outermost insulation layer. A structure comprising a surface-mounting substrate and a part mounted thereon, which comprises, as the substrate used, the surface-mounting substrate of the invention, is also disclosed.

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract: Disclosed are electrical connector devices with integrated electronic components, including magnetic devices. The electronic components integrated into the connector are electrically connected to one another and the connector pins by an electrically conductive circuit formed directly on the connector housing. Formation of the electrically conductive circuit directly on the connector housing substantially reduces the number of assembly steps required to manufacture the connector.

Abstract: A multilayered circuit board has good imbedding properties for circuit patterns, and an interlayer insulating material having superior adhesive force and interlayer insulating properties. In a multilayered circuit board wherein interlayer connection is achieved by the contact of minute pointed protrusions, provided on a first conductive circuit layer, with a second conductive circuit layer, interlayer insulation is achieved by a film having a three-layer structure, comprising a thermoplastic film inserted between a pair of thermosetting adhesive layers.

Abstract: A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.

Abstract: In a semiconductor device, the likely occurrence of cracking of a ceramic substrate, and the consequential disconnection of internal layer wiring, due to thermal changes suffered when the semiconductor device is mounted on external wiring boards having different thermal expansion is prevented. The semiconductor device has a ceramic substrate, a wiring pattern formed on a first principal plane and having mounted semiconductor components, an external electrode portion formed on a second principal plane and connected to an external circuit, internal layer wiring formed inside said ceramic substrate to electrically connect said wiring pattern and said external electrode portion via through-hole wiring, and semiconductor components and a resin layer covering said semiconductor components, wherein the internal layer wiring is formed internally with respect to the side of said ceramic substrate with a clearance of at least 0.05 mm.

Abstract: A conductive bond comprises conductive colloidal particles and a dispersant for dispersing the conductive colloidal particles. A multilayer printed circuit board includes a plurality of substrates, each having a conductive pattern on at least one face thereof. Any adjacent two of the substrates are separated by an insulating layer, and the conductive pattern of a first substrate of the two substrates faces the conductive pattern of a second substrate of the two substrate. The conductive pattern of a first substrate has one or more bumps for electrical connection to the second substrate. The bump and the conductive pattern of the second substrate are bonded to each other with the conductive bond applied to the tip of the bump.

Abstract: A low temperature co-fired ceramic assembly (LTCC) with a constraining core of differing dielectric constants that minimizes shrinkage of the outer ceramic layers during firing. The ceramic assembly has a planar ceramic core. The core has a first ceramic layer with a first dielectric constant and a second ceramic layer adjacent to the first ceramic layer. The second ceramic layer has a second dielectric constant. A third ceramic layer has a third dielectric constant. A fourth ceramic layer has a fourth dielectric constant. The ceramic core is located between the third and the fourth ceramic layers. Several electrically conductive vias extend through the first, second, third and fourth ceramic layers. Several circuit features are located on the first, second, third and fourth ceramic layers. The vias electrically connect the circuit features on the layers.

Abstract: A method of reducing electromagnetic interference and improving signal quality in printed circuit boards with plane splits is described. The use of a lossy slot filling is described. The lossy filling is applied above plane splits and squeezed into the slots. The lossy material helps to damp antenna resonance.

Abstract: A method of fabricating a semiconductor package is disclosed in which a first Ni—Au plating is formed on a bonding pad for connection with a semiconductor chip, without a mechanical process or a masking operation. The method applies a copper plating on a through bore and the bonding pad, where the copper plated layer formed on the bonding pad is selectively removed, and then a second Ni—Au plating is formed on the bonding pad and a ball pad.

Abstract: A printed circuit board (PCB) includes a first layer having first and second surfaces, with an above-board device mounted thereon. The PCB includes a second layer having third and fourth surfaces. One of the surfaces can include a recessed portion for securedly holding an interstitial component. A via, electrically connecting the PCB layers, is also coupled to a lead of the interstitial component.

Abstract: A printed wiring board is formed by a printed wiring substrate having a plurality of a wiring layer, and a thermal expansion buffering sheet having lower coefficient of thermal expansion than that of said printed wiring substrate, which is integrally laminated on a surface of the printed wiring substrate.

Abstract: The invention relates to a transponder provided with an integrated circuit, an antenna, and a first capacitor provided with a dielectric and a first and a second capacitor electrode, which transponder comprises a stack of layers, i.e.: a first layer of a dielectric material, a first patterned electrically conductive layer of which the antenna forms part, a second layer of a dielectric material, and a second patterned electrically conductive layer. The invention further relates to an appliance provided with a transponder which comprises an integrated circuit, an antenna, and a first capacitor.

Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.

Abstract: Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.

Abstract: A two layer PBGA which includes a metal ground plane at its bottom layer. The ground plane is preferably a metal plane which is connected to ground through a metal connection to a ball pad at the center of the package and a ball pad proximate the edge of the package. The ground plane is voided around the signal and power balls, via and “dog bones”. The PBGA is configured such that the ground plane serves effectively the same function as the second layer ground plane in a conventional four layer PBGA. The PBGA provides a cheaper alternative to the generally more expensive four layer PBGA, and provides better cross talk performance (especially for high frequency signaling) as well as better thermal performance as a result of having more metal at the bottom layer of the package.

Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.

Abstract: An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.

Abstract: Electronic equipment has two electronic circuit boards in a casing, which is constructed of a base and a cover. Two electronic circuit boards are piled up in the casing. A first electronic circuit board is, for example, for a radio communication unit, and a second electronic circuit board is, for example, for a control unit. The first board has a portion that does not face the second board. The first board is attached to the base. Heat, which is generated by the first board, conducts by heat contact from the first board to the base and the case of the casing through the contact portion of the first board with the base.

Abstract: A structure for eliminating electromagnetic interference caused by CPU includes a fixing seat, onto which two conductive members having a plurality of elastic contacts are mounted. Each of the conductive members is formed at two ends with two contact wings that are in contact with contacts of a demagnetizing circuit provided on a circuit board onto which the fixing seat is assembled with fastening members. When a central processing unit mounted on the circuit board operates and generates electromagnetic waves, the same are received by a radiator mounted on the fixing seat in contact with the conductive members, and then guided by the conductive members from the radiator to the demagnetizing circuit and be eliminated.

Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.

Abstract: A low temperature co-fired ceramic assembly (LTCC) with a constraining core of differing dielectric constants that minimizes shrinkage of the outer ceramic layers during firing. The ceramic assembly has a planar ceramic core. The core has a first ceramic layer with a first dielectric constant and a second ceramic layer adjacent to the first ceramic layer. The second ceramic layer has a second dielectric constant. A third ceramic layer has a third dielectric constant. A fourth ceramic layer has a fourth dielectric constant. The ceramic core is located between the third and the fourth ceramic layers. Several electrically conductive vias extend through the first, second, third and fourth ceramic layers. Several circuit features are located on the first, second, third and fourth ceramic layers. The vias electrically connect the circuit features on the layers.

Abstract: A hub includes a bluetooth system module coupled to a hub module. The hub module is also coupled to an upstream port and a plurality of downstream ports provided on a housing of the hub respectively enabling the hub to connect to an electronic device via the upstream port and to connect to a plurality of peripherals via the downstream ports for performing a wireless signal communication therebetween, thereby reducing the number of cables connected between the electronic device and peripherals.

Abstract: A multi-layer printed circuit board (PCB) has a plated through hole for receiving a pin of a component. The plated through hole passes through all layers of the PCB and includes a first conductive portion on a first surface of the PCB and a second conductive portion on a second surface of the PCB. At least one layer of the PCB includes a planar conductive material disposed over a planar insulating material. The conductive material surrounds the plated through hole and is separated therefrom by a gap.

Abstract: The power substrate is inserted in a housing (1) as base plate and together with the same forms a standardized power part from whose top side (11) there are projecting terminal pins (5) which are soldered by through-soldering to via holes of the board (4). The circuit board (4), in a strip portion (6) thereof that remains free, has contact pads (7) as control and power terminals by means of which the module can be soldered directly into the slot-like opening of a system circuit board (8).

Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.

Abstract: A circuit board assembly that includes a circuit board and a bracket. The bracket has a first flange, a second flange, and a third flange. The first flange and the second flange are coupled to the circuit board. The circuit board assembly also includes a switch mounting board. The switch mounting board is coupled to the third flange of the bracket. The circuit board assembly also includes a first switch and a second switch, which are coupled to the switch mounting board. The circuit board assembly further includes a connector that is coupled to the circuit board. At least a first portion of the connector is positioned between the circuit board and the first switch. At least a second portion of the connector is positioned between the circuit board and the second switch.

Abstract: A method for determining a wiring pattern of a signal line for connection of a circuit on a multi-layer printed wiring board includes the steps of providing a constraint of an electrical length which the signal line must satisfy, determining an electrical length change at a discontinuous delay part of the signal line along which a signal propagates, determining a wiring route of the signal line, calculating an electrical length of the signal line with use of a wiring length of the signal line and the determined electrical length change, judging whether or not the calculated electrical length satisfies the electrical length constraint given to the signal line, and determining the wiring route as a wiring pattern when the electrical length constraint is satisfied as the decision result, thereby carrying out a wiring layout to make an electrical length constraint satisfied.

Abstract: An electronic board assembly carrying connectors on each side of its lower edge which is adapted to withstand the relatively strong forces required to insert or remove the assembly, e.g., from a backplane board, and yet provide many electrical contacts along the interconnection sites. The electronic board assembly comprises two symmetrical elementary PCBs electrically coupled together, each carrying a connector on its external lower edge. In one embodiment, these two PCBs are coupled together by a flexible adhesive insulative layer and maintained by mechanical devices such that the distance between these two connectors is set to a predetermined distance (to align precisely with the backplane board). The mechanical device used to maintain a predetermined distance between the two connectors of the assembly may comprise a U-shaped member, the upper part of this member being strategically inserted between these connectors.