Abstract: An area array interconnect device (such as of the TAB type) has a plurality of input/output (I/O) leads for connection to an electronic device such as an IC. The interconnect device also has arrays of lead lines in areas remote from the I/O leads, e.g., central or internal areas, which are connected by vias to ground and/or power pads on corresponding areas of the electronic device.

Abstract: A multilayered printed wiring board includes a plurality of inner layer circuits, ground layers, first insulating layers, a second insulating layer, a surface layer circuit, and a parts mounting pad. The inner layer circuits are arranged parallel to each other in a flat manner in at least one inner layer. The ground layers are formed on and under the inner layer circuits to sandwich the inner layer circuits. The first insulating layers are respectively formed between the ground layers and the inner layer circuits to insulate the inner layer circuits from each other and the inner layer circuits from the ground layers. The second insulating layer is formed at least on an uppermost one of the ground layers and serving as a surface layer. The surface layer circuit is selectively formed on the second insulating layer.

Abstract: The radiation noise suppression effect is enhanced by providing an insulation layer which is formed so that the circuit pattern is covered excepting at least a part of power source pattern or ground pattern on the substrate on which circuit pattern is formed, and a conductive layer which is formed so as to be connected to the uninsulated part of the power source pattern or the ground pattern on the insulation layer, by modifying pattern shape of the conductive layer and the insulation layer or by increasing or reducing the number of these layers.

Abstract: A system and method for providing a controlled impedance flex circuit includes providing an insulative flexible substrate having opposed first and second surfaces and having through holes extending from the first surface to the second surface. A pattern of conductive traces is formed on the first surface of the flexible substrate. A film of conductive adhesive is applied to the second surface and to the through holes. The through holes are aligned to contact ground traces in the pattern of conductive traces on the first surface. Thus, a ground plane is established for creating an environment for high frequency signal propagation. The conductive adhesive may be a b-stage epoxy or a thermoplastic material. In the preferred embodiment, a tape automated bonding frame is fabricated.

Abstract: A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements. Carrier tape bonds the integrated circuit chips to the programmable interconnect.

Abstract: An improved printed circuit card or second level electronics package (circuit board) including a laminate of lossy material and dielectric material between the voltage supply plane (Vcc) and the ground (GND) plane. The laminate suppresses common mode noise that is generated by active components on the card or circuit board.

Abstract: In a master slice integrated circuit, a number of connection pads are located in a peripheral edge region of a chip in such a manner that each one power supply pad is interposed between each pair of signal input/output pads and a number of unitary pad arrays each of which consists of a signal pad, a power supply pad and another signal pad located in the named order are repeatedly arranged along a peripheral edge of the chip. Thus, the pad pitch can be reduced to two thirds of the width of an I/O cell, without changing the I/O cell size. In addition, since the power supply pad is located adjacent each of the I/O cells, it is effective to suppress or minimize the power supply voltage noise caused by the simultaneous driving.

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated through holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

Abstract: Multiple circuit functions embodied in electrical circuit lines and areas are supported by a multilayered printed circuit board of various lengths and widths (defining "x" and "y" directions) and of various thicknesses (defining a "z" direction) all on a single board. Several ways of achieving such variations in thickness include providing two layer subassemblies arranged in an alternate and intermediate manner, one subassembly being adapted to support electrical circuit lines and areas, and the other subassembly being formed of thin film dielectric material of various precalculated thicknesses. Another way of achieving a variation in thickness is to limit the surface covered by circuit lines with a pre-calculated core thickness.

Abstract: A mounting structure for an EMI prevention filter which facilitates mounting and dismounting of the EMI prevention filter onto and from an electric wire having a connector to be releasably connected to an electronic apparatus, and which allows reliable mounting of the EMI prevention filter even where the EMI prevention filter and an object electric wire do not conform fully to each other in configuration. An outer holder in which the EMI prevent filter is accommodated is disposed such that the electric wire extends through the inside thereof, and the, the outer holder is resiliently deformed and locked in this condition, where after a second threaded portion is screwed with a first threaded portion to mount the EMI prevention filter onto the electric wire.

Abstract: Disclosed herein is a flexible wiring cable being provided on its forward end with a connecting portion to be connected with a connector, which comprises a base film, a wiring conductor provided on the base film, a dielectric member electrically connected with the wiring conductor in the connecting portion of the base film, and a ground electrode electrically connected with the dielectric member for forming a capacitor with the wiring conductor.

Abstract: An electrical interconnection medium having first and second overlying interconnection layers, each interconnection layer including parallel conductors, the conductors of the first and second interconnection layers being oriented orthogonal to each other, the conductors being interconnected so as to form at least two electrical planes, the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module.

Abstract: A transmission line structure including a central signal conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers of a unitized multilayer circuit structure, a first ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from one side of the central signal conductor stack, and a second ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from another side of the central signal conductor stack such that the central conductor stack is laterally between the first and second ground conductor stacks.

Abstract: A semiconductor circuit device includes a multi-layered substrate comprising a plurality of signal lines sandwiched between a power source line and a ground line, with insulation layers formed therebetween to reduce fluctuation of a ground line potential at the time of simultaneous switching of the signal lines and to increase the operational speed. The signal lines provides bidirectional current paths and is disposed between the current source line and the ground line. The multi-layered substrate is formed around a semiconductor pellet. Electrode pads are formed on the insulation layer over the ground line on the same level as the signal lines and generally on the same level as the main surface of the semiconductor pellet where electrodes pads are formed. Bonding wires are used to electrically connect the electrode pads on the pellet and the electrodes formed on the insulation layer.

Abstract: An electrical interconnection board (e.g., a backplane) in which connection positions are spaced along one dimension of the board. Each connection position includes holes for making electrical connections. Layers of the board each have a pattern of conductive path segments connecting holes at each connection position with corresponding holes at other connection positions. The path segments together define continuous conductive routes along the length of the board. Each conductive route includes path segments which respectively lie on different layers. This arrangement increases the distance along which any two pairs of the conductive routes are adjacent each other on a layer, thus reducing interference (e.g., mutual coupling and crosstalk) and improving signal transmission characteristics.

Abstract: By employing High Density Interconnect (HDI) multi-chip modules (MCMs) having elements of a distributed power supply embedded in the MCM itself, the functions of an MCM and a power converter are combined. The embedded power supply elements include DC-DC or AC-DC converters to convert an input voltage and input current to a relatively lower output voltage and relatively higher output current, thereby decreasing the current requirements of external power supply lines connected to the multi-chip module. The current and voltage outputs may be connected to chip power inputs through relatively short, low-impedance power distribution conductors comprising copper strips direct bonded to a ceramic substrate; alternatively, or in combination with direct bonded copper conductors, the low-impedance power distribution conductors may be situated within an HDI overcoat structure. The power supply elements may be placed within cavities formed in the substrate, or on a thinner portion of the substrate.

Abstract: The multilayer printed wiring board of this invention consists of a base substrate, a plurality of multilayer interconnections formed by lamination of metal wiring layer and insulation layer on the base substrate and ceramic substrates provided with through holes for electrical connection of the multilayer interconnections and inserted between two multilayer interconnections. The manufacturing method comprises lamination of metal wiring layers and insulation layers on both sides of ceramic substrates to form multilayer interconnections, forming of a multilayer interconnection on the base substrate by laminating a wiring layer and an insulation layer, and integration of the ceramic substrates with metal wiring layers and the base substrate placed together under heated and pressurized conditions.

Abstract: A multiple layer printed circuit board and a method of manufacturing multiple layer printed circuit boards which incorporate integral edge shielding in combination with top and bottom shielding to effectively provide a sandwich arrangement within a Faraday Cage. Electromagnetic emissions radiating from an outside surface of either the top or bottom shielding layer are substantially reduced. In one structure, a multiple layer printed circuit board having a sandwich arrangement which includes at least one inner conductive layer for providing a ground plane disposed between the outer shielding layers, the inner conductive layer being electrically connected directly to the edge shield and hence to the outer conductive layers. The larger and more continuous surface area provided by the direct connection to the edge shielding effectively provides an electrical connection having a low inductance and hence in operation results in all ground planes having a more constant non-varying potential.

Abstract: A multilayered wiring board having a printed inductor which is formed on a grounding layer or electric power supply layer through a dielectric layer inserted between them, wherein a removed portion is formed only in the grounding layer or electric power supply layer which is positioned right under the printed inductor and in the neighboring area and no removed portion is formed in the dielectric layer. According to this structure, without increasing the manufacture cost, the distance between the printed inductor and the grounding layer or electric power supply layer opposite to it spreads to the lower electric power supply layer or grounding layer and the stray capacity existing therebetween is reduced, and a reduction of the self-resonance frequency of the printed inductor is prevented, and the frequency characteristics improve.

Abstract: A circuit board includes a circuit-conductor layer, a ground layer and a power source layer superposed in a multilayer form through dielectric layers therebetween, A heat conduction through inside of the circuit board is enhanced so that circuit chips mounted on the circuit board can be cooled down to a level capable of operating normally, The circuit board can be formed to be compact, In order to enhance the heat transfer in the circuit board, at least one of the ground layer and power source layer is formed in a multilayer manner, It is preferable to form these layers at a thickness larger than that of the circuit-conductor layer, Further, preferably, the pin of the chip mounted on the board and at least one of the ground layer and power supply layer are connected to each other in such a manner as to enhance the heat conduction.

Abstract: A DC power supply device for use with a video tape recorder with a built-in camera has a plurality of power supply blocks for supplying a plurality of voltages, each of the power supply blocks being composed of a switching circuit for being supplied with a DC voltage and a smoothing circuit connected to an output terminal of the switching circuit. The power supply blocks are mounted on a multilayer circuit board which includes a layer of a ground pattern with an electric conductor extending substantially fully thereover, the ground pattern being separated into a plurality of ground pattern portions by a plurality of recesses defined therein, the power supply blocks having respective ground terminals connected to the ground pattern portions, respectively.

Abstract: A multi-layer printed circuit board or card including at least one passage in at least one of the layers of the circuit board or card for preventing the diffusion of heat throughout the circuit board or card during the securing or removal of components in plated through holes in the circuit board or card by the heating of the plating material to a temperature above a melting point of the plating material.

Abstract: Mispositioning of chips in a high density interconnect structure is compensated for by including a layer having alignment conductor in the high density interconnect structure without requiring adaptation of the signal conductor metallization levels of the high density interconnect structure. One level, two levels or more of alignment conductor may be employed. The alignment levels of the high density interconnect structure are preferably a ground plane, and if two layers of alignment conductors are provided, a power plane.

Abstract: This invention relates to personal computers, and more particularly to the provision of a shielding structure for attenuating the possible effects of electromagnetic interference on input/output circuits of the computer while structurally reinforcing a side edge portion of a multilayer planar board. The shielding structure has two cooperating constituent parts, one being particularly formed ground plane areas in exterior layers of the planar board and the other being a particularly formed thin sheet metal member which extends about and substantially encloses connectors by which input/output signals are passed to circuits within the planar board.

Abstract: A method for altering an electrical connection in an electronic package including one or more semiconductor chips overlying, i.e., mounted directly onto, or mounted onto one or more modules which are mounted onto, a substrate such as a printed circuit card or printed circuit board, as well as the resulting electronic package, is disclosed. In accordance with a preferred embodiment of the inventive method, at least one plated, solder-filled hole in the substrate is drilled out to eliminate an unwanted electrical connection. A solder region, e.g., a solder ball, is inserted into the drilled out hole into contact with an electrically conductive member, e.g., an electrically conductive pin, extending from, for example, a module into the hole. A cylinder, including a central core of electrically conductive material, encircled by an annulus of electrically insulating material, is inserted into the hole.

Abstract: An encapsulated electrically and thermally enhanced integrated circuit is disclosed. An integrated-circuit die is attached to a thermally conductive, electrically-insulated substrate. A lead frame having inwardly-extending bonding fingers has the bottom sides thereof attached to the top of the substrate. A contiguous layer of insulating material is bonded to the top sides of the bonding fingers, such that the layer of insulating material peripherally surrounds the integrated-circuit die. A conductive layer of material is then bonded to the top of the insulating layer. A second layer of insulating material followed by a second conductive layer may be bonded on top of the first conductive layer. Electrical connections are made from the integrated-circuit die to the conductive layers surrounding the die. The device is then encapsulated in a plastic material.

Abstract: A multilayer interconnection substrate having, e.g., first to third power interconnections provided with first to third interconnection layers. A first insulating layer is provided between the first and second interconnection layers, and a second insulating layer is provided between the second and third interconnection layers. A plurality of first via holes are provided at said first insulating layer and connect the first and second power interconnections and a plurality of second via holes are provided at said second insulating layer with their position being shifted from that of the first via holes and connect the second and third power interconnection.

Abstract: The main system printed circuit board of a computer is mounted on a tray structure that also supports other CPU components of the computer and is removably insertable into the housing portion of the computer. A specially designed card edge connector portion of the system board is operatively insertable into a socketed connector on another circuit board interiorly mounted within the housing. Electrically conductive signal fingers and grounding fingers are respectively mounted on first and second sides of the card edge, with the signal fingers being connected to the signal plane of the system board, and the grounding fingers being connected to its ground plane.

Abstract: A method for forming electrical interconnections in vias is provided by laser drilling vias in a composite that contains at least two circuitized organic polymeric substrates superimposed upon each other. The laser drilling causes metallic circuit lines contained within each substrate to melt and form a fused mass protruding a short distance out of the side of the drilled vias. Next, the drilled vias are plated with a conductive metal to thereby provide the interconnections.

Abstract: A hermetic package particularly adapted for high density interconnect (HDI) electronic systems employs a ceramic substrate which serves as a base for the hermetic package. The substrate comprises a cofired body including buried conductors which provide electrical continuity between a set of inner contact points and a set of outer contact points bridging a seal ring that comprises either a solder seal or a weldable seal for the hermetic package lid. The outer contact points may be directly connected to a leadframe. The leadframe leads, after severing, can be directly attached to a printed circuit board.

Abstract: An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.

Abstract: A backplane circuit board for connecting network signal lines, bus signal lines, and a number of circuit cards includes a first set of traces from a first network signal connector to connectors for the circuit cards, and a second set of traces from a bus signal connector to the connectors for the circuit cards. The first set of traces and the second set of traces are separated by a uniform distance to provide electrical isolation from one another. The traces are made up of signal-active lines surrounded by signal-neutral lines for further electrical isolation. As one other mechanism for signal isolation, the backplane provides signal-neutral lines on a separate layer from, and in superposition to, the signal-active lines.

Abstract: A circuit assembly (400) includes a flexible circuit (402) having first (504) and second layers (502). A current-limiting device such as a nichrome strip (316) is coupled to the flexible circuit (402) for limiting the amount of current during a short circuit condition. A heat sink (404) is selectively placed between the first and second layers of the flexible circuit in thermal proximity to the nichrome wire (316) in order to dissipate some of the heat generated by the nichrome strip (316).

Abstract: A controlled impedance power and distribution network wherein -x- and -y- direction planes of interpositioned power and signal conductors with a dielectric layer between planes and separating each plane from a ground plane are assembled. The network provides the ability to distribute many power levels with all power and signal conductors electrically referenced to ground along their length and each signal conductor also electrically referenced to its respective power level along its length. The network is of particular advantage in the TFM technology in distributing multiple power levels with fewer layers.

Abstract: A ceramic multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer; a semiconductor module having a high reliability in its solder joint part comprising said ceramic multilayer circuit board mounted with a ceramic carrier substrate being mounted with a semiconductor device, said board being able to use a silver or copper conductor having a good electro-conductivity; and an amorphous glass powder for said ceramic multilayer circuit board.

Abstract: A multilayer printed wiring board is presented for surface mounting or through hole technology, which includes one or more layers of a high capacitance flexible dielectric sheet material. The dielectric sheet is comprised of a monolayer of multilayer or single layer high dielectric constant (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The board of the present invention alleviates the need for decoupling capacitors, thus resulting in significant, space savings on the board surface.