Abstract: A compact thick film substrate for filtering, shielding, and routing multiple lines of dc and control signals between isolated ports of a microwave integrated circuit. The substrate circuit includes a dielectric substrate having upper and lower substrate surfaces and first and second side surfaces. A first ground plane layer is formed on the upper substrate surface.

Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

Abstract: A millimeter wave multilayer phased array assembly has a multilayer board consisting of several laminated printed wiring boards (PWBs) and a frame having a waveguide input and waveguide output. The PWBs are made of a high frequency laminate material and have a pattern of metalization to perform varying electronic tasks. These tasks include electrical interconnection, RF signal transmission, DC current routing and DC signal routing.

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core.

Abstract: A packaging substrate is provided such that an electronic components having a plurality of connecting terminals at their side edge portions and other kind of electronic component are mounted in high density on the substrate. More specifically, in a packaging substrate having IC packages (electronic components) surface mounted on the substrate, the package body of each IC package having a plurality of outwardly extending lead terminals at their side edge portions, the package body of the IC package includes at its side edge portion a specified length open region with no connecting terminal disposed therein. The IC packages are arranged in such a way that open regions of adjacent IC packages are positioned so as to confront each other and that front ends of individual leads are kept in closely spaced relation within a specified spacing range, a bypass capacitor (other kind of electronic component) being surface mounted between the open regions of the adjacent IC packages.

Abstract: A multi-layer circuit substrate having an integral bus portion includes a dielectric substrate having a first device signal layer formed on a first side thereof and a second device signal layer formed on a second side thereof. The first and second device signal layers are each patterned to include at least one bus reference plane. A device reference plane layer is disposed between the first and second device signal layers in the dielectric substrate. The device reference plane layer is patterned to include a plurality of guard bands and a bus signal trace between at least two of the guard bands.

Abstract: A printed circuit board having a signal plane with increased channel width for enhanced wireability. The printed circuit board has a top plane having component lands arranged in a grid, wherein the component lands include a first grouping arranged in a first diagonal, and a second grouping arranged in a second diagonal where the second diagonal is parallel and adjacent to the first diagonal, a plurality of offset lands placed within the first diagonal between the component lands therein, and a plurality of electrical connectors electrically coupling component lands in the second diagonal to adjacent offset lands in the first diagonal.

Abstract: A structure for reducing cross-talk in VLSI circuits is disclosed. By filling voltage and ground metal lines in free or unused channels of VLSI chips and connecting them efficiently to the regular power image of the chip, the line to line coupling through vertical layers is reduced almost to zero and in-layer line to line coupling is also drastically reduced.

Abstract: A computer system includes a microprocessor, an an input coupled to provide signal inputs to the microprocessor, a mass storage coupled to the microprocessor, a video controller for coupling the microprocessor to a display, a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, and a multilayer printed circuit board for mounting the microprocessor thereon. The multilayer printed circuit board provides for reduced electromagnetic interference (EMI) and includes at least two layers. The multilayer printed circuit board further includes a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein. The second layer is disposed laterally from and substantially parallel to the first layer.

Abstract: Electrical resonances are reduced and noise propagation is attenuated in a multi-layer construction using planar power and ground planar conductors separated by insulating material by loading the power and ground planar conductors with a sufficient amount of capacitance, or series capacitance and resistance, at specific locations so that the planar conductors are electrically broken up into smaller sections which resonate at frequencies above the signal bandwidth. The propagation of injected noise is suppressed by the low-pass filter effect of the capacitive loading at the discrete locations. In accordance with one embodiment of the invention, islands of material with a dielectric constant higher than the dielectric constant of the overall insulator are placed at regular intervals where the capacitance of each high dielectric constant island is comparable to, or higher than, the capacitance of the “low” dielectric material which comprises the remainder of the insulating material.

Abstract: A low temperature co-fired ceramic assembly (LTCC) with a constraining core to minimize shrinkage of outer ceramic layers during firing. The outer ceramic layers have high density circuit features. A ceramic core includes several ceramic layers. Several via holes are located in the first and second ceramic layers. Several low density circuit features are located on the ceramic layers that make up the core. Outer ceramic layers are placed top and bottom of the ceramic core. The outer ceramic layers have via holes and high density circuit features. The circuit features patterned on the ceramic layers include resistors, capacitors, circuit lines, vias, inductors, or bond pads. The ceramic core is fired first in a furnace. The outer layers are then laminated to the ceramic core and fired. The ceramic core controls the shrinkage rate of the outer ceramic layers during firing allowing higher density circuit features on the outer layers.

Abstract: A printed circuit board is disclosed. A top layer power supply pattern and a top layer ground pattern are formed. The top layer power supply pattern and the top layer ground pattern are connected to a power supply layer and a ground layer through a plurality of viaholes, respectively. A plurality of capacitors or a plurality of capacitor resistor series circuits are disposed at predetermined intervals between the top layer power supply pattern and the top layer ground pattern.

Abstract: Disclosed is a multilayer (e.g., 4-layer) printed circuit board and method of manufacture thereof. The multilayer printed circuit board has at least one inner substrate (inner core) that includes a phenolic resin (e.g., a phenolic resin-laminated paper). Outer insulating layers of the multilayer printed circuit board can have a low dielectric constant (e.g., 3.8-4.4) and a high Tg (e.g., 180°-200° C.). The multilayer printed circuit board can be provided by steps including forming electrical circuit patterns from a copper foil on the inner substrate, to form a printed circuit board, forming a stack of at least one printed circuit board and outer copper foil layers, with insulating layers of, e.g., a semi-cured resin (e.g., prepreg layers) interposed between adjacent conductive metal layers, and then laminating the stack.

Abstract: In a multilayer printed circuit board having at least two conductive layers, including a power-supply layer with a plurality of power-supply planes having different supply voltages and a ground layer, a circuit pattern for transmitting a signal serving as a radiation noise source is formed on a conductive layer facing the ground layer in order to suppress generation of radiation noise.

Abstract: In a multi-layer printed-wiring board (100) the ground and power conductor-bearing layers (102 and 103) are placed immediately (without intermediancy of other conductive layers) below the outer surface conductor-bearing layers (101) and are connected to the outer surface layers by micro-vias (110 and 111) that do not extend beyond the ground and power layers, whereby the micro-vias avoid causing trace-routing blockages on lower, signal-routing, layers (104). The surface layers define traces for static and infrequently-changing signals. One or both of the ground and power layers define double pads (203) each comprising a pair of normal pads (204-205) interconnected by a short trace (206). One single pad of each pair is connected by a micro-via to a corresponding pad (202) on an outer surface layer, which also typically has a lead (201) of a component (200) soldered thereto or serves as a testpad.

Abstract: First to fourth power wiring conductors and first to fourth ground wiring conductors are arranged on first to fourth insulating layers, respectively, and a first signal wiring conductor is arranged on the first or second insulating layer and a second signal wiring conductor is arranged on the third or fourth insulating layer.

Abstract: A printed wiring board device used for electronic equipment, such as the information equipment, etc. A printed wiring board (10) has a power source layer (11) and a ground layer (12) and is mounted with active elements (3 and 4), such as digital ICs, etc. A first capacitor (1) which conductively couples the layers (11 and 12) with each other at a high frequency is provided in the peripheral section of one end side or the other end side of the section of the board (10) where the layers (11 and 12) are faced to each other. Second capacitors (2) which respectively supply transient currents to the active elements (3 and 4) are provided between the power supply pins (3V and 4V) of the elements (3 and 4) and the ground layer (12) near the elements (3 and 4). Therefore, the electromagnetic radiation caused by the power source layer (11) and the ground layer (12) of the printed wiring board (10) can be suppressed easily and remarkably.

Abstract: A multichip module includes an interposer formed from a semiconductor material and having a plurality of interconnections formed on a surface of the interposer. A plurality of integrated circuits is mounted on the interposer and is electrically coupled to the interconnections. One or more repeater circuits are disposed along a length of at least one of the plurality of interconnections. A lid seals the plurality of integrated circuits from environmental insults. As a result, RC transmission line effects and crosstalk effects are reduced for signals propagating from one of the integrated circuits to another across the surface of the interposer. Additionally, thermal coefficient of expansion mismatch is reduced or eliminated between the integrated circuits and interposer.

Abstract: A semiconductor device package is presented for housing an integrated circuit which includes bonding fingers located within a conductive ring structure and routed to device terminals on an underside surface of the semiconductor device package. The semiconductor device package includes a die area defined upon a planar upper surface, a conductive ring surrounding the die area, and a first set of bonding fingers arranged within the conductive ring. The die area is dimensioned to receive the integrated circuit. The conductive ring may be a power ring or a ground ring. The conductive ring and the first set of bonding fingers are located within a first signal layer adjacent to the upper surface. A set of bonding pads which serve as device terminals reside within a second signal layer adjacent to a planar underside surface.

Abstract: An interconnection circuit includes a plated through hole having a plurality of electrically isolated segments with at least one of the plurality of electrically isolated segments coupled to a signal path and at least one of the electrically isolated segments coupled to ground. With this arrangement, the circuit provides a signal path between a first and a second different layers of a multilayer. By providing one segment as a signal segment and another segment as a ground segment the size and shape of the electrically isolated segments can be selected to provide the interconnection circuit having a predetermined impedance characteristic. The interconnection circuit can thus be impedance matched to circuit board circuits, devices and transmission lines, such as striplines, microstrips and co-planar waveguides. This results in an interconnection circuit which maintains the integrity of relatively high-frequency signals propagating through the interconnection circuit from the first layer to the second layer.

Abstract: A printed circuit board (PCB) assembly includes a PCB having and a ferrite attenuator. The PCB includes input/output signal paths for carrying signals to and from the PCB, power paths for conducting power to the PCB, and ground paths for connecting the PCB to a ground level. The ferrite attenuator surrounds the input/output signal paths, the power paths, and the ground paths. The PCB assembly is preferably used in a system, such as a computer system, where the ferrite attenuator suppresses electromagnetic interference (EMI) generated in the system.

Abstract: Connecting pads in pad rows in a signal layer are connected to another signal layer through a plurality of through hole rows each including a plurality of plated through holes that extend through a power source layer. Each of the through hole rows includes a plurality of through holes arranged side by side between each two adjacent pad rows corresponding thereto. These plated through holes each face the space between each two adjacent connecting pads in each corresponding pad row, and are arranged at intervals about twice as long as the intervals between the connecting pads. Each two adjacent through hole rows are located with an offset not smaller than the diameter of each pad in the longitudinal direction of the rows, and the power source layer includes a plurality of clear regions that are cleared of a conductor and penetrated individually by the through holes.

Abstract: A universal multi-chip interconnect system using a set of at least two types of standardized interconnect components is disclosed. One of the component types comprises a chip carrier capable of holding at least one IC chip in a first portion thereof and providing a plurality of standardized interconnections from the first portion to one or more second portions of the carrier, where one or more interconnect components of a different type may be connected. Another of the component types comprises a bridge connector which is capable of connecting to two or more chip carriers at their second portions. Each bridge connector has at least two interconnect portions which are capable of connecting to chip carriers at their second portions, and a standardized pattern of interconnect wires between the interconnect portions.

Abstract: An article comprising a molded circuit for providing a path for electrical current is disclosed. The molded circuit is formed of a first material layer and a second material layer. The first material layer is an electrically insulating material. The second material layer is an electrically conductive material. In an alternate embodiment, the second material layer is surrounded between two layers of the first material layer. The molded circuit can be formed using multi-material injection molding such as co-injection molding or two-shot injection molding. A printed circuit board can comprise the molded circuit.

Abstract: The radio frequency module of the present invention includes an insulating substrate having a first metal film on a first principal surface thereof and a second metal film on a second principal surface thereof opposed to the first principal surface and a semiconductor device. The semiconductor device is thermally and electrically coupled to the second metal film, and a thickness of the second metal film is larger than that of the first metal film.

Abstract: An electronic system contains a backplane circuit card which supplies power to various modules. Embedded power distribution planes each include one or more islands, each island being associated with a respective module. The island is electrically isolated from the body of the power plane except at a relatively small area, called the power ramp. The electronic current path from the power plane to the module goes through the power ramp and the island. Preferably, a pair of adjacent power planes at +48 VDC and 0 VDC are in the middle layers of the backplane with a ground plane on either side. Signal planes carrying circuit patterns for multiple data signals are deposited as additional layers on either side of the ground planes. The pair of power planes are nearly identical patterns, the differences being the location of power connections for the modules. In particular, the islands and power ramps are located in the same places on each power plane.

Abstract: A laminated multi-layer printed board having at least a power source circuit layer, at least a ground layer and at least a signal layer includes a hole which extends through the board to the power source circuit layer. An inductor is provided in the hole.

Abstract: The present invention is a multi-level printed circuit board (PCB) containing at least one power plane for conducting and distributing electrical power and at least one ground plane, spaced apart from the power plane, for providing and distributing an electrical ground. At least one integrated circuit chip is mounted on the printed circuit board. At least one signal plane is spaced apart from both the power plane and the ground plane, for conducting and distributing electrical signals from a first point to a second point. The signal plane(s) each have a portion or "patch" that is electrically isolated from signal traces in the remainder of the signal plane. The patches are placed in the area underneath the integrated circuit chip. The patches are connected, respectively, to the power plane or to the ground plane, for reducing effective inductance and input impedance. The multi-level PCB has one or more plated through hole vias for connecting the power or ground plane to a patch.

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is a dielectric film with patterned metal on both sides. The two metal layers are interconnected by a through via or post process. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides connected by a through via or post process. The upper power/ground wrap substrate, signal core, and lower power/ground substrate are interconnected as desired using z-connection technology (e.g., solder or conductive ink).

Abstract: There is provided a multi-layered printed wiring board including a power supply layer, a ground layer, a signal layer, and insulators sandwiched between those layers. The power supply layer is provided with a circuit in the form of wirings for imparting impedance thereto. For instance, the power supply layer may be formed to include main wirings for distributing a dc current entirely to the printed wiring board with a dc voltage drop being depressed, and branch wirings for enhancing high frequency impedance to isolate circuits in terms of high frequency, which circuits are mounted on the multi-layered printed wiring board and operated independently with each other. The invention makes it possible to provide a relatively great inductance to thereby decrease high frequency power supply current which is generated on IC/LSI operation and is to flow into decoupling capacitors.

Abstract: An inventive printed circuit board for chip-on-board applications has a ground plane that is externally exposed through apertures in any overlying layers in the board so the backside surface of a bare integrated circuit die can be directly attached to the ground plane using a silver-filled epoxy. As a result, heat is conducted away from the die through the ground plane. Also, a substrate bias voltage can be supplied to the backside surface of the die through the ground plane to eliminate the need for an internal substrate bias to the die, and to eliminate the need for a substrate bias voltage bond pad on the front-side surface of the die.

Abstract: Disclosed is a printed circuit board that includes selectable structures for attenuating EMI/RFI of replaceable components. In one preferred embodiment, the printed circuit board has a power plane that is subdivided into a plurality of power islands, a ground plane, a plurality of bypass capacitors, and a connector mounted on the printed circuit board for receiving electrical components. Each bypass capacitor is connected between the ground plane and an associated one of the power islands. The connector is connected to at least two selected power island, and the selected power islands are arranged such that when a first electrical component is inserted into the connector, a first one of the selected power islands is automatically connected to a power supply pin of the first electrical component to facilitate attenuation of electromagnetic interference generated by the first electrical component in a first frequency band.

Abstract: A circuit board including a general-purpose region for mounting a general-purpose electrical part, and a programmable region for mounting a programmable digital electrical part, the general-purpose region and the programmable region being provided on the same board. The circuit board may comprise at least four layers of a first wiring pattern layer, a second wiring pattern layer, a power source layer provided between the first and second wiring pattern layers, and a ground layer provided between the first and second wiring pattern layer.

Abstract: A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is formed over the exposed side surfaces of the mesas and the exposed surfaces of the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material.

Abstract: A method for producing a layer of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of selecting a core material from one of three iron/nickel alloys, namely either (i) 58% Fe/ 42% Ni; (ii) 60% Fe/39% Ni/1% Cu; or (iii) 60% Fe/38.7% Ni/.12% Mn/.07% Si; forming the core material into a panel suitable for an intended application; cleaning the panel in preparation for plating; plating the panel with copper; subjecting the plated panel to heat treatment; and circuitizing the panel as appropriate for the intended application.

Abstract: A modular high-frequency oscillator structure utilizes a master circuit board to form a plurality of oscillator units. The master circuit board has an upper, middle and lower copper foil layer. The upper copper foil layer has a plurality of component circuit patterns and a plurality of positive voltage, ground and signal regulation circuit patterns. The middle copper foil layer has a plurality of power transfer and ground transfer circuit patterns. The lower copper foil layer has a large common ground circuit pattern. The master circuit board is etched in such a manner that the upper and lower copper foil layers are cut through to isolate each oscillator unit and the middle copper foil layer remains uncut.

Abstract: A power supply integrated module includes a metal substrate having a surface and a body of a dielectric material, such as a glass or ceramic, mounted on and bonded to the surface of the substrate. The body is formed of a plurality of layers of the dielectric material bonded together. Areas of a conductive material and a resistive material are coated on the surfaces of the layers of the body to form passive electronic components, such as capacitors, resistors and inductors. At least one transformer is on or in the body. The transformer and passive electronic components are electrically connected by conductive interconnects on the layers of the body and vias of a conductive material extending through the layers of the body to form a power supply integrated circuit. Active electronic components, such as diodes and transistors, may also be mounted on the body and electrically connected in the power supply circuit.

Abstract: There is provided a printed circuit board including (a) at least one dielectric layer, (b) at least two metal layers one of which acts as a ground layer, another one of which acts as a power-supplying layer, and the others of which, if any, act as a wiring layer in which a signal pattern is formed, the dielectric layer and the metal layers being alternately formed one on another, and (c) at least one resistor disposed at a marginal end of the printed circuit board between the ground layer and the power-supplying layer, the resistor having a function of disallowing current communication between the ground layer and the power-supplying layer. The above-mentioned printed circuit board prevents fluctuation in a voltage between ground and a power-supply, and further prevents unintentional electromagnetic interference and circuit malfunction caused by invasion of external electromagnetic field thereinto.

Abstract: In the case of a card cage for an electronic control unit having signal-processing analog and/or digital components, high-speed digital components, as well as components having both signal-processing functional parts, as well as high-speed digital functional parts and power components, which are arranged on a multilayer printed-circuit board and are electroconductively connected to a shared ground plane, the signal-processing components of each module having a shared connection to the common ground plane, the radiated interference from the control unit produced by high-frequency interference currents can be reduced, and high current densities in the ground plane and resultant potential shifts can be prevented from adversely affecting the signal processing, in that the signal-processing components are combined into signal-processing modules having at least one shared function, and the ground connections of all components of such a functional module are routed in each case via conductor connections to a common

Abstract: A computer system includes a multi-layer circuit board having first and second routing layers. A component including pads is mounted on the first layer. Crosstalk protection is provided by a plurality of ground vias and signal vias adjacent to the component and extending between the first and second layers. A first circuit trace extends from a first pad along the first layer and between two adjacent ones of the ground vias. A second circuit trace extends from a second pad along the first layer to a signal via at the first layer and from the signal via along the second layer between the two adjacent ground vias.

Abstract: This invention is directed to a PCMCIA Type II memory card holder assembly for a spread spectrum radio communication card that provides radio frequency interference shielding, electrostatic discharge resistance and heat dissipation. The card holder assembly consists of a multilayer circuit board and a card holder. The multilayer circuit board has a ground plane disposed between a plurality of analog circuit layers and a plurality of digital circuit layers. The ground plane is connected by through vias to ground traces on the surfaces of the circuit board. The card holder consists of a card holder frame in which the memory card is slidably and rotatably mounted so that the ground traces continuously contact the frame, and two outer cover plates which are adhered to the opposing surfaces of the card holder frame.

Abstract: A multilayer printed board has at least a signal layer, a power source layer, and a ground layer that are formed one upon another with insulation material being interposed among the layers. The board is capable of reducing radio waves to be emitted from the board.The board is provided with capacitors that are continuously or discretely formed at the edges of an overlapping pattern of the power source layer and ground layer, to pass a high-frequency current from the power source layer to the ground layer, thereby reducing the emission of radio waves.

Abstract: A semiconductor device has an electrical circuit and a grounding terminal. A multilayer substrate has a plurality of insulator layers and conductor layers in a stacked arrangement and a surface with first and second regions, the conductor layers making electrical contact with the electrical circuit and the grounding terminal of the semiconductor device. The first region generally surrounds the semiconductor device and has first connecting conductors penetrating at least a part of the multilayer substrate so that each of the first conductors makes contact with one or a plurality of corresponding conductor layers. The second region generally surrounds the first region and has second connecting conductors penetrating at least a part of the multilayer substrate and only making contact with one or a plurality of conductor layers coupled to the grounding terminal of the semiconductor device.

Abstract: Electrical potentials and very high frequency (VHF) currents in a circuit board are controlled by patterning the power plane of a multiple layered, capacitive plane printed circuit board in selected geometric patterns. The selected geometric patterns, both simple and complex, control voltages and currents by channeling the capacitance capacity for usage directed to a particular integrated circuit or circuits, isolated to a particular integrated circuit or circuits, or shared between integrated circuits. Accordingly, the capacitive planes including the geometrically patterned power plane are channeled capacitive planes (CCP) that are formed on multiple layers of a single printed circuit board to support flexible, three-dimensional control of VHF electrical currents.

Abstract: A printed circuit board including a terminated power plane is described. Specifically, the power-ground plane construction includes a dielectric layer, a power plane having a peripheral edge, and a ground plane. The ground plane is spaced from the power plane by the dielectric layer, and is positioned in an opposed relationship to the power plane. The power-ground plane construction also includes a termination element coupling the power plane, at or adjacent the peripheral edge thereof, to the ground plane so as to terminate the power plane. In one embodiment, a plurality of termination elements couple the power plane, at or adjacent the peripheral edge thereof, to the ground plane. The termination elements are spaced from each other at substantially regular intervals. In another embodiment, a termination element is a strip or sheet element coupling continuous lengths of the peripheral edge of the power plane to ground plane.

Abstract: A stackable data carrier arrangement including a cardshaped carrier element, at least one integrated semiconductor circuit arranged on the carrier element, at least one external terminal arranged on the carrier element and connected to the semiconductor circuit for making electrical contact therewith, the external terminal being formed so as to circumscribe an edge area of the carrier element and having a respective terminal area on the edge area and adjoining opposite main areas of the carrier element, the terminal areas being electrically connected to one another, includes means defining two slots provided in the carrier element, the slots extending parallel to one another from the edge area into the carrier element to approximately the same extent as the external terminal arranged between the slots, so that a contact tooth bendable perpendicularly to the main areas of the carrier element is formed by the region of the carrier element situated between the slots.

Abstract: A circuit arrangement (4) for the operation of electrical lamps, with a printed circuit board (5), on which electrical components (14) and conductor strips (7; 19; 20) are arranged, whereby potential changes that are rapid over time occur on printed circuit board (5), has an equipotential surface (6) for reducing the radio interference caused by these potential changes. For this purpose, equipotential surface (6) with resting potential relative to the rapid potential changes is connected onto printed circuit board (5). In particular, the equipotential surface is produced by a copper layer (6) on the upper side of printed circuit board (5). The advantage is a simple-to-produce arrangement that can be automated for reducing radio interference.

Abstract: A leadless ceramic chip carrier useful in surface mounting of SAW devices includes electrically conductive vias and metalization between input and output bond pads for improved crosstalk suppression between input and output device connections. A protrusion extending from a top layer of a multilayer ceramic carrier provides additional electrical contact to a package seal brazed thereto. The vias are positioned between input and output bond pads and connect the metalized protrusion to package ground pads through contact with multiple metalized layers of the package for enhancing the electrical connection between the package Kovar seal ring and customer accessed ground pads. For further suppression of crosstalk, bond pads within the package for connection to the SAW device are spaced at a greater distance from each other than their corresponding pads on the package bottom surface thus maintaining an optimum spacing for package connection to printed circuit board pads for minimizing thermal mismatch effects.

Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.

Abstract: In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.