Abstract: A method and structure for routing electrically conductive interconnect paths through a printed circuit board. The printed circuit board includes a plurality of insulating layers and conductive layers, including at least one electrically conductive voltage supply layer for receiving a first supply voltage. A plurality of voltage supply pad patterns are located at the upper surface of the printed circuit board. Each voltage supply pad pattern includes two or more electrically conductive pads which are coupled by one or more electrically conductive traces. Electrically conductive via plugs extend through the printed circuit board to connect the voltage supply layer to the voltage supply pad patterns. Each via plug is connected to one corresponding voltage supply pad pattern, thereby allowing each via plug to provide the first supply voltage to a plurality of pads at the upper surface of the printed circuit board.

Abstract: In semiconductor modules having a plurality of semiconductor devices mounted on a multilayer printed circuit boards as the processing speed increases, a short circuit current flowing through CMOS devices in the semiconductor devices during operation can cause noise because of ground inductance or power supply inductance. This noise can result in erroneous operations. To solve this problem, the power supply layer or grand layer that is connected to either the power supply terminal Vcc or the ground terminal Gnd of each semiconductor memory, which is located farther from the connection terminals, is arranged closer to the semiconductor memories with this arrangement, the short circuit current flowing through the semiconductor memories is more strongly magnetically coupled with the power supply layer or ground layer arranged close to them. Thus, it is possible to reduce the effective inductance. This, in turn, reduces noise, making it possible to provide a semiconductor module with an increased processing speed.

Abstract: A multilayer printed-circuit board includes at least one inner-layer signal line, first and second ground layers between which the inner-layer signal line is sandwiched via a frame member made of an insulating material in a thickness direction of the multilayer printed-circuit board, and metallic wall members which are provided on inner walls of slits formed in the frame member and extending along the inner-layer signal line. The first and second ground layers and the metallic wall members shielding the inner-layer signal line.

Abstract: An electronic relay including current sensors (11, 12, 13) mounted, between terminals (L1, T1, L2, T2, L31, T3), in series on alternating current power supply lines to a load (M). A back of a case (1) of the electronic relay includes a power card (C1) linked to the current sensors (11, 12, 13) and connected via connectors to electronic daughter cards (C2, C3, C4) carrying lateral terminal blocks (B1 and B2) which have outputs in the lateral openings of the case. A front of the case (1) includes a dialogue and communication card (C5) connected to at least one of the daughter cards (C3).

Abstract: Arrangement for the protection of electrical and electronic components against electrostatic discharge, where a printed circuit board on which the components are mounted is physically connected to a metal plate via an insulating layer with the insulating layer having at least one conductor track of the printed circuit board opening over which at least one track is placed to form a first spark gap between the track and the metal plate and with the metal plate being connected to a fixed potential.

Abstract: The invention relates to a coupling device presenting a capacitance belonging to a board with a printed circuit, where said board (1) consists of several electrically conducting layers (50e, 50g) with electrically isolating layers in between (50eg). A surface extension of a reference potential related layer (50e), an opposite surface extension of a supply voltage related layer (50g) and a chosen distance in between said layers are adapted to form a capacitor function to smooth voltage spikes so that the DC-supply voltage can be constant around circuits (2) mounted on said board even at rapid current variations as said circuits and/or components are activated.

Abstract: A multilayer module for packaging at least one electronic component 50. The module includes a plurality of thickfilm layers, and a wiring structure 45 to permit the connection of on-module capacitors. The multilayer module is fabricated such that the wiring structure includes a partial mesh plane 46, 47, 48, and 49 between the topmost and second topmost layers of the thickfilm. Logic noise is reduced in the multilayer module by maximizing the mutual inductance between adjacent mesh planes.

Abstract: In a printed circuit board on which a plurality of electronic components are mounted, a first electronic component having the largest number of input and output pins among the electronic components is arranged at or near the center of the printed circuit board. Wiring patterns including a signal line pattern, a first power supply pattern, and a first ground pattern almost radially arranged from the first electronic component, thereby mounting the electronic components at a high density with a high wiring efficiency.

Abstract: The signal connecting through vias are provided on an edge side of a multilayer printed circuit board along a longitudinal direction thereof, and the signal wiring of the respective layers of the signal wiring layer is inclined with respected to the arrangement of the through vias.

Abstract: A multi-layer circuit board (11) has a cofired ceramic with a configuration of circuit traces (27) extending though differing layers of the multi-layer circuit board (11) to facilitate mountable conductive contact with semiconductor flip chips (13). Via holes (23) are precisely formed in the multi-layer circuit board (11) and are filled with solder or conductive epoxy. Semiconductor chips (13) have an array of metallic posts (19) alignable with the holes (23) and are mounted upon the upper surface of the multi-layer circuit board (11) in plug fashion. An aperture (25) may be formed in multi-layer circuit board (11) directly below each semiconductor chip (13) for protection of the circuitry on semiconductor chip (13) from contact with multi-layer circuit board (11). The via holes (23) and transmission line structure of the circuit board (11) are precisely formed to achieve a desired characteristic impedance.

Abstract: A power distribution system for a multi-layer circuit board includes a board having a component layer with signal runs formed thereon, a ground layer, an insulation layer, and a power supply system. The power supply system includes a supply bus, discrete voltage supply planes, and isolation devices mounted on the component layer, each connecting one of the discrete voltage supply planes to the supply bus. The component layer has a first area for components which perform a first function and a second area for components which perform a second function. The discrete voltage supply planes include a first supply plane corresponding to the first area and a second supply plane corresponding to the second area. The first supply plane is disposed directly beneath and is shaped substantially the same as the first area, and the second supply plane is disposed directly beneath and is shaped substantially the same as the second area.

Abstract: An integrated circuit chip package having an electrical contact configurable for either signal or power/ground and a method for constructing the integrated circuit chip package are disclosed. The integrated circuit chip package includes a substrate for supporting an integrated circuit chip and a dedicated conductor for supplying voltage to the integrated circuit chip. A configurable contact is attached to a surface of the substrate. The integrated circuit chip package further includes a signal connection for electrically connecting a signal connector of an integrated circuit chip and the configurable contact. A removable connector electrically connects the configurable contact and the dedicated conductor, thereby enabling the configurable contact to be configured as either a signal or power/ground contact depending upon the absence or presence of the electrical connection between the configurable contact and the dedicated conductor provided by the removable connector.

Abstract: A power distribution system for a multi-layer circuit board includes a board having a component layer with signal runs formed thereon, a ground layer, an insulation layer, and a power supply system. The power supply system includes a supply bus, discrete voltage supply planes, and isolation devices mounted on the component layer, each connecting one of the discrete voltage supply planes to the supply bus. The component layer has a first area for components which perform a first function and a second area for components which perform a second function. The discrete voltage supply planes include a first supply plane corresponding to the first area and a second supply plane corresponding to the second area. The first supply plane is disposed directly beneath and is shaped substantially the same as the first area, and the second supply plane is disposed directly beneath and is shaped substantially the same as the second area.

Abstract: Disclosed is a backplane assembly that includes stiffeners to provide both mechanical stiffening and electrical power distribution. In particular, the present invention provides a power distribution system that comprises a backplane, a power stiffener having alternate layers of dielectrics and conductors proximately located to the backplane, and removable connection to electrically connect the conductors in the stiffener to the backplane. Because power can be transferred directly to the backplane from the stiffener via the connection, the need for power cables and bus bars on the backplane is eliminated. In addition, noise suppressing capacitors may be located on the power stiffener, close to the load source.

Abstract: The present invention is a printed circuit board having conductive layers split into electrically isolated voltage supply plane regions each plane region being connectable to an external supply voltage. The voltage supply plane regions are split to reduce the total number of PCB conductive layers. Voltage supply plane regions are configured to match the device voltage requirements and their placement on the PCB. In the case in which a circuit includes a device having two voltage supply requirements, a first set of the device's power supply pins are fixedly coupled to a first voltage supply plane region and a second set of the device's power supply pins are fixedly coupled to a second voltage supply plane region. In this instance, each of the first and second voltage supply plane regions are fixedly connectable to external voltage supplies or to a voltage regulator according to the voltage supply requirements of the device.

Abstract: A high-density multilayer printed circuit board is provided such that crosstalk noise between through holes is avoided and wiring efficiency is increased. Power supply through holes which connect to power supply pins of component parts are combined to make room for via holes in certain portions of the multilayer printed circuit board. These power supply through holes are subsequently restored into their original form. This permits via holes to exist at certain locations so that certain wiring layers can be interconnected. Additionally, by restoring the power supply through holes, crosstalk noise is reduced as the rear side of the multilayer printed circuit board is approached. Finally, dummy power supply lines can be provided to further reduce crosstalk noise. These dummy power supply lines are not connected to power supply pins of the component parts.

Abstract: A printed board 10 is provided with two ground layers 3a, 3b. These ground layers 3a, 3b are electrically insulated inside the printed board. By connecting circuits with different characteristics (low frequency and high frequency, for example) with the different ground layers 3a, 3b, interference of these circuits caused due to a common ground can be minimized.

Abstract: In a data processing apparatus, communication apparatus or similar electronic apparatus, a laminate wiring board has a signal layer having a ground area and interposed between a signal layer and a power supply layer. Therefore, there is no need to provide a ground layer between the signal layer and the power supply layer. The wiring board can therefore be implemented with a small number of layers and is free from faults ascribable to extra layers.

Abstract: Within a power supply, the draw of power between redundant power sources are passively balanced. Within a power plane of the printed circuit board a first current distribution plane section is placed. First connector pins are used to electrically connect the first current distribution plane to the first power source. Second connector pins are used to electrically connect the first current distribution plane to the second power source. Moats are placed within the power plane of the printed circuit board so that within the first current distribution plane section a first current path from the first connector pins to a first central power distribution area is substantially symmetrical to a second current path from the second connector pins to the first central power distribution area. Output power current passes through the first central power distribution area.

Abstract: Two interdigitated comb-shaped fixed voltage buses such as a power bus and ground bus, in the form of metallization are provided substantially encircling of an integrated circuit die in an integrated circuit package or other integrated die assembly. Any selection of bonding pads on the die and metallization leads in the assembly may be connected to the fingers of either bus. The length of wire bond or TAB connections and the area occupied by the buses is minimized by the interdigitated geometry of the buses.

Abstract: An apparatus for improving the power dissipation of a semiconductor device surface mounted on a printed circuit board having at least a top printed circuit board layer and a bottom printed circuit board layer is provided. The apparatus includes a first pad of metallic material connected to a top surface of the top printed circuit board layer. The semiconductor device is connected to the first pad. A second pad of metallic material is connected a to the top surface of at least one of the top and bottom printed circuit board layers, wherein the second pad is electrically isolated from the semiconductor device. The apparatus also includes at least one thermal via for heat transfer through the printed circuit board layers thermally coupled to the thermal pad. A heat sink is thermally coupled to the at least one thermal via.

Abstract: A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package.

Abstract: Signal wiring layers are formed between a power supply layer and a ground layer, which have conductor patterns each constituted by a plurality of parallel strip-shaped conductors. The above layers are isolated from each other by insulating layers. The signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the power supply layer, and the signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the ground layer.

Abstract: An electronic circuit structure having a reduced size includes a circuit substrate, an aperture extending through the circuit substrate, and an electronic component suspended within the aperture. The suspension of the electronic component within the aperture significantly reduces the profile of the overall electronic circuit structure. The aperture further enables electronic components to be mounted in a partially overlapping fashion to reduce the surface area of the electronic circuit structure. The electronic circuit structure can make use of standard FR-4, G-10, or ceramic circuit substrates or multilayer flex circuits, as well as electronic components in the form of standard leaded integrated circuit packages. The mounting of the electronic component within the aperture of the circuit substrate provides an advantage of assisting in heat dissipation. The incorporation of mesh-like voltage and ground planes can further aid in heat dissipation and provide electrical isolation and capacitive filtering.

Abstract: A printed circuit board (PCB) capable of operating at first and second predetermined voltage levels including a plurality of metal layers, one of the metal layers being divided to provide two electrically isolated sections, the two electrically isolated sections being on substantially the same plane; one of the electrically isolated sections being associated with the first predetermined voltage level and the other of the electrically isolated sections being associated with the second predetermined voltage level. The PCB includes a first plurality of signal pins coupled to the one of the electrically isolated sections. The PCB also includes at least one capacitor coupled to a ground plane, the first plurality of signal pins and the one of the electrically isolated metal sections, wherein an alternating current path is provided. The PCB in a preferred embodiment is an expansion board utilized in a personal computer.

Abstract: The invention relates to a connecting rear wall (10) for subracks in electronic systems. Metal plates (14, 16) are mounted parallel to a wiring board (12) by being screwed thereto and simultaneously serve to feed the supply voltages and to screen high-frequency interferences. Cutouts (26) and openings (A) in the metal plates (14, 16) have a maximum dimension which does not exceed 1/10 to 1/20 of the wavelength of the interference signal of highest frequency which is to be screened.

Abstract: An improved symmetric circuit connection board may be utilized on both the driver and passenger sides of a vehicle or in left and right-hand orientations. In the past, two distinct boards have been provided for use on the driver and passenger sides. The inventive symmetric boards includes central circuit stampings surrounded by a molded body. Openings extend symmetrically, through the molded body to the circuit stampings such that the assembler may selectively place one opposed face of the board facing outwardly and connect the board as appropriate. Should the board be utilized on the other side of the vehicle, the opposed face of the board faces outwardly for connection. The symmetric board may thus be utilized for either left or right hand side applications in a vehicle.

Abstract: A multilayer thin-film wiring board formed by laminating at least three wiring layers including first, second, and third wiring layers together with a dielectric layer. The first wiring layer includes a first pattern having a plurality of first windows arranged with the same pitch both in a lateral direction and in a longitudinal direction of the wiring board, and a plurality of first island patterns each located at a substantially central portion of each first window. Similarly, the second wiring layer includes a second pattern having a plurality of second windows, and a plurality of second island patterns each located at a substantially central portion of each second window. The second windows are shifted from the first windows by half the pitch both in the lateral direction and in the longitudinal direction. The third wiring layer includes first and second via pads formed on a surface of the wiring board.

Abstract: A circuit board includes a circuit-conductor layer, a ground layer and a power source layer superposed in a multilayer form through dielectric layers therebetween. A heat conduction through inside of the circuit board is enhanced so that circuit chips mounted on the circuit board can be cooled down to a level capable of operating normally. The circuit board can be formed to be compact. In order to enhance the heat transfer in the circuit board, at least one of the ground layer and power source layer is formed in a multilayer manner. It is preferable to form these layers at a thickness larger than that of the circuit-conductor layer. Further, preferably, the pin of the chip mounted on the board and at least one of the ground layer and power supply layer are connected to each other in such a manner as to enhance the heat conduction.

Abstract: The present invention is a printed circuit board design having a configurable voltage supply and a method for implementing a configurable voltage supply PCB with a family of circuit designs. The printed circuit board is designed such that voltage supply planes can be configured to match the device requirements for different ICs inserted into the PCB. The PCB comprises electrically isolated conductive layers that are split into a plurality of electrically isolated fixed and undefined voltage planes. The fixed voltage planes are each coupled to a different supply voltage provided by an external power supply. Undefined voltage planes are coupled to fixed voltage planes with insertable conductive jumpers to obtain the desired voltage supply for each voltage plane. The voltage plane configuration of a particular PCB can be changed depending on where jumpers are inserted to accommodate device voltage requirements over a family of devices.

Abstract: According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening.

Abstract: A power/ground structure and associated circuit card or board are provided in which the coefficient of thermal expansion of the power/ground structure and associated circuit board are closely matched to each other. The circuit board or card is formed of organic electrically-insulating material having electrical circuitry thereon which carries an integrated circuit chip. The power/ground assembly is formed of alternating layers of organic insulating material and at least two layers of electrically-conducting material, typically copper, one of the layers of electrically-conducting material forming a power connection and another layer of the electrically-conducting material forming a ground plane. There is also at least one additional layer of a structural material having a relatively high Young's Modulus and a CTE of less than about 10 PPM/.degree.C. Invar or copper clad Invar are preferred materials for this structure.

Abstract: A memory IC having an SOJ type package is mounted on a metal wiring layer on the surface of the outer layer of a multilevel interconnection board. Protecting portions are formed on the package of the memory IC. The protecting portions contact the surface of the metal wiring layer when the memory IC is mounted on the multilevel level interconnection board. The shape of the projecting portions can be of various types, e.g., circular cylinders or prisms. Heat generated within the memory IC is transmitted to the metal wiring layer through the projecting portions. A first insulating layer has first and second surfaces. Wiring layers are formed on each of the first and second surfaces of the first insulating layer, and first and second semiconductor chips are connected to those wiring layers. First and second resin layers cover the whole surface of the outermost wiring layers and the first and second semiconductor chips.

Abstract: A PGA connector for a microprocessor has a multilayer base board assembly with alternating conductive and dielectric layers of preselected thicknesses through which signal pins, current source pins and a grounding pin extend. The signal pins are insulated from the conductive layers and the current and grounding pin are connected to preselected conductive layers. A series of connecting apertures formed by holes with respective conductive linings extend through the layers at selected locations between pins to interconnect selected conductive layers. The connecting apertures interconnect all conductive layers of the base board or, in another example, alternately positioned connecting apertures interconnect only respective different sets of alternately positioned conductive layers of the base board enabling improved shielding and impedance regulation and matching.

Abstract: A wiring substrate includes a ceramic substrate having a first conductive connection pattern on an lower surface of the ceramic substrate and a second conductive connection pattern on an upper surface or the lower surface of the ceramic substrate, a multilayered wiring portion arranged on the lower surface of the ceramic substrate through the first conductive connection pattern and including an insulating layer made of an organic polymer, on which an integrated circuit and/or a circuit part are/is mounted, and a flexible wiring substrate, connected to the second conductive connection pattern, for connecting the integrated circuit and/or the circuit part to an external circuit.

Abstract: An interface board for use, for example, in a motor vehicle to provide electrical interconnection between a plurality of electrical circuit control elements and a wiring harness. The board comprises a box structure including a plurality of circuit outlets on the upper face of the structure for plug in receipt of the electrical circuit control elements, a plurality of power outlets on a lower face of the structure for plug in receipt of electrical power input and output elements, and a series of electrical paths extending between the power outlets and a circuit control outlets. Each electrical path includes a first conductor extending generally parallel to the first and second faces and second conductors extending generally perpendicular to the first and second faces. The first conductors comprise flat ribbon elements and the second conductors comprise flat ribbon elements connected to the flat sides of the first conductors utilizing clinch joints.

Abstract: A substrate or a ceramic package for packaging semiconductor chips, which comprises an insulating layer having a signal line on one surface of said insulating layer and a power line or ground line corresponding to said signal line on the other surface of said insulating layer. A well-controlled constant high frequency characteristics, and particularly, characteristic impedance, can be obtained on the signal line without being influenced by the power line or ground line.

Abstract: This invention is directed to a PCMCIA Type II memory card holder assembly for a spread spectrum radio communication card that provides radio frequency interference shielding, electrostatic discharge resistance and heat dissipation. The card holder assembly consists of a multilayer circuit board and a card holder. The multilayer circuit board has a ground plane disposed between a plurality of analog circuit layers and a plurality of digital circuit layers. The ground plane is connected by through vias to ground traces on the surfaces of the circuit board. The card holder consists of a card holder frame in which the memory card is slidably and rotatably mounted so that the ground traces continuously contact the frame, and two outer cover plates which are adhered to the opposing surfaces of the card holder frame.

Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.

Abstract: An arrangement for a motor vehicle for central connection of electrical components, the arrangement comprises a housing, a plurality of supply circuits and control circuits, a plurality of circuit straps punched out of metal sheets and printed circuit boards, the supply circuits and the control circuits being formed so that the supply circuits are formed exclusively from the punched circuit straps and the control circuits are formed exclusively from the printed circuit boards, the printed circuit boards with the punched circuit straps and their intermediate insulations being assembled in a plurality of layers in a substantially identical surface configuration to form a printed circuit pack.

Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.

Abstract: A printed circuit board (PCB) capable of operating at first and second predetermined voltage levels including a plurality of metal layers, one of the metal layers being divided to provide two electrically isolated sections, the two electrically isolated sections being on substantially the same plane; one of the electrically isolated sections being associated with the first predetermined voltage level and the other of the electrically isolated sections being associated with the second predetermined voltage level. The PCB includes a first plurality of signal pins coupled to the one of the electrically isolated sections. The PCB also includes at least one capacitor coupled to a ground plane, the first plurality of signal pins and the one of the electrically isolated metal sections, wherein an alternating current path is provided. The PCB in a preferred embodiment is an expansion board utilized in a personal computer.

Abstract: A shielding method which utilizes a three dimensional structure and is effective to a source of the electromagnetic radiation noise, and a circuit board employing the same are obtained. Further, for the purpose of making the shielding function at an enclosure level unnecessary and realizing the recycling of enclosure materials by using this circuit board, in a circuit board structure having at least a signal layer, a power source layer and a ground layer, a signal line on the signal layer which is sandwiched between the two conductor layers made up of the power source layer and the ground layer, or the power source layers or the ground layers, is enclosed in a three dimensional manner with the conductor layers, thereby to form a single or double electrical closed loop current path or paths. By adopting this structure, there is obtained the effect that the electromagnetic radiation noise radiated from the circuit board is greatly reduced.

Abstract: A signal line network on a substrate for interconnecting IC chips is programmable after manufacture to define the desired connections. The signal lines comprise line segments arranged end-to-end in both horizontal and vertical directions and are connectible at their ends and the vertical and horizontal segments are connectible at their crossings. A dedicated contact pad is connected to each segment. A plurality of bonding pads are adjacent several segments and each pad has arms extending across the several segments and are individually connectible to them. All connectible junctions comprise amorphous silicon antifuses which are normally insulators and are selectively programmable after the substrate is manufactured by applying a voltage pulse across the antifuse to render it conductive. The pads are arranged in a pattern in cells, all cells having the same pad pattern to facilitate probe connections for programming and testing.

Abstract: A multi-layered printed circuit board is provided.

Abstract: A printed circuit board is shown to include at least one layer formed from electrically insulating material and a power plane formed on the layer. The outer perimeter of the power plane is spaced away from the outer edge of the layer thereby defining an outer area. A conductive structure is formed in the outer area, spaced from and surrounding the power plane and adapted to be connected to ground. Electromagnetic radiation emanating from the power plane is caused to terminate on the conductive structure. A multi-layered printed circuit board can also include a first layer of electrically insulating material, a ground plane formed on the first layer, a second layer of electrically insulating material and a power plane formed on the second layer. The outer perimeter of the power plane is spaced away from the outer edge of the second layer.

Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed. The interconnect board can have layers assigned to specific voltages, in a power-translation design.

Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.

Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.

Abstract: A power supply structure for a multichip package is provided to improve the transmission performance of signals. Cases are fitted onto one face of a ceramic substrate. On the other face are aligned substrates. On each of the substrates are erected I/O pins. The I/O pins are connected to signal pins of LSIs via the ceramic substrate's internal layer. On side faces of the substrates are provided power supply pads. To the power supply pads are connected the power supply pins of the LSIs via the ceramic substrate's internal layer. When power is to be supplied, electroconductive bars are inserted between the substrates. The electroconductive bars supply power to the LSIs via the power supply pads. A cable is connected to one of the I/O pins.