Abstract: A high-performance, integrated circuit interconnection laminate. Power/ground layers in laminates fabricated with open areas to permit out gassing of gases generated during high temperature lamination are located such that they do not lie under/over critical traces on signal layers. This placement of the open areas enables a reduction in cross-talk between signal layers lying on opposite sides of a power/ground layer and a reduction in signal delay.

Abstract: The invention encompasses an electrical apparatus. Such apparatus comprises a first substrate having first circuitry supported thereby. The first circuitry defines at least a portion of a radio frequency identification device. At least one first electrical node is supported by the substrate and in electrical connection with the first circuitry. The apparatus further comprises an input device comprising a second substrate and second circuitry on the second substrate. The second circuitry is in electrical communication with at least one second electrical node. Neither of the first nor second electrical nodes is a lead, and the second electrical node is adhered to the first electrical node to electrically connect the input device with the radio frequency identification device. The invention also encompasses a termite-sensing apparatus. Additionally, the invention encompasses methods of forming electrical apparatuses, and methods for sensing termites.

Abstract: Each wiring layer of a multilayered wiring substrate includes signal wirings disposed in parallel with one another, and dummy wirings disposed at each side parallel to the signal wirings of the signal wiring group made by signal wiring, respectively. The dummy wirings have the same shape as the signal wirings, and are disposed in parallel to the signal wirings at the same intervals as that in the signal wirings. Through holes are formed in the respective clearances among the signal wirings. Dummy through holes having the same shape as the through holes are formed between the dummy wiring and signal wiring. A conductive layer is formed on the inner wall of the through holes. The multilayered wiring substrate is able to reduce or eliminate the delay time difference between signals that propagate along the signal wirings.

Abstract: A method including routing a signal from a memory device on an integrated circuit in a package to a memory module, and returning the signal to a reference line in the package between the memory module and the integrated circuit. Also, a method including providing a memory module including at least one memory package configured for electrically coupling to a bus on a system board, the at least one memory package comprising an integrated circuit including a plurality of memory devices, and a package substrate including a surface having a plurality of externally accessible contact points coupled to the memory devices and an externally accessible reference signal line and a surface of the package, and tuning the electrical characteristics of the memory package using an electrical potential between the contact points and the reference signal line.

Abstract: A printed circuit board and method for reducing the impedance within the reference path and/or saving space within the printed circuit board. In one embodiment of the present invention, a printed circuit board comprises a plurality of conductive layers. The printed circuit board further comprises two or more vias for interconnecting two or more conductive layers. The printed circuit board further comprises an electrical component embedded in a particular via between two conductive layers to reduce the impedance within the reference path and/or save space within the printed circuit board.

Abstract: A via on a printed circuit board having a circuit has a first interconnect and a second interconnect located about at least a portion of the first interconnect. The second interconnect connects to ground of the circuit and is coaxial and substantially concentric with the first interconnect and inductively coupled with the first interconnect. A method of electrically interconnecting at a via multiple layers on a printed circuit board to provide a common ground plane for a circuit is also provided. A high speed interconnection can be attained by allowing the ground return path for a circuit carried on multiple layers of a multilayer printed circuit board to remain coupled to the signal, thereby lowering ground inductance and maintaining signal integrity, even at UHF, while minimizing costs.

Abstract: A PCSB assembly including a PCSB; a first plurality of LVD SCSI bus signal trace pairs formed in the PCSB; a second plurality of LVD SCSI bus signal trace pairs formed in the PCSB and positioned next adjacent one another for the entire length thereof comprising a RESET signal trace pair, a SELECT signal trace pair and a BUSY signal trace pair.

Abstract: In a circuit board having a multilayer structure comprising a ground pattern and a power-supply pattern both, for example, by forming a plurality of slits along each side of the ground pattern or the power-supply pattern, a long thin conduction path connecting a corner and a side center of the ground pattern is formed and resistive elements are placed in the middles of the conduction path to short, circuit the corner and a side center of the ground pattern. Therefore, portions corresponding to an antinode and a node or antinode and an antinode of a standing wave are short-circuited. The standing wave is generated when electric power is supplied to ICs and LSIs mounted on the circuit board. Thus, noise sources caused by the standing wave cancel each other. As a result, the occurrence of an antiresonance phenomenon and an increase in impedance of the power supplying system caused by the standing wave can be suppressed.

Abstract: Power and ground planes used in Printed Circuit Boards (PCBs) having porous, conductive materials allow liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.

Abstract: A circuit comprising is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Abstract: The invention relates to an electronic unit having a mounting board (4) and electronic components (1-3) mounted on it, with the mounting board (4) having metal webs (41) which are embedded in an electrically insulating material (40), the metal webs (41) having a first side (411), which is in the form of a contact surface for making contact with the electronic components (1-3) and having a second side (412) facing away from this. According to the invention, cutout(s) are arranged in the electrically insulating material (40), via which the second side (412) of each metal web (41) is accessible for a voltage or current measurement apparatus.

Abstract: A method of packaging a device is disclosed. In one embodiment, a substrate including a common voltage plane and a mounting region is provided, with the device mounted to the mounting region. An electrically conductive dam structure is disposed on the surface of the substrate with the electrically conductive dam structure being electrically coupled to the common voltage plane and circumscribing a perimeter of the mounting region. An electrically insulating encapsulant at least partially fills a pocket defined by the substrate and the electrically conductive dam structure, the electrically insulating encapsulant contacting the electrically conductive dam structure. An electrically conductive encapsulant is provided that overlies the electrically insulating encapsulant, the electrically conductive encapsulant being coupled to the electrically conductive dam structure.

Abstract: An inter-layer structure between a power layer and a ground layer of a printed circuit board includes an insulative magnetic structure with at least two layers of insulative magnetic substances with different complex magnetic permeability frequency characteristics.

Abstract: A multi-chip module (MCM) having a substrate including a first surface, a second surface and a multi-layer interconnection arrangement disposed between the two surfaces. A high-density thin-film circuit region is provided on the substrate first surface to interconnect a plurality of integrated circuit chips and the multi-layer interconnection arrangement. The integrated circuit chips are powered through the high-density thin-film circuit region, which receives power from the multi-layer interconnection arrangement. A plurality of discrete on-board voltage converter devices, mounted on at least one substrate surface, provide uniform power supply distribution to multi-layer interconnection arrangement power planes, converting an MCM input voltage and current to a relatively lower output voltage and a relatively higher output current.

Abstract: A multi-layer circuit board comprises: an insulating layer having upper and lower surfaces thereof, and wiring patterns arranged on the upper and lower surfaces of the insulating layer. A ferroelectric layer has a dieletric constant larger than that of the insulating layer and has upper and lower surfaces. The ferroelectric layer is arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively. A pair of electrode films are formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the multi-layer circuit board.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: An apparatus comprising an integrated circuit comprising a plurality of memory devices and signal circuitry coupled to the plurality of memory devices, and a package substrate comprising a first surface coupled to the integrated circuit, a second surface having a plurality of externally accessible contact points coupled to the signal circuitry, and an externally accessible reference signal line disposed between the integrated circuit and the second surface.

Abstract: A multilayer wiring substrate includes differential signal wires placed within a first insulating layer between a first power-supply plane and a first ground plane; and general signal wires placed within a second insulating layer between a second power-supply plane and a second ground plane. In the multilayer wiring substrate, the differential signal wires are placed in a different plane from a plane having each of the general signal wires so that the different plane includes a first area having the differential signal wires, and a second area having one of the second power-supply plane and the second ground plane. The general signal wires are placed in a vertical direction of the second area in a laminated state so that each of the general signal wires is placed between the second power-supply plane and the second ground plane.

Abstract: A table- or workbench covering made of a first electrically conductive layer having a specific resistance in the range of 5×106 &OHgr;cm to 5×109 &OHgr;cm, and a second electrically conductive layer having a specific resistance in the range of 5×104 &OHgr;cm to 5×107 &OHgr;cm, the layers being made of rubber mixtures containing antistatic agents and/or electrically conductive particles and are calendered together as well as connected by vulcanization, and which have a sulfate content of <100 &mgr;g/cm2, extractable using deionized water.

Abstract: A method of designing an electronic component comprises: a) modeling a first material with respect to a characteristic of the first material in a sufficient detail to at least partially account for a first value for the characteristic; b) modeling a second material with respect to a characteristic of the second material in a sufficient detail to at least partially account for a second value for the characteristic; c) modeling an interface between the first material and the second material such that in at least some instances the characteristic of the interface does not have an obvious characteristic or obvious value of between the first value and the second value; and d) generating a set of evaluation data from the modeling of the interface.

Abstract: A technique for reducing the number of layers in a multilayer circuit board is disclosed. The multilayer circuit board has a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer circuit board. In one embodiment, the technique is realized by forming a first plurality of electrically conductive vias in the multilayer circuit board extending from the surface of the multilayer circuit board to a first of the plurality of electrically conductive signal layers, wherein the first plurality of electrically conductive vias are arranged so as to form a channel in a second of the plurality of electrically conductive signal layers beneath the first plurality of electrically conductive vias.

Abstract: A first interconnection pattern having a comb shape is formed around a semiconductor chip on a package body. A second interconnection pattern having a comb shape is formed around the first interconnection pattern. The projections of the first interconnection pattern are engaged with the projections of the second interconnection pattern. The distances between those two groups of projections and the bonding pads of the semiconductor chip are set nearly equal to each other.

Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board comprising: an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.

Abstract: A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.

Abstract: Modularly constructed multichip modules with are disclosed. A plurality of miniature capacitor substrates and/or miniature resistor substrates are assembled and attached to a base substrate, preferably in a regular pattern. Power supply substrates are preferably attached to the base substrate along with the miniature substrates. All of the attached components are preferably pretested and have thicknesses close to one another. The pretesting substantially increases the manufacturing yield. Gaps between the miniature substrates and power supply substrates are filled with a polymer material, such as a powder-filled polyimide precursor. Thereafter, dielectric layer is formed over the components to provide a more planar surface. The dielectric layer is preferably planarized, such as by a chemical mechanical polishing process, to provide for a more planar layer.

Abstract: A multilayer printed-circuit board is provided which is formed by stacking one on the other a plurality of circuit boards, each including a hard insulative substrate having a conductor circuit formed on one or either side thereof, and having formed therein via-holes formed through the hard insulative substrate to extend to the conductor circuit and each filled with a conductive substance, with an adhesive applied between the plurality of circuit boards, and heating and pressing the circuit boards together. One of the outermost ones of the stacked circuit boards has formed on the surface thereof conductive bumps each positioned right above the via-hole and electrically connected to the via-hole, and the other outermost one of the stacked circuit boards has formed on the surface thereof conductive pin or balls each positioned right above the via-hole and electrically connected to the via-hole.

Abstract: A circuit device board having a desired characteristic is provided by bonding dielectric substrates. A printed board 11 carrying patterns 11a and 11b incorporating a resonator is joined by a prepreg 13 to a printed board 12 carrying patterns 12a and 12b, which are substantially identical to the patterns 11a and 11b, so that the patterns come opposite to each other. As a grounding conductor is provided on the outer side of each of the printed boards 11 and 12, a band-pass filter having the three-plate structure is completed. The patterns 11a and 12a are connected to each other for determining the signal input while the patterns 11b and 12b are connected to each other for determining the signal output. Accordingly, the frequency response can be obtained at a desired level regardless of the thickness of the prepreg 13.

Abstract: A multilayer printed circuit board enables needless electro-magnetic radiation to be suppressed. Interlayer insulation materials are arranged in layer-built constitution between respective layers of a mixed wiring layer of a first signal and/or a power supply wiring, a first ground layer, a second ground layer, and a mixed wiring layer of a second signal and/or a power supply wiring. A through-hole for connecting the ground layers with each other is provided adjacently to a through-hole for connecting the signal and/or the power supply between these layers. According to the constitution, a return circuit current route of the signal and the power supply to the ground layers is secured. As a result, a loop made by the current becomes small, thus needless radiation of electro-magnetic wave is capable of being suppressed.

Abstract: Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

Abstract: Isolated planar conductive structures on separated layers of a PCB provide the normally-open, common, and normally-closed components of an electromechanical relay circuit to minimize inductive area. The isolated planar configuration reduces coupling of relay contact-noise currents to nearby sensitive circuits, and minimizes coupling EMI energy from nearby logic or microprocessor circuits to the relay contact circuits.

Abstract: An apparatus for use with data processing systems. In one embodiment, the apparatus includes but is not limited to at least one conductive member having a first end electrically coupled to a first conductive structure which partially forms a moat and a second end electrically coupled to a second conductive structure which substantially spans the moat, with the second conductive structure having at least a part overhanging a third conductive structure which partially forms the moat.

Abstract: A vehicle electric power distribution apparatus is provided which includes a plurality of vertically stacked conductive circuit layers, each layer including an array of contact pads, a layer of electrically insulating plastic material between each of the conductive circuit layers, at least some of the contact pads are electrically connected to selected other contact pads of the same conductive circuit layer via integrally formed conductive traces. In addition to the stacked circuit layers the apparatus includes a plurality of conductive pins providing electrical contact between selected contact pads of different selected conductive circuit layers.

Abstract: In an integrated circuit carrier having a large number of power pins allocated to an internal power plane, the current flowing through the power pins may divide very unevenly, and result in current flow through some of the power pins which exceeds the maximum specification for either the package pin or for the socket into which the package may be inserted. In such a package, the magnitude of the current flowing through the highest current power pin may be reduced by configuring the resistance of the power plane(s) and vias to provide approximately the same total resistance to every power pin location. Slots may be cut in a package power plane to alter the current path and raise the impedance of the conduction path between some of the package power pins and the internal contact pads otherwise having the lowest impedance.

Abstract: The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.

Abstract: The invention relates to a module component having chip components buried in a circuit board, and a method of manufacturing the same, and more specifically it relates to a module component capable of obtaining desired circuit characteristics and functions stably if the size of the component is reduced, being produced very efficiently, and suited to machine mounting, and a method of manufacturing the same.

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.

Abstract: A technique for improving electrical signal performance in multilayer circuit boards by eliminating the need for electrically conductive vias is disclosed. In one embodiment, the technique is realized as an improved multilayer circuit board having an electrically conductive signal layer disposed beneath at least one dielectric layer. The improvement comprises a cavity in the multilayer circuit board extending through the at least one dielectric layer so as to expose at least a portion of the electrically conductive signal layer within the cavity. The cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the electrically conductive signal layer, thereby eliminating the need for an electrically conductive via electrically connected to the electrically conductive signal layer and formed through the at least one dielectric layer or any other layer of the multilayer circuit board.

Abstract: The present invention provides a through-hole structure for connecting a connector to a printed circuit board, the through-hole structure comprising a signal through-hole having a conductive layer therein for supplying a signal to the printed circuit board, power through-holes having a conductive layer therein for supplying power to the printed circuit board, and dielectric constant adjusting portions formed among the signal through-hole and the power through-holes. Moreover, the present invention provides a printed circuit board having the above-described through-hole structure formed therein.

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.

Abstract: A chip assembly (162) with integrated power distribution between an integrated circuit chip (164) and a section of wafer interposer (166) is disclosed. The wafer interposer section (166) has first (80, 82) and second (86, 88) sets of contact pads that are electrically and mechanically coupled to first and second sets of contact pads of the integrated circuit chip (164). The wafer interposer section (166) has first (32) and second (36) supply voltage terminals that are respectively coupled to the first (80, 82) and second (86, 88) sets of contact pads of the wafer interposer section (166) that provide first and second supply voltages to the first and second sets of contact pads of the integrated circuit chip (164), thereby integrating power distribution between the integrated circuit chip (164) and the wafer interposer section (166).

Abstract: An improved circuit board construction featuring a multilayered, laminated structure having an intermediate power core layer having conductive adhesive-filled via through holes. The via through holes of the intermediate power core layer make electrical connection with metallic pads of conductive vias of adjacent outer signal core layers when the layers are laminated.

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

Abstract: A method and implementing computer system are provided in which de-coupling capacitors are used at driver and receiver sources, and defined gaps are created separating power and ground areas on a voltage reference plane of a circuit board. Short-circuit via connections are also provided through one or more vias between spatially separated circuit board layers. Each driver or receiver module includes the driver or receiver along with an associated gap, capacitor and via connections to VDD and ground planes, all included within a defined proximity to effectively block switching energy and/or VDD noise from entering the tri-plate ground-to-ground reference system. In a related exemplary construction, signal lines are placed at predetermined positions between ground planes to provide a tri-plate circuit board structure for transmitting logic signals from a driver to one or more receivers.

Abstract: A wiring board simplifying connection of electronic parts mounted on a principal face side of the wiring board and chip capacitors mounted on a reverse face side thereof in such a manner that the wiring board 100 mounting the chip capacitors 160 on a reverse face 101c-side comprises bumps 129 capable of being connected to IC chip 10, first and second capacitor connecting pads 149p, 149g connecting the upper face parts 163 of the chip capacitors 160, a plurality of insulating layers 121, 111, 141 intervening the first and the second capacitor connecting pads, and first and second converting-conductor layers 146p, 146g in stripe pattern formed at interlayer 152, connected to the bumps 129 at the principal face 101b-side, connected to the first capacitor connecting pads 149p at the reverse face 101c-side or the second capacitor connecting pads 149g for changing the connecting positions or the connecting number between the principal face side and the reverse face side.

Abstract: A printed circuit board includes a ground layer, a power supply layer divided into a plurality of lands, a dielectric layer disposed so as to cover the plurality of lands of the power supply layer, and a conductor layer disposed so as to cover the dielectric layer. The plurality of divided lands are coupled to each other by electrostatic capacitors formed by each of the lands of the power supply layer and the conductor layer sandwiching the dielectric layer therebetween.

Abstract: An arrangement for a motherboard having a connector for a removable module is disclosed which increases the aggregate current carrying capacity of the connector by reducing the difference in current flow between power pins of the connector having the highest current flow and power pins of the connector having the lowest current flow. The current flow through all the power pins may then be operated nearer to the design maximum of the particular connector used. Thicker power planes within the motherboard (as well as within the module) reduce the effective resistance per square of the power plane, and help distribute the current more uniformly to a greater number of power pins of the connector. The use of multiple power planes in parallel also achieves a lower effective resistance. Multiple power terminals connecting the source of regulated power supply voltage (or reference voltage, such as ground) to the power plane may be used instead of just one power terminal.

Abstract: The design and fabrication of a highly integrated, intelligent integral horsepower, three-phase induction motor drive is based on multichip module (MCM) technology. A conventional three-phase induction motor is transformed into a stand-alone variable-speed drive by way of MCM technology. This solid-state controller-known as a multichip power module (MCPM)-uses known good die (KGD) to obtain minimal footprint, volume, and mass, while maximizing efficiency, reliability, and manufacturability. This is done by integrating the low-power control and high-power sections onto a single substrate. In accordance with one embodiment of the present invention, an integrated circuit assembly formed on a single substrate is capable of transforming and controlling AC power input to DC power output responsive to input signals.

Abstract: An improved electrical interconnection between a first circuit board and a second circuit board is provided. In one embodiment, the first circuit board has a substantially rigid circuit portion having a plurality of circuit layers, including a first signal layer, and a first interconnection portion, including the first signal layer, for mating with a second interconnection portion of the second circuit board. The first circuit board also includes a flexible portion, including the first signal layer, for connecting the substantially rigid circuit portion to the first interconnection portion. The flexible portion allows the first interconnection portion to be oriented substantially perpendicular to the substantially rigid circuit portion such that a mating of the first interconnection portion with the second interconnection portion results in a substantially orthogonal electrical interconnection arrangement between the first circuit board and the second circuit board.

Abstract: An electrical interconnect having a multi-layer circuit board structure is designed to facilitate source and load impedance matching. The circuit board structure has a first transmission line extending along a surface of one of the layers, and a second transmission line extending along a surface of another of the layers. A signal line connects the first transmission line to the second transmission line in the vertical direction of the circuit board structure. A conductive ground spacer is interposed between respective layers of the circuit board structure and has a through-hole in which the signal line resides. A dielectric medium, such as air, occupies the through-hole and substantially circumferentially surrounds the signal line. Accordingly, the ground conductor, the signal line and the dielectric medium form a coaxial structure in the vertical direction, by which it is easy to provide a desired characteristic impedance.