Abstract: A voltage-resistant switch comprising a first switching contact and a second switching contact, and an MOS switching transistor having a source terminal, a drain terminal and a gate terminal, wherein the source terminal of the MOS switching transistor is connected to the second switching contact, and the drain terminal of the MOS switching transistor is connected to the first switching contact. The voltage-resistant switch has a switching monitoring unit with a control input and a protection output and a protection switch with a switching input, wherein the switching input is connected to the protection output of the switching monitoring unit and the protection switch is arranged and adapted to electrically connect the gate terminal of the first MOS switching transistor to the source terminal of the first MOS switching transistor in dependence on a protection signal.

Abstract: A lightening conductor (10) for lightning protection of structures (37), particularly of mobile structures (37), comprises a conduit (18) connected to a mast (12) and provided for dissipation of a lightning current. The mast (12) is telescopable so that the height of the lightening conductor (10) can be individually adapted to local conditions and is transported conveniently.

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit includes a pad adapted for connection to a first voltage source of a protected circuit node of the IC, and a silicon controlled rectifier (SCR) having an anode adapted for coupling to the first voltage source, and a cathode adapted for coupling to a second voltage source. At least one capacitive turn-on device respectively coupled between at least one of a first gate of the SCR and the first voltage source, and a second gate of the SCR and the second voltage source.

Abstract: An ESD detection circuit which includes: a triggering circuit for generating an ESD trigger signal when the ESD detection circuit is in ESD mode; a bias circuit for providing at least a first bias voltage and a second bias voltage for controlling the operation of the triggering circuit; a trigger controlling circuit for decreasing a voltage difference between the first bias voltage and the second bias voltage when the ESD detection circuit is in the ESD mode, and for controlling a duration of the ESD trigger signal that is generated by the triggering circuit; and an activating control circuit for activating the trigger controlling circuit and the triggering circuit to enter the ESD mode according to a voltage level at a first node.

Abstract: Example embodiments are directed to an over-voltage protection circuit and method thereof. The over-voltage protection circuit may include a voltage converter, a voltage comparator, a delay unit, and/or a switching unit. The voltage converter may be configured to generate first voltage and second voltages from a supply voltage. The voltage comparator may be configured to compare the first voltage with the second voltage and to generate a control signal according to the comparison result. The switching unit may be configured to determine whether to apply the supply voltage to a chip in response to the control signal. The delay unit may be configured to delay transmission of the control signal to the switching unit by a delay time.

Abstract: A fault detection apparatus of a power source provided with a central processing unit, a power source, a power receiver supplied with current from a power source, a unit periodically accessing the power receiver from the central processing unit so as to supply a periodic current periodically repeatedly turning on and off from the power source to the power receiver, and a unit judging the power source to be defective when the output voltage of the power source exceeds a predetermined threshold value and a method and program for the same. By this, it is possible to judge a power source to be defective when fluctuations in the output voltage of a power source due to the periodic supply of current to the power receiver (voltage load fluctuations) exceed a predetermined threshold value.

Abstract: An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) that provides ESD protection during an ESD event is disclosed. The electrostatic discharge (ESD) protection circuit includes a first electrostatic discharge (ESD) protection component and a second electrostatic discharge (ESD) protection component coupled in series to the first electrostatic discharge (ESD) protection component. A snapback holding voltage of the electrostatic discharge protection circuit is greater than the operating voltage of the electrostatic discharge protection circuit and a snapback trigger voltage of the electrostatic discharge protection circuit is lower than an oxide breakdown voltage of said integrated circuit.

Abstract: Provided is a battery protection circuit and a battery device which may be manufactured at lower cost. Before all terminals of a battery protection circuit are each connected to batteries, even when a logical circuit malfunctions by an operation of a parasitic bipolar transistor formed by P-wells due to a connection order in which the batteries are connected, the logical circuit is reset by an operation of a parasitic bipolar transistor formed by the P-wells. For this reason, a charge/discharge path of the batteries is not interrupted due to the connection order. Accordingly, no limitation is placed on the connection order.

Abstract: System and method for protecting an integrated circuit. The system includes a first transistor coupled to a first voltage and a second voltage, a second transistor coupled to the gate of the first transistor and the first voltage, a third transistor coupled to the gate of the second transistor and the first voltage, and a capacitor coupled to the gate of the second transistor and the second voltage. The first voltage is provided to the integrated circuit, the gate of the third transistor is configured to receive a first control signal, the gate of the second transistor is configured to receive a second control signal, and the second control signal is capable of turning off the second transistor a time period after the third transistor is turned off.

Abstract: An over-voltage protection circuit is disclosed herein for protection against over-voltage of an energy storage device while charging. The circuit operates within the operational limits of a battery-operated device, such as a mobile or handheld device. The over-voltage protection circuit comprises an over-voltage protection device, and an over-voltage protection controller. The controller allows current to flow to the over-voltage protection device only when an energy storage device is experiencing over-voltage.

Abstract: An output driver in an integrated circuit includes a driver circuit operable by a power supply voltage and coupled to an output pad, and a driver power conditioner configured to generate a fractional pad voltage in response to a voltage on the output pad and to provide the fractional pad voltage to at least one transistor of the driver circuit as a protected supply voltage in response to an absence of the power supply voltage.

Abstract: A method for assessing metal vapor arcing risk for a component is provided. The method comprises acquiring a current variable value associated with an operation of the component; comparing the current variable value with a threshold value for the variable; evaluating compared variable data to determine the metal vapor arcing risk in the component; and generating a risk assessment status for the component.

Abstract: An overvoltage protection circuit is for a circuit of an output MOS transistor and a load connected in series between a first power supply and a second power supply. The overvoltage protection circuit contains a control signal circuit, a dynamic clamping circuit, a control switch, and a serge detecting circuit. The control signal circuit is connected between a gate of said output MOS transistor and said load, and the dynamic clamping circuit is connected with said gate of said output MOS transistor. The control switch is connected between said first power supply and said dynamic clamping circuit and the serge detecting circuit which monitors a voltage of said first power supply and turns on said control switch when the voltage of said first power supply increases to a voltage higher than a predetermined voltage.

Abstract: Protection is provided against electrical surges resulting from Electrical Over Stress conditions, e.g., when interfacing circuits with powered connections. An EOS shunt is activated for as long as the EOS condition exists. EOS protection using an EOS shunt in accordance with the principles of the present invention remains activated by a voltage threshold trigger as long as necessary. In a disclosed embodiment, an EOS shunt includes a voltage threshold detector that detects a voltage on a power bus with respect to a ground rail exceeding a predetermined amount, e.g., 5 volts in a device powered at 3.3 volts. During the EOS event, a path between power and ground comprising a transistor is turned on.

Abstract: The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.

Abstract: Device for the protection of electric lines which comprises: processing means; power supply means; voltage measurement means; means of alert; and switching means which alternatively send the line's own current through a main branch (which comprises the remaining components) or through a branch line; and method for the protection of electric lines by means of the device in accordance with the invention, which comprises: normal operating mode—safety element in perfect condition and inactive protection device; boundary anomalous operating mode—the intensity circulating through the safety element surpasses a caution threshold and the protection device signals said condition; and line verification anomalous operating mode—after failure of the safety element, all the current flows through the protection device and the protection device detects, signals, and analyses said condition.

Abstract: An integrated circuit includes a first RF port and a second RF port. A limiter section is disposed between the first RF port and the second RF port and a detector section coupled to an RF signal path between the first RF port and the second RF port configured to detect a power level of an input signal, and coupled to the limiter section.

Abstract: The invention describes combination I/O modules for automation. Various combinations of inputs and output with different electrical interfaces are offered providing greater flexibility in controller hardware selection.

Abstract: An inverter circuit includes an IGBT (3) and an IGBT (4) connected in series between a power supply potential (Vcc) and a GND potential, and an HVIC (1) and an LVIC (2) for respectively controlling actuation of the IGBTs (3) and (4). The inverter circuit also includes a capacitor (5), a diode (6), and a resistor (7). The capacitor (5) is connected between a terminal (VS) and the GND potential. The diode (6) has a series connection to the capacitor (5) between the terminal (VS) and the GND potential, with such a polarity that a forward current flows from the GND potential to the terminal (VS). The resistor (7) is connected in parallel to the capacitor (5).

Abstract: An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and ensure transistors are not electrically overstressed. As input-related terminals experience switching related voltages, the bias selectors select alternate terminals to continue selection of the highest voltage available and provide correct reverse biasing conditions. A resistor and clamp generate translated output voltage levels limited to the native supply voltage range. A latch is triggered by a first input signal excursion above the native supply voltage.

Abstract: An over-voltage protection circuit structure for protecting a high power translation circuit is provided. The over-voltage protection circuit structure receives an alternating current input and comprises a relay circuit, a voltage detection module, and an energy supply circuit. The relay circuit relays the alternating current input to the high power translation circuit. The energy supply circuit provides power to the voltage detection module in response to the alternating current input. The voltage detection module detects a voltage value of the alternating current input continuously. When the voltage value is greater than or equal to a first reference value, the voltage detection module generates an over-voltage signal. The relay circuit opens to cease delivering the alternating current input into the high power circuit in response to the over-voltage signal, thus the purpose of protecting the high power circuit is achieved.

Abstract: An overvoltage protection system and method including a control circuit and a bank of resistors to absorb the energy from a transient voltage without exceeding an allowed temperature for the resistors. The resistors in the bank are independently switched and configured such that upon detection of an overvoltage condition a combination of the resistors is switched into the circuit to dissipate energy. The resistance introduced by the combination of resistors prevents the voltage from rising to an unacceptable level that may damage the circuit being protected. As time progresses, the control circuit alters the combination of resistors in the bank of resistors so as to increase the effective load resistance value, thereby decreasing a load current.

Abstract: A current limiting device includes a constant current source circuit constructed and arranged to be connected to a direct current input voltage source and to regulate electrical current and a resonance source circuit receiving current from the constant current source circuit. The resonance source circuit is constructed and arranged to be electrically connected with an electro-luminescent (EL) lamp so that the EL lamp receives alternating current. The constant current source circuit and the resonance source circuit are constructed and arranged such that when current flows from the constant current source circuit to the resonance source circuit and to the EL lamp, a maximum peak current received by a user contacting an output of the device or contacting the EL lamp is less than about 0.7 mA.

Abstract: An input voltage sensing circuit comprising a circuit input terminal; a comparator having first and second input terminals, the first of said input terminals being coupled to a reference voltage; a switch circuit provided between the circuit input terminal and the second of the input terminals of the comparator, the switch being provided to protect the comparator from voltages exceeding a predetermined voltage at which the switch turns off; and an electrostatic discharge circuit coupled to the circuit input terminal for discharging electrostatic induced voltages exceeding a predetermined value.

Abstract: A switching power supply device includes: a switching element connected through a primary winding of a transformer to an output end of an input rectifying/smoothing circuit that rectifies and smoothes an alternating current input voltage and outputs a direct current input voltage; an output rectifying/smoothing circuit that rectifies and smoothes a voltage induced in a secondary winding of the transformer and outputs a direct current output voltage; and a control circuit that controls ON and OFF of the switching element.

Abstract: An anomaly control device for a dual fan of computer is composed of a first and second coil, a first and second driving IC, a controller, and a voltage level comparing circuit. The voltage level comparing circuit will perform a voltage dividing to a first and second reference potential signals input from the first and second driving ICs to obtain a third reference potential signal which is compared with a reference pulse wave signal output from an output end of the first driving IC, to determine to output either a high level pulse voltage signal or a low voltage direct-current signal to the controller for processing. The controller will output a control-gate-on or a control-gate-off signal to the first and second driving ICs for enabling the first and second coils to continue to operate or to stop operating.

Abstract: A system for regulating high speed voltage surges, particularly as a result of lightning strikes, which includes a transistor, an isolated voltage provider, and an array of voltage regulating electrical components, where the isolated voltage provider maintains the transistor in a fully on mode unless a voltage surge occurs. In the case of a voltage surge the array of voltage regulating electrical components switches the transistor to linear mode thus providing protection equal to its rating. A method of determining the voltage rating of individual Zener diodes contained within a Zener diode array consisting of shorting out individual diodes from the array and measuring the total voltage rating, then comparing the total voltage rating of the array with no diodes shorted out to the voltage rating of the array with the one diode shorted out.

Abstract: Circuit and method for providing over-current and overloading protection with a single additional pin. A converter controller circuit is provided that includes a voltage controlled oscillator and outputs upper and lower gating signals for driving the upper and lower driving transistors in a voltage converter, for example, in an inductor-inductor capacitor half-bridge circuit topology. A current sense input pin of the circuit receives a voltage corresponding to the current flowing in the half-bridge circuit. A feedback input pin has an external capacitor coupled to it and receives a voltage from an output voltage sensor at the output terminals. Over-current protection is provided by sensing the voltage at the current sense input pin with no external components needed. Overload protection is provided by utilizing the external feedback capacitor and the feedback input pin during overload conditions. Methods for providing over-current and overload protection are disclosed.

Abstract: A thin film circuit substrate is provided with a voice-output-section driving section, formed of a thin film layer on an insulative substrate, for driving a voice output section. An antisurge section, provided on a wiring between the voice-output-section driving section and an output terminal section thereof, includes an antisurge element. When a surge voltage is applied to the wiring, the antisurge element, monolithically formed on the thin film circuit substrate, connects the wiring to the ground so as to pass a current (surge current), generated by the surge voltage applied to the wiring, to the ground. This makes it possible to provide a thin film circuit substrate which is monolithically provided with a function which can protect a circuit section when a voltage exceeding a predetermined range is applied to the wiring linking the circuit section with an input terminal section or an output terminal section.

Abstract: The invention relates to a surge protector device of the spark gap lightning arrestor kind, the device comprising: a first spark gap (E1); a first pre-trigger system (2) electrically connected to the first spark gap (E1) in such a manner as to enable an arc to be struck therein; and a control device (4) electrically connected to the first pre-trigger system (2) in such a manner as to activate it; the protector device being characterized in that it includes at least one second spark gap (E2) connected in parallel with the first spark gap (E1), and electrically connected to a second pre-trigger system (3) connected in parallel with the first pre-trigger system (2), in such a manner that the control device (4) activates the first and second pre-trigger systems (2, 3) simultaneously so as to trigger the first and second spark gaps (E1, E2) simultaneously. Devices for providing protection against surges.

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry is provided herein. In one embodiment, a circuit for protecting an integrated circuit from ESD includes a protected circuit node in the integrated circuit, a multiple stage transistor pump circuit coupled to the protected circuit node, and an electrostatic discharge protection circuit having a trigger coupled to the multiple stage transistor pump circuit. The multiple stage transistor pump circuit may comprise a Darlington transistor pump circuit.

Abstract: An overvoltage protection system and method including a control circuit and a bank of resistors to absorb the energy from a transient voltage without exceeding an allowed temperature for the resistors. The resistors in the bank are independently switched and configured such that upon detection of an overvoltage condition a combination of the resistors is switched into the circuit to dissipate energy. The resistance introduced by the combination of resistors prevents the voltage from rising to an unacceptable level that may damage the circuit being protected. As time progresses, the control circuit alters the combination of resistors in the bank of resistors so as to increase the effective load resistance value, thereby decreasing a load current.

Abstract: A semiconductor device includes one or more first transistors of which each source connects to a power wiring, a second transistor of which a source connects to a ground wiring and a drain connects to a drain of the first transistor, one or more third transistors of which each source connects to the power wiring and each drain connects to the drains of the first and second transistors, and a gate potential control circuit which controls the gate potential of the third transistors based on the potential of the power wiring.

Abstract: A switching power supply is modified to mitigate potentially adverse effects of near zero loads on power delivery. In one example, a processor-controlled dummy load is coupled to the power supply output in addition to an actual load. The dummy load is controlled so that at least some minimal load is presented to the power supply when the actual load is drawing low or near zero power. In another example, the feedback loop of the switching power supply is modified to mitigate the effects of a potential overvoltage condition in a bias supply from which the switch controller of the power supply draws power, which condition may occur at low or near zero load power. A lighting system may include a switching power supply thusly modified to provide power to a variable load that includes one or more LED-based lighting apparatus.

Abstract: A semiconductor integrated circuit includes a first and second power supply domain circuits having a first and second power supply terminals, respectively. An internal signal propagation line propagates a signal from a circuit of the first power supply domain circuit to that of the second power supply domain circuit. A voltage detector detects a surge voltage input to the first and second power supply terminals and outputs, from a control signal node, a control signal which is determined in accordance with a capacitive coupling by a first capacitor between the first power supply terminal and the control signal node, a second capacitor between the second power supply terminal and the control signal node, and a load capacitance at an output side of the control signal node. A voltage limiting circuit limits a voltage of a signal on the internal signal propagation line in accordance with the control signal.

Abstract: This invention discloses a semiconductor device including a first buffer MOSFET of a first conductivity type, a second buffer MOSFET of a second conductivity type, an ESD protection circuit, an external input terminal, and a control circuit. The external input terminal capacitively couples to a terminal to which a second potential is applied, and receives the first potential or second potential in a normal operation mode. The control circuit includes a prebuffer which controls the gates of the first and second buffer MOSFETs on the basis of the potential of the external input terminal in the normal operation mode and fixes the external input terminal to the second or first potential by capacitive coupling upon ESD surge application, thereby fixing the gate of the second buffer MOSFET to the second or first potential and turning off the second buffer MOSFET.

Abstract: A protection ability of a power supply control circuit is improved so as to protect an output transistor against a back electromotive voltage from a load, a dump surge voltage, and a positive spike surge voltage which has a smaller energy but is higher than the dump surge voltage. The power supply control circuit includes: an output MOS transistor (power semiconductor device) connected between a first power supply terminal and an output terminal; a load connected to the output terminal; a first dynamic clamping circuit for controlling a voltage difference between a first power supply line and the output terminal; and a first switch connected between the first dynamic clamping circuit and the output MOS transistor, in which a conductive state is determined according to a result of comparison between a reference voltage and a voltage at the output terminal.

Abstract: An electro static discharge (ESD) protection circuit employing a field-effect transistor (FET) having no silicide block disposed thereon. It is connected with an internal circuit so as to prevent the internal circuit from the influence of an ESD event, wherein the internal circuit has at least a signal input end. The ESD protection circuit includes: an ESD clamp circuit for providing an ESD grounding path as an ESD occurs; and at least a pair of p-n junction diodes. The p-n junction diodes are stacked so that one of the p-n junction diodes has a n-type end coupled to the signal input end and the other one has a p-type end coupled to the signal input end as well. The ESD clamp circuit has at least a FET, whose drain has no silicide block disposed thereon.

Abstract: An ESD protection system for an image sensor array includes a two-dimensional array of pixels formed on a substrate. Each of the pixels is connected to a gate line and a data line. The system includes a common ESD bus and at least one ESD protection circuit formed on the substrate. The protection circuit includes: a pair of thin film transistors connected in a back-to-back configuration with a first terminal connected to one of the gate lines, and a second terminal connected to the common ESD bus. Upon the occurrence of an electrostatic discharge onto the gate line causing the voltage across the terminals to exceed a threshold value, the protection circuit discharges the ESD charge from the gate line to the ESD bus, thereby preventing damage to each of the switching transistors in the pixels connected to the gate line.

Abstract: An electronic circuit configuration for connecting an active rotary speed sensor.

Abstract: One embodiment of the invention includes a power regulation system. The system comprises a power regulator configured to periodically generate a switch signal that regulates a current flow through an inductor to set a magnitude of an output voltage. The system further comprises an overvoltage protection circuit configured to monitor a peak voltage magnitude of the switch signal and to generate an overvoltage indication signal in response to the peak voltage magnitude of the switch signal exceeding a predetermined limit.

Abstract: Methods and apparatus for over-voltage protection of device inputs are disclosed. An example apparatus to protect a device from an over-voltage condition disclosed herein comprises a switch coupled between a device input and at least one component of the device, and a voltage compensator to pull a control input of the switch to a voltage associated with the device input to open the switch to protect the device component from the over-voltage condition.

Abstract: An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.

Abstract: A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.

Abstract: A protection circuit for an NMOS device is provided. The protection circuit includes a cascoding NMOS transistor and an adjusting circuit. The cascoding NMOS transistor is cascoded between the NMOS device and an external voltage source. The adjusting circuit is coupled to the external voltage source, a gate of the cascoding NMOS transistor, and an internal voltage source. The adjusting circuit adjusts the voltage at the gate of the cascoding NMOS transistor according to the voltages of the external voltage source and the internal voltage source so as to protect the NMOS device from a voltage stress caused by the external voltage source.

Abstract: A driving circuit of a switch includes first and second transistors connected in series to each other and to relative intrinsic diodes in antiseries and driven by a driving device that includes at least one first and one second output terminal connected to the switch to supply it with a first control signal for driving the switch in a first working state and a second control signal for driving the switch in a second working state. At least one latch circuit coupled between respective common gate and source terminals of the first and second transistors supplies the common gate terminal with the first and second control signals, respectively, according to the working state to turn off and turn on the first and second transistors.

Abstract: Disclosed is an ESD protection circuit, which includes: an ESD protection element, coupled to a pad; a transmitting gate circuit; an N MOSFET, for providing a first biasing voltage to the transmitting gate circuit according to the second voltage level; a first P MOSFET, for providing a second biasing voltage to the transmitting gate circuit according to the first voltage level; a delay circuit for determining the turning on and turning off time of the transmitting gate circuit; a first inversing logic circuit, for generating a first control signal according to the output of the delay circuit; and a second inversing logic circuit, for generating a second control signal according to the output of the first inversing logic circuit, wherein the transmitting gate circuit turns on or turns off according to the first control signal and the second control signal.

Abstract: Electrostatic discharge and electrical overstress protection circuit is disclosed to include a discharging circuit, a detection circuit and a controller. The controller is operable to sense and compare the output voltage from the detection circuit to a reference voltage. The controller, upon detection of a normal operating condition or an electrical overstress (EOS) situation, is operable to cause the discharging circuit to discharge any excess voltage from the voltage supply to the electrical ground at a safety voltage level. The controller, upon detection of an electrostatic discharge (ESD) event, is operable to cause the discharging circuit to discharge the excess voltage at a second voltage level that is less than the safety voltage level.

Abstract: A circuit and a method are provided for protecting sensitive circuitry from over voltage and over current during a double fault situation. The circuit may be used in a portable electronic device, and may include an over voltage protection component and an over current protection component. The over voltage protection component may be coupled across power supply inputs of a load of the portable electronic device. The over current protection component is configured in the circuit to provide over current protection to the load of the portable electronic device at least when the over current protection component provides over current protection to the over voltage protection component.

Abstract: An exemplary backlight control circuit includes a load (250), an inverter circuit (230), a pulse width modulation integrated circuit (PWM IC) (210), a protecting circuit (270), and a feedback circuit (240). The load (250) includes two backlight lamps (251, 252) with first terminals (241). The PWM IC with a protecting output (215) is connected to the load via the inverter circuit. The protecting circuit haves a reference voltage. The first feedback circuit is capable of outputting a voltage to the protecting circuit corresponding to the voltage detected from the first terminals. The protecting circuit is configured to control the PWM IC to stop outputting a backlight adjusting signal to the inverter circuit such that the inverter circuit stops driving the load when the output voltage is higher than the reference voltage of the protecting circuit.