Abstract: Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example method of removing a substrate current from a substrate disclosed herein comprises injecting the substrate current via turning on an active device, forming a low impedance path to ground via a substrate clamp based on the substrate current, and removing the substrate current from the substrate via the substrate clamp.

Abstract: An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

Abstract: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.

Abstract: An overvoltage protection element having at least one overvoltage limiting component in a housing, terminal contacts for electrical connection of the overvoltage protection element to a path to be protected, an electrically conductive connecting element and with a spring system acting on the connecting element, a first terminal contact being directly connected with the first pole of the overvoltage limiting component, the connecting element being in electrically conductive contact with the second terminal contact and the second pole of the overvoltage limiting component via a thermally separating connection. With the thermal connection separated, the connecting element moves out of electrically conductive contact with the second terminal contact and the second pole of the overvoltage limiting component by the force of the spring system an insulating disconnecting element connected to the connecting element is moved between the second terminal contact and the second pole of the overvoltage limiting component.

Abstract: An interface circuit and a communication device are provided. The interface circuit includes a transformer unit, a protection unit, and an interface unit. A secondary side of the transformer unit is connected with a chip. A first terminal of the protection unit is electrically connected with a center tap of a primary side of the transformer unit, and a second terminal of the protection unit is grounded. A first access terminal of the interface unit is connected with a first port of the primary side of the transformer unit, a second access terminal of the interface unit is connected with a second port of the primary side of the transformer unit, and a third access terminal and a fourth access terminal of the interface unit are electrically connected with the first terminal of the protection unit respectively.

Abstract: A DC power tool having an interiorly provided lithium battery element and a charging switch includes a safety protection module to eliminate the risk of circuitry burn-out and other dangers resulting from connecting the power tool to a power supply with unmatched rated voltage and rated current when charging the power tool via use of an adapter.

Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

Abstract: An overvoltage protection circuit for protecting a pass element in a controlled voltage supply circuit electrically connected between a circuit power supply interconnection terminal region suited for electrical connection to a circuit power supply and an output terminal, the pass element being protected from voltage surges that may occur on the circuit power supply interconnection with respect to a voltage reference interconnection. A voltage reference is provided electrically connected in series with a voltage. The voltage divider and the voltage reference are connected in series with one another between the circuit power supply interconnection and the voltage reference interconnection. A threshold switch is electrically connected to a corresponding one of the voltage divider output and one of the voltage divider terminating regions terminating regions, and has an output coupled to the pass element control region.

Abstract: A circuit includes: an input of shunt circuitry to couple with an output of detection circuitry that provides a protection signal; an output of the shunt circuitry to couple with an input of power amplification circuitry; and the shunt circuitry configured to reduce a gain of the power amplification circuitry responsive to the protection signal, the shunt circuitry including a delay stage configured to continue shunting of an input signal of the power amplification circuitry for a time period corresponding to a turn on time of the power amplification circuitry. In addition, a method includes: receiving a protection signal from detection circuitry; responsive to the protection signal, shunting an input signal of power amplification circuitry to reduce a gain of the power amplification circuitry; and continuing the shunting for a time period corresponding to a turn on time of the power amplification circuitry.

Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).

Abstract: A load dump protection system is operable to provide protection for power transistors used to drive a blower motor of a vehicle. The load dump protection system includes circuitry for detecting an over-voltage transient. The circuitry adjusts a drive transistor into a saturation mode in response to a detection of an over-voltage transient. The circuitry lowers the power dissipated by the drive transistor when the drive transistor is in the saturation mode.

Abstract: An overvoltage protection element with a housing, at least one overvoltage limiting component in the housing, especially a varistor, and two connecting elements for electrically connecting the overvoltage protection element to a current or signal path in a normal state, the connecting elements being in electrically conductive contact with a respective pole of the overvoltage limiting component. In the normal state of the overvoltage protection element, at least one pole is connected to a connecting element via a plug-and-socket connection, and at least one spring is located between the housing and the overvoltage limiting component such that, when the overvoltage limiting component is thermally overloaded, it is turned by the spring separating the at least one pole from the assigned connecting element, and creating a thermally separating connection between the overvoltage limiting component and the housing when the temperature of the overvoltage limiting component exceeds a given boundary temperature.

Abstract: System and method for protecting an integrated circuit. The system includes a first transistor coupled to a first voltage and a second voltage, a second transistor coupled to the gate of the first transistor and the first voltage, a third transistor coupled to the gate of the second transistor and the first voltage, and a capacitor coupled to the gate of the second transistor and the second voltage. The first voltage is provided to the integrated circuit, the gate of the third transistor is configured to receive a first control signal, the gate of the second transistor is configured to receive a second control signal, and the second control signal is capable of turning off the second transistor a time period after the third transistor is turned off.

Abstract: Improved protection circuits are provided for use as voltage overload protection circuits, ESD protection circuits for RF input pins, and unit protection cells for distributed amplifiers. Preferably, the protection circuits include a positive threshold voltage trigger used to trigger a switch wherein the trigger includes a diode string in series with a resistor and the switch includes a bipolar transistor switch in series with a diode. Alternatively, the trigger includes a diode string in series with a single diode and a single resistor, and is used to trigger a Darlington pair transistor switch in series with a diode. In another embodiment, a Darlington pair transistor switch is triggered by a capacitor. In use with distributed amplifiers, the ESD protection circuits are preferably absorbed inside the artificial transmission lines of the distributed amplifier.

Abstract: A test plug for use with protective relays has a circuit that when it detects an overvoltage on the secondary side of a current transformer limits the overvoltage amplitude and the occurrence of the overvoltage to a predetermined number of peaks that are less than all of the peaks that occur when the secondary side is open circuited and the test plug is connected to the relays. The test plug also ensures that there is a continuous flow of current in the relays. The test plug further that has an indicator visible external to the plug to indicate the occurrence of an open circuit transformer secondary and that indicator remains illuminated when the test plug is disconnected from the protective relays.

Abstract: A circuit and a method are provided for protecting sensitive circuitry from over voltage and over current during a double fault situation. The circuit may be used in a portable electronic device, and may include an over voltage protection component and an over current protection component. The over voltage protection component may be coupled across power supply inputs of a load of the portable electronic device. The over current protection component is configured in the circuit to provide over current protection to the load of the portable electronic device at least when the over current protection component provides over current protection to the over voltage protection component.

Abstract: In one or more embodiments, a switched mode power supply circuit is configured to monitor and control its output voltage during discontinuous conduction mode (DCM) operation, to prevent output over-voltage conditions. For example, in one embodiment, a switched mode power supply circuit is configured to operate selectively in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), and it includes a control circuit that is configured to detect an output over-voltage condition during DCM operation. The control circuit reduces the output voltage of the switched mode power supply circuit responsive to detecting the output over-voltage condition, such as by activating a pull-down device and/or temporarily reverting the switched mode power supply circuit to continuous conduction mode (CCM) operation.

Abstract: A system for testing a power supply unit includes a test sub-system and a test control sub-system connected to the test sub-system and the power supply unit. The test sub-system perform tests and record the results. The test control sub-system is capable of selecting test items to test the power supply unit and setting an execution sequence of the test items. The test items includes a standby test item for testing the power supply unit at a standby state, a normal test item for testing the power supply unit at a normal state, and an over temperature protection test item for testing the power supply unit at an over heated state. The test control sub-system is further capable of automatically switching the standby test item to the normal test item, and switching the normal test item to the over temperature protection test item.

Abstract: A device intended to meet flameproof approval requirements is configured to have two compartments separated by an energy-limiting barrier. The first compartment of the device houses the wiring terminations that bear ignition-capable energy and, therefore, must be flameproof. The energy-limiting barrier is configured to limit the energy that can reach the second compartment to a level that is not ignition capable. This allows the second compartment to be safe without meeting the flameproof requirements, and allows user-interface elements such as switches and indicators to be designed in a more cost-effective manner.

Abstract: A protective circuit connected between a terminal of a semiconductor integrated circuit and ground (GND), comprises: a first diode having an anode connected to the terminal of the semiconductor integrated circuit; a second diode having an anode connected to GND and a cathode connected to the cathode of the first diode; a transistor having a collector or drain connected to the terminal of the semiconductor integrated circuit, and an emitter or source connected to GND; and at least one third diode connected in series in a forward direction from the cathode of the first diode toward the base or gate of the transistor.

Abstract: A system for real-time modeling of uninterruptible power supply (UPS) control elements protecting an electrical system is disclosed. The system includes a data acquisition component, a power analytics server and a client terminal. The data acquisition component acquires real-time data output from the electrical system. The power analytics server is comprised of a virtual system modeling engine, an analytics engine and a UPS transient stability simulation engine. The virtual system modeling engine generates predicted data output for the electrical system. The analytics engine monitors real-time data output and predicted data output of the electrical system. The UPS transient stability simulation engine stores and processes patterns observed from the real-time data output and utilizes a user-defined UPS control logic model to forecast an aspect of the interaction between UPS control elements and the electrical system subjected to a simulated contingency event.

Abstract: A system for providing real-time modeling of protective device in an electrical system under management is disclosed. The system includes a data acquisition component, a virtual system modeling engine, and an analytics engine. The data acquisition component is communicatively connected to a sensor configured to provide real-time measurements of data output from protective devices within the system under management. The virtual system modeling engine is configured to update a virtual mode of the system based on the status of the protective devices and to generate predicted data for the system using the updated virtual model. The analytics engine is communicatively connected to the data acquisition system and the virtual system modeling engine and is configured to monitor and analyze a difference between the real-time data output and the predicted data output. The analytics engine is also configured to determine the bracing capabilities for the protective devices.

Abstract: An electrostatic discharge protection circuit protects the internal circuits of a semiconductor. The electrostatic discharge protection circuit includes a first electrostatic protection unit connected to a power source supply pad. The first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit. A driver driven by the first driving voltage generates a second driving voltage by an ESD current. A second electrostatic protection unit discharges the introduced ESD current into the power source supply pad by the second driving voltage such that a voltage applied to a gate of the first NMOS transistor is reduced.

Abstract: A system for performing real-time failure mode analysis of a monitored system is disclosed. The system includes a data acquisition component, an analytics server and a client terminal. The data acquisition component is communicatively connected to a sensor configured to acquire real-time data output from the monitored system. The analytics server is communicatively connected to the data acquisition component and is comprised of a virtual system modeling engine, an analytics engine and a machine learning engine.

Abstract: Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are connected to each other. A capacitor in which an end is connected to the first pad and the other end is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor. The ESD protection devices also includes a resistor in which an end is connected to the second pad and the other end is connected to the capacitor. The first pad may be a power pad and the second pad may be a ground pad. Alternately, the first pad may be an input/output pad and the second pad may be a ground pad.

Abstract: An apparatus for protecting a device against an over-voltage condition that is in excess of its breakdown voltage includes a detector for detecting the over-voltage condition and a protection circuit for protecting the device in response to detection of the over-voltage condition. The protection circuit may include a transmission gate and a PMOS transistor for producing a protection signal. The protection signal may be applied to a gate and/or a drain and/or a source and/or a well of the device such that a voltage across the device does not exceed the breakdown voltage. The protection signal may be derived from the over-voltage condition independent of whether a supply of power to the device is present.

Abstract: Semiconductor device having an amplifier. In one embodiment, the amplifier includes a first amplifier path including a first input and a second amplifier path including a second input. An inductance having a connectable node is connected between the first and second inputs, the connectable node being symmetrically connected between the first and second inputs. At least one ESD protection structure is connected to the connectable node. In one embodiment, the semiconductor device is used in a communications device.

Abstract: An ESD device with a protection structure utilizing radiated heat dissipation to prevent or reduce thermal failures. The device includes a voltage switchable polymer 10 between electrodes 11 and 12, which is configured to provide a heat radiating surface 40 for radiating heat when an ESD condition occurs. A radiation transmission material 19 is disposed between the heat radiating surface and the environment for radiating heat 20 when an ESD event occurs. One embodiment adds a spacer 50 for accurately spacing electrodes. A method for fabricating the device is further illustrated.

Abstract: Transient overvoltage suppression circuit prevents voltage surges from damaging an attached load. The suppression circuit includes a transistor connected in series with a low-side or return line of the load. A control circuit monitors the voltage on the input line (i.e., high-side) and in response to a detected voltage transient turns the transistor OFF to isolate the load from the transient voltage.

Abstract: An over-voltage protection device includes a comparison module, a first switch, a second switch and an output switch. The comparison module compares a divided input voltage with a threshold voltage to output a control signal according to the comparison result. The first switch is coupled with the comparison module and controlled by the control signal. The second switch is coupled with the first switch and is controlled by the output signal of the first switch. The output switch is coupled with the second switch, the output switch is coupled with the voltage output terminal, and the output switch is coupled with the voltage input terminal. The output switch is controlled by the output signal of the second switch to cut off the input voltage or pass the input voltage to the voltage output terminal.

Abstract: A photovoltaic array for use in an electrical power system includes multiple photovoltaic modules and a voltage converter coupled to at least one of the photovoltaic modules. The photovoltaic array also includes an over-voltage protection circuit. The over-voltage protection circuit includes an interface adapted to couple to an output of the voltage converter. The over-voltage protection circuit also includes a spike detector configured to detect a voltage spike in an output voltage of the voltage converter. The over-voltage protection circuit further includes a voltage control module configured to regulate an output voltage slew rate of the voltage converter in response to an over-voltage signal received from the spike detector.

Abstract: In a charging circuit charging a battery based on a power supply voltage from an external power supply, a charging transistor is provided on a path from the external power supply to the battery. A charging control circuit is integrated on a semiconductor substrate, and adjusts an ON state of the charging transistor to control a charging current supplied to the battery. The voltage adjusting circuit provided on an electric power supply path from the external power supply to a power supply terminal of the charging control circuit generates a necessary voltage drop. The current adjusting circuit adjusts the ON state of the charging transistor such that a voltage of the battery is brought close to a predetermined voltage value. The clamp circuit clamps a voltage at the power supply terminal of the charging control circuit below a predetermined clamp voltage.

Abstract: A power circuit includes a gate drive sever comparator circuit operable to disconnect a pre-drive transistor circuit from ground in response to an over voltage fault condition. A back-up gate drive comparator circuit operable to switch a reference directly into a multiple of shunt MosFets such that the multiple of shunt MosFets are turned on to reverse the over voltage fault condition until voltage drops and the gate drive sever comparator circuit and the back-up gate drive comparator circuit turn off to maintain a regulated voltage between comparator controlled limits.

Abstract: A semiconductor device for coupling a transient voltage at an input node to a reference node, the device having a bipolar transistor adapted to couple its collector to an input node and its emitter to the reference node and a driver device adapted to be coupled between the input node and the base terminal of the transistor such that the driver device is responsive to a transient voltage at the input node to turn on the transistor, thereby shunting the transient voltage to the reference node. Preferably, the input node is coupled to a high speed data transmission line that operates below 5 v and the reference node is coupled to ground and the transistor is an NPN transistor. The driver may preferably be a gate-drain connected MOS transistor with its gate-drain terminal coupled to the collector terminal of the transistor and its source terminal coupled to the base terminal of the transistor.

Abstract: A liquid crystal display (LCD) device having electrostatic discharge (ESD) protection functionality is disclosed. The LCD device includes a flexible printed circuit board, an LCD panel, a lighting module, a first ESD protection unit, and a second ESD protection unit. The lighting module is disposed on the flexible printed circuit board. The first ESD protection unit is disposed in the LCD panel and is coupled between the first end of the lighting module and the ground of the flexible printed circuit board. The second ESD protection unit is disposed in the LCD panel and is coupled between the second end of the lighting module and the ground of the flexible printed circuit board.

Abstract: Improved protection circuits are provided for use as voltage overload protection circuits, ESD protection circuits for RF input pins, and unit protection cells for distributed amplifiers. Preferably, the protection circuits include a positive threshold voltage trigger used to trigger a switch wherein the trigger includes a diode string in series with a resistor and the switch includes a bipolar transistor switch in series with a single reverse diode. Alternatively, the trigger includes a diode string in series with a single diode and a single resistor, and is used to trigger a Darlington pair transistor switch in series with a single reverse diode. In another embodiment, a Darlington pair transistor switch is triggered by a capacitor. In use with distributive amplifiers, the ESD protection circuits are preferably absorbed inside the artificial transmission lines of the distributed amplifier.

Abstract: An output driver in an integrated circuit includes a driver circuit operable by a power supply voltage and coupled to an output pad, and a driver power conditioner configured to generate a fractional pad voltage in response to a voltage on the output pad and to provide the fractional pad voltage to at least one transistor of the driver circuit as a protected supply voltage in response to an absence of the power supply voltage.

Abstract: An overload power cut-off device is provided in an electric auxiliary system for avoiding overload in the system. The device includes a current detecting unit, a voltage comparing unit, an alarm unit, and a power cut-off unit. The current detecting unit includes a sensor coupled to the loop of the system for detecting a loop current of the system so as to output a sensing signal corresponding to the loop current. The voltage comparing unit compares the voltage value of the sensing signal with a preset voltage value and a voltage value of a rated current for respectively outputting a first driving signal and a second driving signal. The alarm unit receives the first driving signal to generate an alarm signal. The power cut-off unit receives the second driving signal to output a power cut-off signal for cutting off the power supply loop of the electric auxiliary system.

Abstract: A hybrid protection circuit may include a stress detection circuit, a clamp device, and an on-time adjustment circuit. The stress detection circuit may output a detection signal that may be activated when a positive ESD event or a positive EOS event occurs. The on-time adjustment circuit may receive a detection signal and output a clamping signal that may be in an active state until charges generated by a positive ESD event or a positive EOS event are discharged. The clamp device may discharge charges induced by an ESD event or an EOS event. Therefore, a hybrid protection circuit may protect the internal core from both an ESD event and an EOS event.

Abstract: A method for implementing an inductor-capacitor filter in an integrated circuit. Embodiments of the invention implement a 5-pole LC low-pass filter suitable for incorporation in wireless applications necessitating compact layouts. Inductors are formed in an IC as concentric coils on metallization layers, the concentric coils providing a negative coupling coefficient between the inductors. The invention provides programmable frequency response characteristics, enabling the transmission of high-frequency base band information while attenuating carrier RF frequencies.

Abstract: A magnetic interface circuit for interfacing between the line side and the circuit side of a communication channel, such as an Ethernet port, includes a transformer having a primary winding connected to the line side of the channel and a secondary winding connected to the circuit side of the channel. The primary winding is fortified to provide differential mode electrical surge protection on the line side. The transformer design having parasitic L, C and R and, saturation during the surge event, acting to suppress the coupling of the electrical surge to the secondary winding. A voltage limiting device is connected in the circuit side of the channel to limit any voltage surges on the circuit side to a safe level. A pair of voltage limiting devices connected in series with the connection therebetween connected to ground may be used to also provide common mode surge protection.

Abstract: The invention relates to a control system for at least two light tubes connected to a common transformer circuit. The control system comprises a control circuit which is provided with at least two detection inlets (a2, a3) used for detecting lamp currents (I1, I2) passing through the first and second light tubes, respectively. The detected lamp currents (I1, I2) can be regulated to a day mode with a high current intensity, and in a night mode with a low current intensity by the control circuit. The lamp currents (I1, I2) can be detected individually in day mode and in a common manner in night mode. The control system reduces instability of the tubes, in particular flicker.

Abstract: A power integrated circuit with internal over-voltage protection includes a power transistor monolithically integrated with a sense element and a control circuit. The power transistor is connected to an output terminal that is connected (or is connectable) to an external load. The sense element is connected to the output terminal in parallel with the power transistor. The sense element is constructed to be similar to the power transistor except that the sense element has a lower breakdown voltage. When the voltage of the output terminal exceeds the breakdown voltage of the sense element a breakdown current flows from the gate of the sense element to the control circuit. Inside the control circuit, a comparator or other over-voltage protection circuit monitors this feedback and controls the power transistor accordingly to protect the power integrated circuit from damage.

Abstract: A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a combination of low voltage and high voltage transistors.

Abstract: Method, and apparatus for operating a power feed in a computing system. One exemplary embodiment includes monitoring the power feed to ensure the power level of the entire system never remains above a first power level and only remains above a second power level for a period of time determined by a timer level.

Abstract: An apparatus and method for providing electrostatic discharge protection of a transmit integrated circuit including an ESD protect block coupled to an integrated circuit pad in a package without bond wires, and an ESD clamp circuit coupled between the ESD protect block and ground. During transmission, one or more capacitors within the ESD protect block may charge up to various levels near the peak transmit voltage, which reverse biases one or more diodes in the ESD protect block, thereby buffering the transmit circuit from the capacitive load of the ESD clamp circuit. The ESD protect block may prevent the ESD clamp circuit from activating due to the high peak voltages output from the transmit circuit. An embodiment of the ESD protect block may apply particularly to transmit power amplifier circuits in which the output signal peaks at twice the supply voltage. In one embodiment applicable for lower voltage CMOS processes, the ESD protect block includes a diode and a capacitor.

Abstract: An electrostatic discharge (ESD) protection circuit includes an NPN transistor having a collector terminal connected to a voltage source and an emitter terminal connected to the ground via a diode. The NPN transistor includes a base terminal for receiving a base current to turn on the NPN transistor to allow an electrostatic discharge at the voltage source to flow through the NPN transistor to the ground. The ESD protection circuit further includes a PMOS transistor having a source terminal coupled to the voltage source and a drain terminal coupled to the base terminal of the NPN transistor. The PMOS transistor includes a gate terminal for receiving a first and a second gate voltage. The ESD protection circuit further includes an R-C circuit coupled between the source voltage and the ground.

Abstract: An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

Abstract: A semiconductor integrated circuit has a bipolar transistor whose collector is connected to a substrate of an NMOS transistor serving as a protecting transistor. When an ESD event occurs, the bipolar transistor causes the NMOS transistor to be changed into bipolar operation at a low voltage, by supplying current to the substrate of the NMOS transistor. In accordance with this structure, good levels of ESD protecting performance and off leak current of the protecting transistor can both be achieved in the semiconductor integrated circuit.

Abstract: An overcurrent protection arrangement for aircraft to protect an electric element from an overcurrent, the overcurrent protection arrangement including an overcurrent protection device designed for detecting the overcurrent of a current through the electric element to be protected via the overcurrent protection device in such a way that the current through the element to be protected does not exceed an upper current limit.