Abstract: The invention relates to a diagnostic method for multiple-stage excess voltage protection apparatuses that include at least one gas discharge distance between an input and a reference potential as a first stage, at least one diode path between an output and the reference potential as a second stage, and at least one decoupling inductance interposed between the input and the output. The diagnostic method is characterized in that a secondary voltage applied to a secondary inductance, which is actively connected, inductively, to the decoupling inductance, is measured and evaluated with a view to excess voltage events in the excess voltage protection apparatus. The invention also relates to a two-stage excess voltage protection apparatus.

Abstract: An apparatus for preventing an electric overstress in an electronic device, which is capable of protecting the electronic device from the electric overstress is provided. The apparatus includes an interface unit for connecting the electronic device to an external device, includes an electric power terminal which is included in the interface unit and includes a first electric power terminal and a second electric power terminal which are electrically separated, and an electric overstress preventing unit connected with the first and second electric power terminals.

Abstract: A driver circuit and a diagnostic method are provided. The driver circuit includes a first voltage driver, a second voltage driver, and a microprocessor. The microprocessor generates a first pulse width modulated signal to induce the first voltage driver to output a second pulse width modulated signal to energize a contactor coil. The microprocessor sets a first diagnostic flag equal to a first value if a first filtered voltage value is greater than a first threshold value. The microprocessor sets a second diagnostic flag equal to a second value if a second filtered voltage value is greater than a second threshold value. The microprocessor stops generating the first pulse width modulated signal to de-energize the contactor coil if the first and second diagnostic flags are set equal to the first and second values, respectively.

Abstract: Disclosed is an overvoltage protection circuit which includes a first terminal through which a first voltage is supplied to an internal circuit; a second terminal through which a second voltage is supplied; a rectifier having an input end connected to the first terminal and having an output end; and first-stage to n-th-stage switching elements which are connected in parallel to one another. The first-stage to n-th-stage switching elements have first to n-th controlling ends, respectively. Each of the switching elements has first and second controlled ends connected to the first terminal and the second terminal, respectively. The rectifier is configured to output a control voltage from the output end thereby to cause the first-stage to n-th-stage switching elements to be turned on, in response to receipt of an overvoltage from the first terminal.

Abstract: According to one embodiment, there is provided a protection relay. The protection relay includes an input circuit that detects a state of an external device according to whether or not an external input voltage is larger than a preset threshold voltage. The input circuit includes switching unit that is made conductive by a divided voltage obtained by voltage-dividing resistors that divide the external input voltage when the external input voltage is higher than or equal to the threshold voltage, and a photocoupler that is operated by a constant current of a constant current output circuit supplying a constant current and outputs an operation signal to the operation unit when the switching unit is made conductive.

Abstract: The present invention provides an integrated circuit having a better ESD protection capability and capable of reducing a circuit layout area. The integrated circuit comprises: an internal circuit, a first pad, and at least a first impedance matching unit. The first impedance matching unit is coupled between the internal circuit and the first pad, and the first impedance matching unit comprises: a first switch unit and a first resistance unit. The first switch unit is coupled to the internal circuit, and the first resistance unit is coupled between the first switch unit and the first pad, wherein the first resistance unit has a first terminal and a second terminal. The first terminal is directly electrically connected to the first pad and the second terminal is coupled to the first switch unit.

Abstract: A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.

Abstract: A surge arrestor includes at least one arrestor element, and a disconnecting device for disconnecting the arrestor element from the grid. The disconnecting device includes a thermal disconnect point that is incorporated into the electrical connection path within the arrestor. A moving conductor section or a moving conductive bridge is connected to the arrestor element by way of the disconnect point. A conducting element is disposed in or at the end of the path of motion of the conductor section or of the bridge, the conducting element coming into contact with the conductor section or the bridge when the disconnecting device is triggered. A moving insulation part penetrates into the path of motion of the conductor section or of the bridge directly prior to or upon reaching a short circuit state.

Abstract: The semiconductor device is provided. The semiconductor device includes a substrate, an electrostatic discharge layer disposed on the substrate and including a plurality of electrostatic discharge circuits, at least one semiconductor chip stacked on the electrostatic discharge layer, and a plurality of vertical electrical connections which pass through the at least one semiconductor chip and the electrostatic discharge layer to connect the at least one semiconductor chip to the semiconductor substrate. The vertical electrical connections are connected to the electrostatic discharge circuits, respectively.

Abstract: An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other.

Abstract: A fault current limiter includes a rectifier having AC terminals and direct current (DC) terminals, the AC terminals to be coupled to an AC power source and a load. The fault current limiter further includes a DC diode coupled in parallel across the DC terminals of the rectifier and a DC reactor coupled to the DC diode. When an AC current drawn from the AC power source is less than a predetermined threshold, the DC diode is in a forward bias state to allow the AC current flowing to the load through the DC diode. When the AC current drawn from the AC power source is greater than or equal to the predetermined threshold, the DC diode is in a reverse bias state, forcing the AC current to flow to the load through the DC reactor.

Abstract: ESD (electrostatic discharge) protection for radio frequency (RF) couplers included in the same semiconductor package as other integrated circuits, such as integrated circuits having power amplifier (PA) circuitry, is disclosed along with related systems and methods. The disclosed embodiments provide ESD protection for RF couplers within semiconductor packages by including coupler ESD circuitry within an integrated circuit within the semiconductor package and coupling the connection ports of the RF coupler to this coupler ESD circuitry. Further, this coupler ESD circuitry can be implemented using two sets of serially connected diodes so that the signal connected to the coupler ESD circuitry can swing around ground without being clipped by the ESD circuitry. Still further, the ESD diodes can be formed in deep N well structures to improve isolation and to reduce parasitic capacitance associated with the ESD diodes.

Abstract: A load driving device according to an exemplary aspect of the present invention includes: an output transistor coupled between a first power supply line and an output terminal, the output terminal being configured to be coupled with a load; a protection transistor that is provided between a gate of the output transistor and a second power supply line, and brings the output transistor into a conduction state when a polarity of a power supply coupled between the first power supply line and the second power supply line is reversed; and a back gate control circuit that controls the second power supply line and a back gate of the protection transistor to be brought into a conduction state in a standby mode when the polarity of the power supply is normal.

Abstract: In one general aspect, an apparatus can include an input terminal and an overvoltage protection device coupled to the input terminal and configured to receive energy via the input terminal. The overvoltage protection device can have a breakdown voltage at an ambient temperature less than a target maximum operating voltage of a source configured to be received at the input terminal. The apparatus can also include an output terminal coupled to the overvoltage protection device and a load.

Abstract: By directly connecting, ballast to an emitter electrode of an ion generator (e.g., a corona-discharge device), a rapid and self-corrective reduction in emitter-to-collector voltage may be provided responsive to an increase in current characteristic of incipient sparking discharge. Voltage levels in the emitter-to-collector gap can be rapidly reduced based on voltage drop across the ballast that, while negligible under nominal ion current conditions, transiently increases in the event of a sparking discharge. As a result, the portion of supply voltage (typically multi-KV supply voltage) across the emitter-to-collector gap is transiently reduced to levels below a current breakdown voltage and, indeed, field intensity proximate to the emitter is transiently reduced below levels otherwise necessary to sustain ion generation.

Abstract: An output over-voltage protection circuit for power factor correction, which includes a chip external compensation network, a chip external resistor divider network, a static over-voltage detection circuit, a dynamic over-voltage detection circuit and a compare circuit; The chip external compensation network is connected between the chip external resistor divider network and the dynamic over-voltage detection circuit, the chip external compensation network converts the dynamic over-voltage signal conversion to the dynamic current signal and conveys it to the dynamic over-voltage detection circuit, the dynamic over-voltage detection circuit detects the dynamic current signal and ultimately produces the dynamic over-voltage signal (DYOVP); The dynamic over-voltage signal (DYOVP) is inputted into the compare circuit, which converts the dynamic over-voltage signal (DYOVP) into a voltage compared with a reference voltage and outputs a over-voltage control signal (OVP), so as to achieve a dynamic over-voltage prote

Abstract: Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.

Abstract: Aspects of the invention provide for qualifying a new meter with specific power supply requirements. In one embodiment, aspects of the invention include a system, including: an electric meter having a housing; and a voltage-modifying device connected to the electric meter for modifying a received voltage, such that the electric meter operates in accordance with a predetermined power supply requirement, wherein the voltage-modifying device is located within the electric meter housing or external to the electric meter housing.

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Abstract: Methods and apparatus to clamp overvoltages for inductive power transfer systems are described herein. An example overvoltage protection circuit is described, including a first terminal configured to receive an alternating current signal for conversion to a second signal, a capacitor, a first switch configured to selectively electrically couple the capacitor to the first terminal based on an overvoltage detection signal to reduce an overvoltage on the second signal, and an overvoltage detector. The example overvoltage detector is configured to determine a signal level of the second signal and, in response to determining that the signal level of the second signal is greater than a threshold, to output the overvoltage detection signal to cause the switch to electrically couple the capacitor between the first terminal and a second terminal.

Abstract: A method, device, and system for mitigating the effect of a power spike on a protective device. The device can receive an input signal and determine whether the input signal exceeds a threshold value. If so, the device simultaneously starts an initial time period and starts a latch time period, where the latch time period is greater than the initial time period. During the initial time period, the device replaces the input signal with a set value signal. After the initial time period ends and during the remainder of the latch time period, the device prevents the input signal from being replaced by the set value signal. If, during the remainder of the latch time period, the input signal exceeds the threshold value, a trip signal may be generated by a protective device.

Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

Abstract: A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

Abstract: A power supply system for a display panel includes a power supply regulator that regulates a power supply voltage of a display driver of a power supply circuit connected to the display panel, and a protection circuit that protects the display driver against an overvoltage.

Abstract: A voltage surge protection device for protection of a high voltage device includes a varistor having a first part and a second part separated by varistor material. The voltage surge protection device further includes an expandable member arranged to act on a movable electrical contact for short-circuiting the voltage surge protection device upon a threshold voltage being applied between the first part and the second part of the varistor. A high voltage circuit breakers includes one or more semiconductor devices connected in series and the voltage surge protection device connected in parallel thereto.

Abstract: A protective circuit compares at least two different signals and asserts a control node toward respective logic states accordingly. At least one of the signals is derived from a voltage on a power rail within a computer or other device. A switching element passes or isolates an enable signal based on the logic state of the control node, enabling or preventing operation of a power supply, accordingly. Central processing units (CPUs) or other elements are protected against electrically caused damage in the event that a fault is detected by the protective circuit.

Abstract: Systems and methods for overvoltage protection are disclosed. According to one illustrative implementation, an overvoltage protection device is provided having one or more overvoltage protection elements and a measuring device for monitoring the overvoltage protection elements. Further, the measuring device may include an evaluation device, which is designed to count pulse-like overvoltage events which are arrested by the overvoltage protection element, wherein the evaluation device is connected to the overvoltage protection element via a light-measuring device and/or a device for identifying a current flow.

Abstract: Various exemplary embodiments relate to a current driver for controlling a safety control device, including: a clamp circuit connected to a first output configured to clamp the voltage at the first output to a clamp voltage value, wherein the first output is configured to be connected to a high voltage switch; a plurality of medium voltage switches; a plurality of switch drivers, wherein each switch driver is connected to one of the medium voltage switches; a plurality of second outputs wherein each of the plurality of second outputs are configured to be connected across one of a plurality of loads; and a controller configured to control the high voltage switch.

Abstract: An ESD protection circuit for an RF semiconductor device includes an RF input pad configured to receive an RF input signal having an RF operating frequency for the RF semiconductor device. A first ESD block is coupled between an intermediate node and the first power supply voltage terminal, to direct an ESD pulse of a first polarity toward the first power supply voltage terminal. A second ESD block is coupled between the intermediate node and the second power supply voltage terminal, to direct an ESD pulse of a second, opposite polarity toward the second power supply voltage terminal. A resonance circuit is coupled between the RF input pad and the intermediate node. The resonance circuit is configured to present a greater impedance to the RF input signal having the RF operating frequency than to the ESD pulses.

Abstract: An electrical protection circuitry for a docking station base of a hand held meter and method thereof are disclosed. In the event of a short circuit at a meter interface connector, the protection circuitry removes power at the meter interface connector. Similarly, in the event of an applied voltage outside a specified operating range of the base, the protection circuitry removes power to the meter interface connector. These conditions of the electrical system of the base are monitored regardless whether the meter or the meter's battery is electrically connected to the base. The protection circuitry also provides a visual indication in the event of either the over current and under/over voltage conditions. Additionally, the base is designed to prevent liquid from pooling inside a pocket used to cradle and hold the meter in the base through the use of a drain located at the lowest point in the pocket.

Abstract: An overvoltage protection method for backlight driver includes: providing an LCD device having 2D and 3D modes, comprising a backlight driver comprising a constant current supplying chip and a dimming control coupled to the constant current supplying chip, the constant current supply chip applying a first overvoltage protection level and a second overvoltage protection level as a overvoltage protection level; detecting a signal of the dimming control by using the constant current flow supplying chip, and applying the first overvoltage protection level as the overvoltage protection level based on the signal of the dimming control when the LCD device is in the 2D mode; and detecting the signal of the dimming control by using the constant current flow supplying chip, and applying the second overvoltage protection level as the overvoltage protection level based on the signal of the dimming control when the LCD device is in the 3D mode.

Abstract: A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.

Abstract: An improved electronic component is described. The electronic component has a capacitor with first planer internal electrodes in electrical contact with a first termination and second planer internal electrodes in electrical contact with a second termination. A dielectric is between the first planer electrodes and the second planer internal electrodes. The electronic component further comprises at least one of: an inductor comprising a conductive trace wherein said conductive trace is between the first termination and a third termination; and an overvoltage protection component comprising: a third internal electrode contained within the dielectric and wherein the third internal electrode is electrically connected to the first termination; a fourth internal electrode contained within the ceramic and electrically connected to a fourth termination; and a gap between the third internal electrode and the fourth internal electrode.

Abstract: Disclosed include a control circuit adapted for a power controller powered by an operation voltage. When the operation voltage exceeds an over-voltage reference, the power controller stops power conversion provided by a power converter. The control circuit comprises a slope detector detecting a variation slope of the operation voltage. When the variation slope exceeds a drop rate, the slope detector recovers the power conversion. When the power conversion is recovered the power controller compares the operation voltage with the over-voltage reference.

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Abstract: A control circuit with protection circuit for power supply according to the present invention comprises a peak-detection circuit and a protection circuit. The peak-detection circuit detects an AC input voltage and generates a peak-detection signal. The protection circuit comprises an over-voltage protection circuit. The over-voltage protection circuit generates an over-voltage protection signal in response to the peak-detection signal. The protection circuit generates a reset signal to reduce the output of the power supply in response to the over-voltage protection signal. The present invention can protect the power supply in response to the AC input voltage effectively through the peak-detection circuit.

Abstract: Certain embodiments of the invention may include systems, methods and apparatus for voltage clamp circuits. According to an example embodiment of the invention, a voltage clamp circuit may include a first circuit portion electrically coupled to the output of at least one power source. The first circuit portion comprises a power semiconductor device having a first, second and a third node and one or more zener diodes electrically coupled to the first or the second node of the power semiconductor device. The voltage clamp circuit may further include a second circuit portion in electrical communication with the first circuit portion, where the second circuit portion comprises a resistor, a capacitor and a directional device, and where the second circuit portion connects to the one or more zener diodes to reduce peak voltage output between the second and the third node of the power semiconductor device.

Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.

Abstract: A semiconductor integrated circuit that is efficiently reduced in a noise level is offered. P-channel type MOS transistors M1 and M2 serving as differential input transistors have a thin gate oxide film in order to reduce the noise level. A protection circuit to protect the P-channel type MOS transistors M1 and M2 from overvoltage is formed including P-channel type MOS transistors M3 and M4. The P-channel type MOS transistor M3 is a first protection transistor to protect the P-channel type MOS transistor M1 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M1. The P-channel type MOS transistor M4 is a second protection transistor to protect the P-channel type MOS transistor M2 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M2.

Abstract: Included are: a circuit-specific printed circuit board to be a circuit board that generates a power supply voltage; a first diode that is connected in antiparallel with the transistor and is configured so as to be capable of passing a current through a path to circumvent the transistor; a second diode that is connected in series to the transistor and prevents a current flow through a parasitic diode formed on the transistor; a protection circuit that is connected in parallel with the second diode to protect the second diode from a high voltage breakdown, and is formed on a substrate different from the circuit-specific printed circuit board; and a cooling unit that is joined to the protection circuit outside the circuit-specific printed circuit board and cools the protection circuit.

Abstract: A TSV bidirectional repair circuit of a semiconductor apparatus is provided. The bidirectional repair circuit includes a first and a second bidirectional switches and at least two transmission path modules. The first and the second bidirectional switches determine whether to transmit an input signal of a first chip or a second chip to each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether short-circuit on the corresponding TSV and a silicon substrate is present according to the input signal and the corresponding TSV to produce a short-circuit detection output signal.

Abstract: A power unit (e.g., inverter module) includes a housing and a switch attached to the housing. The switch may be configured to be electrically coupled to a remotely-mounted drive circuit through two or more wire leads. The power unit also includes a clamping circuit electrically coupled to terminals of the switch and in parallel with the switch. The clamping circuit may be disposed inside the housing or on an outer surface of the housing, and is configured to limit a voltage across the switch.

Abstract: An apparatus and method is disclosed for providing an electrostatic discharge protection circuit for compound semiconductor devices and circuits. The electrostatic discharge protection circuit comprises a first terminal and a second terminal. The electrostatic discharge protection circuit further comprises a transistor shunt element that is operably coupled between the first terminal and the second terminal; the transistor shunt element is capable of providing a bi-directional discharge path between the first terminal and the second terminal. The electrostatic discharge protection circuit further comprises a shut-off element that is operably coupled with the second terminal; the shut-off element is capable of keeping the transistor shunt element turned-off.

Abstract: A circuit with an electro-static discharge clamp coupled to a first power source and second power source. The electro-static discharge clamp includes an NMOS stack and an electro-static discharge detector. The NMOS stack has a first NMOS transistor with gate node ng1 and a second NMOS transistor with gate node ng2. The electro-static discharge detector is configured to control the NMOS stack, and may include three switches. A first switch is configured to switch the gate node ng1 to the second power source. A second switch is configured to switch the gate node ng1 to the gate node ng2. A third switch is configured to switch the gate node ng1 to the ground.

Abstract: A regulating system for an insulated gate bipolar transistor (IGBT) includes a clamping circuit coupled to the IGBT. The IGBT is coupled to a gate driver circuit. The regulating system also includes a feedback channel coupled to the clamping circuit. The feedback channel is configured to transmit signals representative of a conduction state of said clamping circuit. The regulating system further includes at least one gate driver controller coupled to the feedback channel and the gate driver circuit. The gate drive controller is configured to regulate temporal periodicities of the IGBT in an on-condition and an off-condition.

Abstract: A suppression system provides more effective protection for communication stations with distributed radio and power systems. The suppression system provides surge protection both locally close to the radio station building where the power plant and telecommunication equipment are located and remotely next to the radios and antennas located outside of the building on the communication tower. Local and remote suppression units may include monitor circuitry that monitor remote and local DC voltage levels and alarm conditions. The alarm conditions may include over-voltage protection failures, intrusions, and/or water infiltration. Displays on both the local and remote suppression units identify the voltage levels and alarm conditions.

Abstract: An overvoltage protection circuit is based on replacing the bias resistor in a conventional overvoltage protection circuit with a self-biased latch. The new circuit automatically survives both overvoltage and overcurrent events.

Abstract: An electrical power distribution system for an aircraft comprises a power source electrically connected to an electrical load and at least one circuit interruption device for interrupting current in the power distribution system. A distinguishing device is connected to the system for distinguishing a transient electrical event in the system from a steady-state level of electrical activity in the system, wherein the transient electrical event induces a potential difference across all or part of the distinguishing device. The circuit interruption device is operable to interrupt current flowing through the power distribution system if the potential difference across the distinguishing device exceeds a threshold voltage.

Abstract: Disclosed herein is a common mode filter. The common mode filter includes a main body that includes a coil electrode, first and second external electrodes connected with both ends of the coil electrode, respectively, and a ground electrode, and an electro static discharge (ESD) protection layer that includes a switching member formed therein, and is provided on any one surface of the main body. Here, one end of the coil electrode is connected with the second external electrode, the other end thereof is connected with the first external electrode through the switching member, and the switching member is disconnected from the coil electrode in accordance with a switching operation when a surge current is applied and connected with the ground electrode. Therefore, it is possible to protect the common mode filter from a surge current by ESD.

Abstract: A power supply arranged to charge a smoothing capacitance via a resistive element for soft-starting in the event that one or more conditions for normal operation are not complied with is arranged to detect that a voltage across at least part of the smoothing capacitance exceeds an excess voltage threshold and, responsive to the detecting, interrupt charging of the smoothing capacitance via the resistive element for soft-starting.