Abstract: The probability of soft-programming of the reference cells of a FLASH-EPROM memory may be excluded by having a decoupling transistor of a type of conductivity opposite to that of the cells functionally connected between the gate of each reference cell and the respective row line. Moreover the elimination of the electrical stresses to which the reference cells are subjected during the repeated programming cycles of the memory cells, increases the stability of the respective reference values of threshold and current level provided by the reference cells, thus increasing the reliability of the device.

Abstract: The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.

Abstract: A semiconductor integrated circuit includes "n" cascaded inverters IV.sub.j ("j"="1" to "n") formed of MOS transistors. The size of an input side MOS transistor and the size of an output side MOS transistor of each inverter are determined so that an input capacitance CG.sub.j and an output load capacitance CL.sub.j of each inverter satisfy the following relationships: F.sub.j =(CG.sub.(j+1) +CL.sub.j)/CG.sub.j and F.sub.(j+1) =F.sub.j -(CL.sub.j /CG.sub.j).

Abstract: A non-volatile semiconductor memory cell comprises a P-type semiconductor substrate (5) and N+ diffusion regions (6) spaced apart from each other on the principal surface of a P-type substrate (5). Each N+ diffusion region (6) can be used as source or drain of a transistor. Between any two adjacent N+ diffusion regions and under the gates is located the channel region (7). A control Y gate (8) is formed on an insulation layer above a portion of the channel and extends over a portion of N+ diffusion region (6). A floating gate (9) is formed on an insulation layer above the control Y gate (8) and the rest of the channel, and extends over a portion of another N+ diffusion region (6). A control X gate (10) is formed on an insulation layer above the floating gate (9) and N+ diffusion regions (6).

Abstract: A memory devices having NAND type cells as storage elements is disclosed. The amplifier prevents the error from occurring and improves the sensing speed by getting the column line and the reference line approximately the same current level for a while, after the equalizing signal was just turned into row level, in order that the potentials of the column line and the reference line normally come out without time delay. And, the sensing amplifier comprises a reference cell string selecting part 203 connected to a reference line and to selection lines 1 to N, a reference cell part 204 connected to row lines 1 to N and to the reference cell string selecting part 203, a column dummy cell part 205 connected to a column line and to dummy lines 1 and 2, a reference dummy cell part 206 connected to the reference line and to the dummy lines 1 and 2.

Abstract: A semiconductor read only memory of this invention includes a plurality of word lines disposed in parallel. The read only memory has a plurality of units.

Abstract: A memory circuit incorporating a current-mirror type amplifier which directly amplifies a varied potential of a pair of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify a minimal difference (100 mV) of potential between these bit lines. Data signal outputted from the current-mirror type amplifier is then transmitted to a read-only signal line. As a result, data is quickly read out before a built-in sense amplifier completes amplification, thus quickly achieving an accessing operation at extremely fast speed.

Abstract: A memory cell constructed in accordance with the present invention includes a node operable to present an electrical level representing a first state or a second state. Further included is a first switching device having a first terminal connected to the node such that if the first switching device were to close, the electrical level at the node would be connected to a second terminal of the first switching device. Additionally, second and third switching devices are provided both having first and second terminals and both operable to switch as a function of the state at the node. Finally, a single control switching device is provided in association with the second and third switching devices wherein a control signal switches the control switching device such that the state at the node may be determined by connecting to the first terminals of the second and third switching devices.

Abstract: A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

Abstract: A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor.

Abstract: A are a semiconductor memory device excellent memory characteristics of which can be obtained without deteriorating a characteristic of a transistor for use in a peripheral circuit even when a memory cell array region and a peripheral circuit region differ from each other in wiring pattern density and a manufacturing method therefor. The semiconductor memory device includes a dummy pattern formed between and at predetermined distance from gate electrodes of a transfer gate transistor in the peripheral circuit region.

Abstract: In a pseudo-static random access memory of the invention, refresh operations are conducted in a normal mode and a self-refresh mode. The memory includes a plurality of bit-line pairs each having two bit lines, a precharge voltage generating circuit for precharging the plurality of bit-line pairs to a first potential level during a precharge period in the normal mode, the circuit being electrically connected to the plurality of bit-line pairs during the precharge period in the normal mode; and bit line discharge circuit for discharging the bit-line pairs during a precharge period in the self-refresh mode, thereby decreasing the potential level of the bit-line pairs to a second potential level which is below the first potential level.

Abstract: For providing a semiconductor memory device that includes a plurality of cross-point memory cells each having a fine device structure and a high capacitance, a bit line is formed on an insulating substrate, and a word line is disposed above the substrate so as to cross the bit line. A MOS transistor with a vertical structure, whose gate electrode is used as the word line, is provided on the bit line. A MIM (Metal-Insulator-Metal) capacitor is provided on the MOS transistor.

Abstract: A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.

Abstract: The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on.

Abstract: The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. It includes a decoding scheme wherein the memory chip has a row address bit which is used for the row decoding also participating in the bit line decoding process. The invention comprises only one row decoder providing the required voltages to the read word lines during reading, programming and page and flash erase operations. The invention expands the feature of the reduction in programming time of non-volatile memories from a single cell to the entire row of cells that program using hot electrons. The invention reduces the diffusion isolation spacing between bit-lines by using shield transistors. A current mirror with multiple branches is used as part of a power switch to control the supply of 5 or 12 volts to various circuit block of the EEPROM chip.

Abstract: A memory cell has a thin film memory transistor and a thin film selective transistor. The thin film memory transistor has a charge trapping structure and a positive-negative-charge occurrence structure. The charge trapping structure includes a first thin film semiconductor layer, an insulating memory gate layer formed on the first thin film semiconductor layer, and a memory gate electrode. The positive-negative-charge occurrence structure includes an impurity high density layer with a portion facing the memory gate electrode. The thin film selective transistor is coupled to the thin film memory transistor in a serial form and has an only n-channel occurrence structure which includes a second thin film semiconductor layer, an insulating selective gate layer formed on the second thin film semiconductor layer and being thicker than the insulating memory gate layer, and a selective gate electrode formed on said insulating selective gate layer.

Abstract: A non-volatile memory cell includes heavily doped source 12 and drain 14 regions separated by a channel region 16. The source 12 and drain 14 are isolated from floating gate 18 and control gate 22 by thick oxide 36. A floating gate 18 is formed over and insulated from a portion of said channel region 16 adjacent to the source 12 and a control gate 22 is formed over and insulated from the floating gate 18 and the remaining portion of the channel region 16. The cell is programmed by applying a nearly reference voltage V.sub.s to the source region 12 and applying a drain voltage V.sub.D to the drain region 14. A gate voltage V.sub.G is applied to the control gate 22 such that an inversion region 15 is formed in the remaining portion of said channel region 16 such that the floating gate 18 is charged up by hot electron injection on the side away from the source junction. The source junction is self aligned to floating gate and is graded for efficient erase. Other key features and methods are also disclosed.

Abstract: A memory device is provided that includes a plurality of floating gate memory cells arranged in an array, where each memory cell includes a control gate, a drain and a source. A decoder is provided that applies a first erase voltage to the control gates of selected floating gate memory cells of the array to prevent erasure of the selected floating gate memory cells and a second erase voltage to the control gates of the remaining floating gate memory cells of the array to permit erasure of the remaining floating gate memory cells in a sector erase mode of operation. The decoder is also preferably capable of supplying the second erase voltage to the control gates of each of the floating gate memory cells in a bulk erase mode of operation.

Abstract: Disclosed is a TFT for a semiconductor memory device and the fabricating method thereof, comprising a first conductive layer formed on a first insulating layer of a semiconductor substrate and doped with a first conductive type impurity, a second insulating layer formed on the first conductive layer, a contact hole formed in the second insulating layer above the first conductive layer, a semiconductor layer formed on a predetermined portion of the first conductive layer exposed in the contact hole, the inner walls of the contact hole and the second insulating layer, a thin-film gate insulating layer covering the semiconductor layer, a second conductive layer formed on a gate insulating layer to overlap the contact hole and its periphery, a first impurity region formed while upwardly dispersing the impurity of the first conductive layer into the semiconductor layer in contact with the first conductive layer of the contact hole, a second impurity region placed in the semiconductor layer of the second insulating

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: By provided a dummy region, having a shape similar to and being formed in the same process as, the active regions having transistors that constitute memory cells formed therein, between two transistors, the spacing between the active region and the dummy region is made to be equal to the spacing between other transistors. By reducing the nonuniformity in the gate width of the transistors within the memory cell array regions with the above arrangement, it is possible to prevent the reduction of the transistor performance, and to prevent a performance reduction and the generation of malfunctions due to a delay in the data output time of the semiconductor memory device.

Abstract: According to this invention, a semiconductor non-volatile memory is formed as follows. In an EPROM memory array consisting of MIS transistors arranged in a matrix form, a first bit line consisting of polysilicon is connected to a drain region through a first contact formed in the drain region, a second bit line formed on the first bit line through an interlayer insulator by a metal film is connected to the first bit line by a second contact, and the second contact is formed on each source line of the memory array.

Abstract: A MOS fuse with programmable tunnel oxide breakdown is made up of a tunnel oxide EEPROM cell, which can be programmed/erased by a programming/erasure voltage having a slow-rising edge, while the tunnel oxide can be subjected to breakdown, when desired, by switching over to a programming/erasure voltage having a steep edge. Such fuse can be used in all MOS integrated circuits and particularly in memory card type applications.

Abstract: A method which can operate a semiconductor memory device having a volatile memory and a non-volatile memory without lowering the retention characteristic of the non-volatile memory is described. The volatile memory includes a MOS transistor, and a capacitor, one electrode of which is connected to the source of the MOS transistor. The non-volatile memory includes a floating gate transistor. The semiconductor memory device further has a switch connected between the source of the MOS transistor and the drain of the floating gate transistor. The control gate of the floating gate transistor is connected to the source of the MOS transistor. When the switch is off and the volatile memory to be operated, a voltage which is substantially one half of that of a power source voltage with respect to the ground level is applied to the source of the floating gate transistor.

Abstract: A semiconductor memory device has an array of memory cells which are accessed by digit and word lines. The device includes a digit line controller for selecting a digit line to access a preselected memory cell and for applying an activation voltage to the selected digit line. The device also has an isolation voltage generator for generating an isolation voltage. An isolating circuit then transfers the isolation voltage to digit lines immediately adjacent to the selected digit line to isolate neighboring memory cells from the memory cell being accessed. This isolation voltage effectively reduces or eliminates parasitic leakage between neighboring memory cells in high voltage and highly integrated memories.

Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.

Abstract: A dynamic random access memory device in the folded bit line configuration comprises first sense amplifier circuits located on one side of sets of bit lines associated with first transfer units, second sense amplifier circuits located on the other side of the sets of bit lines asoicated with second transfer units, and sets of word lines, and each sets of bit lines and each set of word lines respectively consist of first to third bit lines and first to third word lines for providing nine addressable locations, wherein memory cells are provided at six addressable locations selected from the nine addressable locations, and each set of bit lines respectively propagate two data bits read out from two of the six memory cells to the first and second sense amplifier circuits, thereby increasing the number of memory cells in a unit area.

Abstract: The invention provides a semiconductor memory which is minimized in leak current and has a high data holding performance. The semiconductor memory comprises a memory cell including a flip-flop in which a thin film transistor is employed as a load element. The thin film transistor has a channel region which is bent at an intermediate portion thereof.

Abstract: A static type RAM performs latch of supplied address signals by rise or fall edge of clock pulses supplied from the outside, and performs the write operation continuously while write control signals are activated, and substantially opens a data output terminal in the period. Also an address buffer of the RAM is activated by a definite time required for the state that the supplied address signals are latched by timing pulses formed based on the clock pulses.

Abstract: A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed.

Abstract: A semiconductor non-volatile memory device, has plural data storage parts which are connected in series between the source region and drain region. In such a constitution, when integrating the semiconductors, the relative area occupied by the selection gate, separation gate, source region and drain region of the area of the data storage parts may be drastically reduced, and the degree of integration of the semiconductor non-volatile memory device can be dramatically enhanced. The device also allows for setting the semiconductor substrate in a depletion state by sequentially varying the gate potential of the plural data storage parts and transferring the electric charges sequentially. By this transferring of electric charges, data write errors may be prevented.

Abstract: An electrically programmable memory array including a plurality of memory cells for storing data aligned in rows and columns, a plurality of word lines each connected to the gate terminals of the memory cells in a particular row, a plurality of bit lines each connected to the drain terminals of the memory cells aligned in a particular column, and a plurality of source conductors each electrically connected only to the source terminals of the memory cells in a particular row. This architecture lends itself to a finer granularity of small blocks without extra memory cell area.

Abstract: An improved method of programming EEPROM cells in a memory array, wherein a cell page can be programmed and erased without disturbing other cell pages in the array, and further, an individual cell can be reprogrammed without disturbing other cells in the array. The user can selectively erase and program cells in the array by controlling the operating conditions of the word lines, bit lines, and Vss lines coupled to those cells according to the method of the present invention.

Abstract: A circuit and method for rapid removal of drain-column programming voltages from drain-column lines of a memory array. The circuit includes a resistor/transistor connected between a supply voltage and a common node, the resistor/transistor being enabled by a program enable signal. During the discharge operation, the source-drain paths of a driver transistors of the array connect column lines to reference potential. The gates of the driver transistors are coupled to the common node. An enabling transistor has a source-drain path connecting reference potential to the common node and has a gate connected to the program enable signal. The circuit includes at least one inverter, an OR circuit, and a bypass transistor. The bypass transistor has a source-drain path connected between the supply voltage and the common node and a gate coupled to the common node through the inverter and the OR circuit.

Abstract: A voltage sensing circuit receives an input voltage signal and generates an output voltage signal. The circuit has a sensing node. A first P-type MOS transistor is connected having one of its ends to receive the input voltage signal with the other end connected to the sensing node to provide a sensing signal. A first voltage source is connected to the gate of the first P-type transistor. A voltage dropping circuit receives the input voltage signal and generates a first drop voltage signal lower than the input voltage signal. A second P-type MOS transistor has one end connected to receive the first drop voltage signal. The first voltage source is also connected to the gate of the second P-type MOS transistor. A third N-type MOS transistor has a gate connected to the other end of the second P-type MOS transistor. The third N-type MOS transistor has one of its ends connected to the sensing node. A second voltage source is connected to the other end of the third N-type MOS transistor.

Abstract: A compact SRAM memory cell employs two invertor areas longitudinally offset along a longitudinal axis and having transistor gates interdigitated, with a gate electrode of one invertor extending perpendicular to the longitudinal axis to make contact with the output node of the other invertor. Adjacent cells are related by a 180.degree. rotation through a transverse edge and a reflection through a longitudinal edge.

Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.

Abstract: One embodiment of the present invention is a one transistor DRAM cell having enhanced capacitance and minimized soft error rate by providing an ungrounded cell capacitor plate which is insulated from the substrate. The structure includes a vertical transistor on the sides of a vertical depression or trench in a substrate. In the bottom of the trench, a memory cell capacitor is fabricated. This capacitor includes a conductive polycrystalline silicon post through the middle of the capacitor, thereby increasing the surface area of the capacitor plates. This increases the capacitance of the memory cell capacitor.The ungrounded plate of the memory cell capacitor is fabricated in the trench and is insulated from the substrate. This ungrounded plate is connected to the vertical transistor via a polycrystalline silicone plug. Thus this embodiment of the present invention reduces soft error rate by providing a fully insulated ungrounded memory cell capacitor plate.

Abstract: An EEPROM memory cell having sidewall floating gates (28, 28a, 28b) is disclosed. Sidewall floating gates (28, 28a, 28b) are formed on sidewalls (30, 32) of a central block (22). Spaced apart bit lines (36, 36a, 36b) are formed to serve as memory cell sources and drains. Sidewall floating gates (28a, 28b) are capable of being programmed independently of one another. When control gate (18) is actuated and either bit line (36a) or bit line (36b) is used to read the device, four separate memory states may be identified depending on whether either, neither or both of the sidewall floating gates (28a, 28b) have been programmed.

Abstract: A static memory in which polysilicon thin film transistors serve as load elements in a memory cell, and the gate electrodes of the polysilicon thin film transistors are formed of diffusion regions. In the static memory, high quality uniform TFTS are formed, and the oxidation films of the TFTs can be thin, without using a complex manufacturing technique.

Abstract: An EPROM and a method of testing the former, in which a defective memory cell caused by defects in the insulating films between a substrate and a floating gate and between the floating gate and a control gate can be tested without writing any data in the individual memory cells by holding data lines to a low potential and word lines fed with a voltage.

Abstract: A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array.

Abstract: A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, a first peripheral circuit irregularly provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.

Abstract: A non-volatile storage cell has (a) storage points which are insulated from one another and each having a stack of gates formed, in order, by a first insulant in contact with the substrate, a floating gate, a second insulant and a control gate, a source and a drain formed in substrate on either side of the stack and a channel, whose length is oriented in a direction (x) and (b) conductor lines serving to apply electric signals to the stacks of gates and the drains, the second insulant having, in a plane perpendicular to the surface of the substrate and containing the first direction (x), the shape of an inverted U within which is located the entire floating gate, the control gate also being shaped like an inverted U, without projection and within which is located the entire second insulant.

Abstract: A memory cell is disclosed which comprises a filament channel transistor and a ferroelectric capacitor formed on a surface of a semiconductor substrate. The transistor comprises a substantially cylindrical channel filament which is formed substantially perpendicular to the substrate surface between the surface and the capacitor. The capacitor comprises a storage layer which can be formed of a ferroelectric material such that the memory cell is nonvolatile. The storage layer may also comprise a high dielectric material such that the memory cell is operable as a dynamic random access memory cell.

Abstract: A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface area for charge storage. The second electrode is used to partially planarize the surface topology. The first electrode can also be used as the gate of a sensing transistor in a signal amplifying cell, as well as in multiport and multistate dynamic RAM cells.

Abstract: A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.

Abstract: A semiconductor memory cell includes a write row line, a read row line, a write column line, a read column line, a single MOS write transistor, and a single MOS read transistor. The write transistor has a first controlled node coupled to the write column line, a second controlled node, and a gate coupled to the write row line. The read transistor has a first controlled node coupled to the read column line, a second controlled node coupled to the read row line, and a gate coupled to the second controlled node to define a charge storage node.

Abstract: A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.