Abstract: An electrically erasable programmable read only memory (EEPROM) memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series with the source and is controlled by the transfer terminal.

Abstract: An addressable memory cell (10) which is composed of an interrupt transistor (20) of the field-effect type whose source (S) is connected to the input terminal (I) of the cell (10) and whose gate (G) is connected to a clock (H, H) and a loop (30) which includes a first inverter (31) which is connected in series with the drain (D) of the interrupt transistor (20) and whose output is connected to the output terminal (0) of the cell (10), and a second inverter (32) which is connected in series, in the loop (30), with the first inverter (31). In accordance with the invention; the cell (10) is made of gallium arsenide and the loop (30) also includes a diode (33) which is connected in the forward direction between the output of the first inventer (31) and the input of the second inverter (32), and a resistance (34) which is connected between the output of the second inverter (32) and the input of the first inverter (31).

Abstract: An integrated circuit device structure for a static random access memory includes a feature which improves soft error immunity. Each static random access memory has two storage nodes for storing data of that cell. Each of these nodes is at the connection of the drain of a pull-down transistor and the source-drain of a pass transistor which occurs in a doped region of the substrate in which the integrated circuit is formed. The soft error immunity is increased by increasing the capacitance of each of the storage nodes. This is achieved by providing only a thin insulating layer over the doped regions of the storage nodes and extending a portion of grounded, heavily-doped polysilicon over the doped regions. The ground polysilicon is then separated from the doped regions by only the thin insulating layer so there is thus substantial added capacitance to the storage nodes.

Abstract: A programmable circuit for inclusion in an integrated circuit die for encoding information identifying or otherwise relating to such die, such circuit utilizing a plurality of single bit information storage and reading bit cells, each bit cell including a MOSFET or IGFET capacitor structure as a bit storage element. A gate of the MOSFET or IGFET acts as a positive voltage plate of the capacitor, while a source and drain are both connected to ground and act as ground plates of the capacitor. Normally, an open circuit is present between the gate and the source and drain, however, when a programming high voltage is applied to the gate, the capacitor structure physically breaks down and a conduction path is formed between the gate and the source or drain. The presence or absence of this conduction path enables the MOSFET or IGFET capacitor structure to act as a binary bit.

Abstract: A memory cell is provided comprising a bistable latch (I1, I2) having first and second nodes (NODE 1, NODE 2) and a nonvolatile transistor (NV1). The control gate of the nonvolatile transistor is connected to the first node and either the source or drain is connected to the second node. A switching transistor is provided for maintaining the control gate and the substrate of the nonvolatile transistor at substantially the same potential during volatile operation of the latch, thereby reducing voltage stress which would lead to charge tunnelling to or from the floating gate. In this way, disturbance of the floating gate charge is avoided during volatile operation. The cell is particularly suited to silicon gate fabrication technology.

Abstract: In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.

Abstract: A memory cell array has a continuous diffusion region for source regions of a plurality of memory transistors; a continuous diffusion region for drain regions of the plurality of memory transistors; the both diffusion regions being formed in a substrate in parallel to each other; and word lines electrically insulated from the both diffusion regions and formed in a direction crossing the both diffusion regions; the word lines being composed of polycrystal silicon films in first and second layers and alternately arranged and electrically insulated from each other. A region of the memory transistors for ion implantation is wider than a channel region of the memory transistors. The region of the memory transistors for ion implantation is formed up to the channel region of the memory cell transistors provided by the word lines in the second layer. A thick oxide film is formed on the both diffusion regions.

Abstract: A methd of making an electrically programmable and erasable memory device having a re-crystallized floating gate is disclosed. A substrate is first defined. A first layer of dielectric material is grown over the substrate. A layer of polysilicon or amorphous silicon is then deposited over the first layer. The layer of silicon is covered with a protective material and is annealed to form recrystallized silicon. A portion of the protective material is removed to define a floating gate region. Making oxide is grown on the floating gate region. The remainder of the protective material and the recrystallized silicon thereunder is removed. A second layer of dielectric material is formed over the floating gate and over the substrate, immediately adjacent to the floating gate. A control gate is patterned and formed. Source and drain regions are then defined in the substrate.

Abstract: Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor formed in the SOI substrate and an Esaki diode is positioned on the MOS transistor. The memory device also comprises a memory cell provided with a plurality of tunnel diodes connected to one of the impurity regions constituting the FET formed in the semiconductor substrate, and another memory cell provided with an Esaki diode formed in an self-alignment by a solid phase diffusion. In manufacturing the semiconductor memory device, the MOS transistor and the Esaki diode, which collectively form a memory cell, are integratedly formed one upon the other. The MOS transistor is formed in a semiconductor substrate using an SOI structure so as to prepare a memory cell which does not include a parasitic pn-junction.

Abstract: Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Abstract: A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor 10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

Abstract: An EPROM memory cell (32) stores information in a floating gate (44) which overlies a portion of a channel between a program drain (36) and a read drain (34). A control gate (46) has a lower segment (48) which overlies the portion of the channel not covered by the floating gate (44), and has an upper portion (50) overlying the floating gate (44). During a program operation, electrons flow from the read drain (34), acting as a source, to the program drain (36), and hot electrons are stored within the floating gate (44). During a read operation, electrons flow from the programming drain (36) to the read drain (34), and the majority of hot electrons drift to the control gate (46). Since the hot electrons do not enter the floating gate (44) during read operations, a higher driving current can be used, thereby increasing the speed at which the EPROM memory cell (32) is read.

Abstract: In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Abstract: A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.

Abstract: A stacked static random access memory SRAM having a plurality of memory cells is disclosed. Individual memory cell has a portion formed in an upper active element layer in the device structure and a portion formed in a lower active element layer in the device structure separated from the upper layer by an intermediate insulating layer. A word line, a bit line and access transistors are formed in the same upper active element layer, eliminating the need for interconnecting them through the insulating layer. The elimination of the inter-layer connections helps to reduce the number of through-holes required to be made in the insulating layer. This in turn reduces the area to be occupied by the memory cell and leads to a simplified manufacturing process of the SRAM.

Abstract: A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, a storage capacitor having a storage node disposed within a given sidewall of the trench, a switching device coupled to the storage capacitor and having an elongated current carrying element disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench and a control element disposed on the sidewall of the trench between the storage capacitor and the elongated current carrying element, and an electrically conductive line disposed on the major surface of the semiconductor substrate in a direction orthogonal to the longitudinal axis of the trench and in contact with the control element of the switching device.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM which is composed of a memory cell having its high resistance load element and power source voltage line connected with the information storage node of a flip-flop circuit through a conductive layer. At the same fabrication step as that of forming the plate electrode layer of a capacity element over the conductive layer formed on the portion of the information storage node through a dielectric film, an electric field shielding film for shielding the field effect of a data line is formed over the high resistance load element through an inter-layer insulation film.

Abstract: A dynamic type semiconductor device comprises a memory cell array including a plurality of cell groups, each of the cell groups including four adjacent memory cells disposed in a point symmetry fashion, with a single contact hole formed at the center of the point symmetry to be common to the four memory cells, in which the four memory cells and bit lines are connected through the single contact hole.

Abstract: An apparatus (50) activates and drives sense amplifiers in a dynamic random access memory (DRAM) at a high speed. The sense amplifier includes a P-MOS sense amplifier (15, 16) and an n-MOS sense amplifier (18, 19). The P-MOS sense amplifier is connected to a power line (31) through a first switching element (22) to be activated while the n-MOS sense amplifier is connected to a ground line (30) through a second switching element (20) to be activated. The sense amplifier driving apparatus includes a capacitor (34) conneced between the power line and the ground line. This enables compensation for the charge and discharge currents which flow in the bit line charging and discharging operations, reduction in the bit line charging and discharging times, and suppression of the fluctuation in supply potential, improving the operating speed of the DRAM.

Abstract: An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

Abstract: A three-dimensional memory element comprises a multilayer tunnel switch portion formed by alternately stacking conductive films and insulating films, both the ends of the switch portion consisting of insulating films, a write electrode formed on the insulating film as one end of the multilayer tunnel switch portion, a read electrode formed on the insulating film as the other end of the multilayer tunnel switch portion, and charge accumulating capacitors respectively connected to the conductive films of the multilayer tunnel switch portion.

Abstract: A grooved separating region 112 having information electric charge storing capacitances C.sub.P formed on side surfaces thereof is formed to extend the region between the adjacent word line 107 in parallel with the word line 107. As a result, the grooved separating region 112 does not contact the channel region 111 of the gate transistors and does not intersect the word line 107.

Abstract: A semiconductor memory device includes a semiconductor substrate having source and drain regions each having a conduction type opposite to that of the semiconductor substrate, an insulation film formed on a main surface of the semiconductor substrate having first and second contact windows, and a gate electrode formed on the insulation film so as to be located between the source and drain regions. The semiconductor substrate has a charge barrier layer which has the same conduction type as the semiconductor substrate and which has an impurity concentration higher than that of the semiconductor substrate. The charge barrier layer is formed so that a depth (d.sub.1) of the charge barrier layer located under the gate electrode measured from the main surface of the semiconductor substrate is smaller than a depth (d.sub.2) of the charge barrier layer located under the source and drain regions measured from the main surface of the semiconductor substrate.

Abstract: A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface area for charge storage. The second electrode is used to partially planarize the surface topology. The first electrode can also be used as the gate of a sensing transistor in a signal amplifying cell, as well as in multiport and multistate dynamic RAM cells.

Abstract: A high density computer memory which utilizes a probe operating with two degrees of freedom over a memory area, the probe location altered by drive systems incorporating piezoelectric elements arranged to drive the probe parallel to the plane of the memory surface. Sensors to provide an indication of the location of the probe independent of the drive system are provided. The memory system incorporates an underlying substrate upon which is deposited one of a variety of elements or compounds chosen to effect a change in physical-chemical properties when a data bit is written on the surface. The probe is moved over the surface at a distance which produces a current from Schottky or Field effect.

Abstract: A static memory cell of the metal-insulator-semiconductor type, which can be used in the microelectronics field for producing random access memories for storing binary information. This MIS type memory cell is a random access static memory cell known under the abbreviation SRAM. A bistable flip-flop is formed by a MIS transistor and a parasitic bipolar transistor. The source and drain of the MIS transistor respectively formed by constituting the emitter and collector of the bipolar transistor. The region of the channel of the MIS transistor located between the source and drain serves as the base for the bipolar transistor. The base is completely isolated from the outside of the memory cell. The gate electrode of the MIS transistor is electrically isolated from the region of the channel. There is an addressing circuit for the flip-flop for storing binary information in the form of the absence or presence of current.

Abstract: A Dynamic Random Access Memory device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

Abstract: A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Abstract: For reduction in occupation area, there is provided a complementary field effect transistor consisting of a n-channel MIS type field effect transistor formed along a side wall of a p-type silicon substrate and a p-channel MIS type field effect transistor formed along a side wall of an n-type well in the p-type silicon substrate, and both of the side wall of the silicon substrate and the side wall of the n-type well define a groove where a conductive material is deposited to provide an interconnection between the n-type and p-type MIS type field effect transistors and another complementary field effect transistor.

Abstract: A semiconductor memory has a first insulating layer formed on one major surface of a silicon single crystal substrate having a hole portion. The hole portion is filled with a material of a first conductivity type up to the depth of the first insulating layer. A first single crystal silicon layer is formed on the first insulating layer and a diffused region of the first single crystal silicon layer is formed on the first insulating layer and on the material of a first conductivity type. Source and drain regions are formed by doping the first single crystal silicon layer with a first impurity up to high degree of concentration. A second insulating layer is then formed on the first single crystal silicon layer with a low resistive portion formed on this second insulating layer to form source and drain regions. A second single crystal silicon layer is formed along the wall surfaces of the second insulating layer and the low resistive portion.

Abstract: An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced apart from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.

Abstract: A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.

Abstract: A static random access memory cell implemented with metal Schottky field-effect transistors. The cell has first and second branches, each of the branches including: a depletion mode current limiting transistor having a drain connected to a first circuit node; a depletion mode load transistor having a drain connected to the source of the current limiting transistor and a source connected to a second circuit node; an enhancement mode active transistor having a drain connected to the second circuit node and a source connected to a third circuit node; an enhancement mode access transistor having a source connected to the second circuit node and a gate connected to the gate of the current limiting transistor; the gate of the load transistor connected to the second circuit node; the commonly connected gates of the current limiting transistor and the access transistor adapted to receive a word-line signal; and the drain of the access transistor adapted to receive a bit-line signal.

Abstract: A semiconductor memory device, including a plurality of programmable read only memory cells arranged at intersection points of a matrix formed by a plurality of word-lines and bit-lines crossing each other, independently having first column transfer gate transistors located between a programming circuit and the bit-lines to transfer a programming data signal from the programming circuit to a selected memory cell located on one of the bit-lines when the memory device is in a programming mode and second column transfer gate transistors located between a sense amplifier and the bit-lines to transfer a read out data signal from a selected memory cell located on one of the bit-lines to a sensing amplifier when the memory device is in a reading mode.

Abstract: A dynamic random access memory cell has a storage capacitor and an access transistor formed on only one sidewall of a trench etched into the face of a semiconductor bar. The storage capacitor uses the sidewall of the trench as the storage node, and uses a polysilicon plug as a common node. This polysilicon plug is part of a plate that extends along the face in the trench for a column of like cells, functioning to provide field-plate type of isolation between capacitors along the trench. The channel of the access transistor is formed in the upper part of the one sidewall of the trench, using an upper edge of the capacitor storage node as the source region of the transistor and having a buried N+ drain region on the face at the top. The capacitor areas are isolated from one another on opposite sidewalls, so an array can be laid out that has two cells per bit, to provide improved alpha particle immunity, or by using two wordlines per row a true crosspoint array is possible, providing higher density.

Abstract: A semiconductor memory including two cross-coupled driver MOS transistors respectively having source and drain regions within a semiconductor substrate and each of the drain regions being in ohmic contact with the gate electrode of the other driver MOS transistor. The gate electrodes of the driver MOS transistors are formed in a first-level polycrystalline silicon (polysilicon) layer and the two transfer MOS transistors respectively have their source and drain regions formed in portions of a second-level polysilicon layer. The driver regions are formed so as to be independently brought into ohmic contact with the respective drain regions of the driver MOS transistors, and each of the transfer MOS transistors have a gate electrode effected in a third-level polysilicon layer which also defines a word line.

Abstract: Disclosed is a nonvolatile memory cell which utilizes a tunnel window to discharge the floating gate at a location spacially displaced from the program path for the cell. Also disclosed is a process for making such a memory cell.

Abstract: A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load device may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET may be present in another wall of the trench or in a lateral orientation adjacent the trench in the semiconductor surface. Two of these multiple element trench cells may be interconnected in various configurations to form conventional static random access memory (SRAM) cells.

Abstract: A semiconductor memory device is provided with memory cells which each comprises an insulated gate type field effect transistor and a capacitor connected in series with one another and connected to bit lines. The capacitor is composed of a pair of electrodes and a dielectric film which includes a silicon nitride film existing between the pair of electrodes. One electrode of the capacitor is provided with a terminal to which a voltage is applied. The value of the applied voltage is chosen so that the voltage applied between the pair of electrodes is smaller in an absolute value than a voltage applied to the bit line.

Abstract: A dynamic RAM provided on a semiconductor substrate comprises: a memory cell including a capacitor for storing electric charges as information, the capacitor having a storage gate electrode to which a potential other than a ground potential is applied during normal operation of the dynamic RAM; a peripheral circuit including a CMOS circuit; and grounding means for applying the ground potential to the storage gate electrode only in a predetermined period immediately after a start of application of a power supply voltage to the dynamic RAM.

Abstract: A semiconductor memory device determines the level of a select control signal, according to the level of drive signals for two systems as generated in the preceding access cycle, and the level of the least significant bit of an address to fetch data in a desired serial access cycle. In accordance with this select signal, a select circuit selects one of the drive signals as generated by drive signal generating circuits, and supplies the selected signal to two data selecting/fetching systems. The function of this select circuit allows one of the two data selecting/fetching systems to first start the data access operation.

Abstract: A memory is disclosed which uses a microcapacitor as a data storage portion. The microcapacitor uses as its main electrode surface the side wall of a first trench formed on a semiconductor substrate, and is fabricated by diffusing an impurity from a second diffusion trench adjacent to the first trench by setting the shapes and diffusion conditions of the first and second trenches so that the tip of the diffusion layer reaches the side wall of the first trench. The capacitor uses the diffusion layer as one of the electrodes. An insulating film is deposited on the side wall of the first trench and an electrode as the other electrode of the capacitor is deposited on this insulating film. The memory can reduce a leakage current between memory cells by connecting the capacitor to a transistor fabricated in the same semiconductor substrate, and can be formed within a limited space.

Abstract: A volatile semiconductor memory module (RAM) is combined with a permanent memory based on an electrically polarizable, preferably ferroelectric, layer within an integrated monolithic module in such a manner that, as a result of a STORE command, the information present in the semiconductor memory is permanently stored by polarization of selected regions of the electrically polarizable layer. In the same way the permanently stored information can be read out again as a result of a RECALL command and returned to the semiconductor memory. Preferably, a ferroelectrically polarizable layer 11 is applied to the semiconductor memory, which layer, in the same way as the semiconductor memory, is provided on its upper side and underside with word and bit lines in the form of strip electrodes, 9,12. The strip electrode system 9 on the underside of the ferroelectric layer 11 simultaneously forms the word or bit line system of the semiconductor memory facing the surface.

Abstract: A transistor varactor for dynamic semiconductor storage means which are formed on a doped silicon substrate having a high integration density and which includes one field effect transistor which has source and drain and a gate and a varactor overlaps the gate electrode and is formed as a stacked capacitor. The gate electrode and the varactor are electrically isolated from each other by insulating layers and the contact of the source zone is electrically isolated from the gate electrode by the insulating layers and the upper polysilicon layer of the varactor formed by oxidation of the side portions of the polysilicon layer. The contact of the source zone adjusts to the gate electrode and to the polysilicon layer in that the distance of the contact of the source zone relative to the gate electrode and the polysilicon layer is independent of the photographic accuracy. A buried contact between the polysilicon layer and the drain zone is self-adjusted relative to the gate electrode.

Abstract: A semiconductor memory device comprises a silicon substrate; an insulating layer formed over this substrate comprising a first portion and a second portion; at least one monocrystalline silicon island formed within the insulating layer, separated from the silicon substrate by the first portion of the insulating layer and from one another by the second portion of the insulating layer, with at least one trench having a wall defined by a side of the at least one monocrystalline silicon island and extending into the first portion of the insulating layer; a lower electrode film formed inside each of the at least one trench in contact with the at least one monocrystalline silicon island; a dielectric film formed on the lower electrode; and an upper electrode film formed on the dielectric film. Information is stored as charge in a capacitor consisting of the lower electrode film, the dielectric layer, and the upper electrode film.

Abstract: A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on the substrate and are connected to the drains of the driver MOS transistors, respectively. A conductive film for fixing the sources of the driver MOS transistors to a ground voltage is formed above the principal surface of the semiconductor substrate, and this conductive film defines one electrode of a capacitance element formed on the substrate. The conductive film is formed over the load resistors formed on the semiconductor substrate so as to constitute an electric field shield for the load resistors.

Abstract: A semiconductor memory device includes a column decoder which is constructed such that it selects two adjacent columns in a memory cell array, and by means of which one of the two columns at a higher or lower position is selected, depending on whether or not a control signal indicates that one is added to a designated address. When the designated column address is the most significant address, the most and least significant addresses are selected, and if, in this case, the control signal indicates that one is added to the designated address, the least significant column address is selected and an address carry signal is generated. If, on the other hand, the control signal indicates that one is not added to the designated address, then the most significant column address is selected, in which case no address carry signal is generated.

Abstract: A method for memorizing a data bit in an integrated static MOS-type RAM, a transistor for performing the method, and a memory produced by the method are described. An MOS transistor with a weakly doped channel has a hysteresis phenomenon with subthreshold conduction. The transistor is advantageously used as a memory element in an integrated static RAM cell.

Abstract: The invention provides a semiconductor memory having a plurality of memory cells and a bit line connected to the memory cells comprising, the bit line being formed of a plurality of sub-bit lines, switch means for interconnecting and disconnecting the sub-bit lines, reference potential means for storing reference potentials, and sense amplifier means for comparing the output of an addressed memory cell with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.