Abstract: The spacing between the horizontally-adjacent floating gates of a "T-shaped" flash electrically programmable read-only-memory (EPROM) array is reduced beyond that which can be photolithographically obtained with a given process by covering the layer of polysilicon that forms the floating gates with two sacrificial layers, exposing strips of the polysilicon layer with a standard photolithographic process, forming spacers that protect a portion of the exposed polysilicon layer, and then etching the layer of polysilicon that remains exposed.

Abstract: There is a case where a memory cell brought to an over-erase (depletion) state if the erasing time is too long, for example, in an electrically erasable non-volatile semiconductor memory device. In this case, the transistor constituting the memory cell is always in ON state and causes erroneous operation. Therefore, it is detected whether there is any memory cell in the over-erase state or not after erasing in each memory cell, and if any memory cell is detected being in the over-erase state, tunnel writing is performed in each memory cell. Specifically, electrons are injected into the floating gate of the transistor constituting each memory cell by a tunnel phenomenon. This causes the memory cell in the over-erase state to recover to a normal state. Detection of the over-erase state and recovery from it are performed by an over-erase correcting circuit 72.

Abstract: A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.

Abstract: A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses.

Abstract: A buried layer which is highly doped and implanted with high energy in a lightly doped isolated well in which an array of flash EPROM cells are provided. The buried layer is doped with the same conductivity dopant as the well in which it is provided, for example a p.sup.+ -type buried implant is provided in a p-type well. The buried layer enables channel size of the flash EPROM cells to be reduced providing a higher array density. Channels of the flash EPROM cells are reduced because the buried layer provides a low resistance path between channels of the flash EPROM cells enabling erase to be performed by applying a voltage potential difference between the gate and substrate of a cell.

Abstract: A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

Abstract: A semiconductor memory cell of the present invention comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a read/write node, and a plurality of capacitors for information storage connected at one end to said MOS transistors, respectively, at the end remote from said node.

Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming several of types of memory cells having different electrical properties. Storage data per memory cell is therefore so multivalued that the number of memory cells is reduced.

Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: A non-volatile memory device which includes a recording medium, a heating means for heating the recording medium, a reading means for reading the information stored in the recording medium, and the recording medium containing a liquid crystal compound.

Abstract: A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.

Abstract: In a DRAM which includes a memory cell consisting of one MOS transistor and one stacked capacitor, the node electrode of the capacitor is constituted of a stacked layer formed by alternately stacking a first conductor film and a second conductor film. As the first conductor film use is made of, for example, an n-type polycrystalline silicon film, and as the second conductor film use is made of, for example, an oxygen-rich n-type polycrystalline silicon film, or a silicide film of a high melting point metal. On the side faces of the node electrode, the edges of the first conductor films are at the positions that are more indented than the edges of the second conductor films. Because of the indentations, the surface area of the node electrode is increased so that a stacked capacitor with large capacitance can be realized even when the occupancy area of the capacitor is small.

Abstract: In a static random access memory device where thin film transistors are used memory cell loads, first and second semiconductor layers having source regions, channel regions and drain regions of the thin film transistors partly oppose first and second conductive layers serving as gate electrodes thereof. A third conductive layer for receiving a definite potential opposes at least the channel regions of the first and second semiconductor layers.

Abstract: A semiconductor mask ROM device has word lines embedded in a surface portion of a silicon substrate, a gate insulating layer covering the word lines and a silicon strips extending over the gate insulating layer and providing channel regions over the word lines, and the silicon strips are physically separated without a thick field oxide layer, thereby increasing the integration density of the memory cells.

Abstract: In a semiconductor memory device including a boosting circuit for generating a high voltage constantly, and a word line driving circuit for transmitting a high voltage from the boosting circuit on a selected word line, a capacitor for stabilizing the high voltage generated by the boosting circuit is formed of a series of capacitive elements using a FET having a gate insulating film identical in thickness to that of a insulating gate type field effect transistor in the memory device. A voltage applied across each capacitive element is relaxed, and the capacitor is improved in dielectric breakdown voltage characteristics, to stably supply the high voltage.

Abstract: The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.

Abstract: A semiconductor memory comprises a memory cell array including a plurality of digit lines, a plurality of word lines, a plurality of memory cells located at intersections between the digit lines and the word lines, and a column selection circuit for selecting one digit line from the digit lines in accordance with a selection signal. A sense amplifier includes a first P-MOS transistor for precharging a digit line selected by the column selection circuit, an inverting amplifier having an input connected to receive a signal on the selected digit line, and a second P-MOS transistor having a gate and a drain connected to an output and an input of the inverting amplifier, respectively. A gate-grounded third P-MOS transistor maintained in a conductive condition is connected at its source to a voltage supply voltage and at its drain connected to a source of the P-MOS second transistor.

Abstract: A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.

Abstract: In the manufacturing process of a Dynamic Random Access Memory cell, the conducting layer used for preventing the capacitive coupling between a bit line and a word line is formed over the surface of the entire memory cell excepting the contact region of a bit line and a storage electrode. Moreover, as the conducting layer used for preventing the capacitive coupling is used as an etching barrier in the etching process forming a contact hole, self-aligned contacts are formed. Therefore, the operation of the unwanted cell of a Dynamic Random Access Memory cell caused by the capacitive coupling is protected and a highly integrated Dynamic Random Access Memory cell is manufactured.

Abstract: An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.

Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

Abstract: A semiconductor device having a programmable memory cell which includes a bipolar transistor of which a base region (13) can be provided with a base current through a control transistor (7, 8, 9, 10). The bipolar transistor has an emitter region (12) connected to a first supply line (151) and has a collector region (14) connected to a second supply line (152) through a load (16). A constant potential difference is maintained between the two supply lines (151, 152) during operation. The collector region (14) is laterally electrically insulated and provides a feedback to the control transistor in such a manner that, during operation within a certain voltage domain, a change in the voltage difference between the emitter region (12) and the collector region (14) leads to an opposite change in the conductivity through the control transistor.

Abstract: Memory cells having a stable write operation are formed in an array on a CMOS gate array semiconductor substrate. Each memory cell includes mutually adjacent transistors from a first pair of complementary conductivity type MOS transistor rows. These transistors are used to form a flip-flop and first and second access gates. The memory cell further includes mutually adjacent MOS transistors from a second pair of complementary conductivity type MOS transistor rows. These transistors are used to form an inverter and a third access gate connected to the output of the inverter. The input of the inverter is connected to one end of the flip-flop. The inputs of the first and second access gates are connected to bit lines through which complementary data signals are applied. The gates of the first and second access gate transistors are connected to a write word line.

Abstract: A nonvolatile memory circuit having a decoding scheme for reliable multiple bit hot electron programming. The nonvolatile memory circuit has a memory array in which data received at each data input can be programmed into multiple memory bits simultaneously. The address of each memory bit selected for programming is decoded by a row decoder and a column decoder. The row decoder decodes the word line of each selected memory bit and the column decoder decodes the bit line of each selected memory bit. The column decoder includes a programming column decoder and a read column decoder. The programming column decoder is enabled during a programming operation and disabled during a reading operation. The read column decoder is enabled during a reading operation and disabled during a programming operation. During a programming operation, a programming voltage is applied to the nonvolatile memory.

Abstract: A PROM built-in micro computer has a semiconducting nonvolatile memory which can be written into electrically, and has a micro computer. It detects a semiconducting nonvolatile memory cell whose readout current is less than or equal to a constant value at a time of data comparison after a writing operation. The PROM built-in micro computer is adapted to prevent a readout error which may result from a fluctuation of temperature or supply voltage. This may be done by changing a reference potential at the time of a data comparison, by changing the sensitivity of a sense amplifier, or by changing a readout current or a threshold value of the PROM cell.

Abstract: Disclosed is an EEPROM cell which can be manufactured with ease by the standard CMOS process. The EEPROM cell of the present invention has a first MOS transistor formed in a semiconductor substrate of a first conductivity type and having current conducting regions of a second conductivity type and a gate electrode, a well of a second conductivity type provided in the substrate, a plate electrode formed on the well with an insulating layer interposed therebetween, and at least one region of the first conductivity type formed in the well adjacent to the plate electrode. The gate electrode and the plate electrode are connected in common and act as a floating gate, and the well acts as a control gate.

Abstract: A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

Abstract: A non-volatile memory system which includes an array of memory cells with each of the cells including a source, drain and intermediate channel and which is suitable for low voltage operation such as battery powered applications. A floating gate is positioned over the channel and a control gate is positioned over the floating gate. The array is formed in a P type well, with the P well being formed in an N type well. The N well is formed in a P type substrate. The system includes circuitry for applying appropriate voltages for programming selected cells, reading selected cells and erasing the cells. The substrate is biased to circuit ground and, in read operations, the N well/P well PN junction is reversed biased. A positive voltage, typically a low level battery-supplied voltage, is applied to the control gate of the selected cell to be read and the source of the selected cell is biased to a negative voltage.

Abstract: A semiconductor device used as a semiconductor memory device is disclosed which is made of an amorphous silicon material that provides either a "1" or "0" memory state when the amorphous silicon material is in a non-conduction or insulating state and a "0" or "1" memory state when the amorphous silicon material is transformed, by use of a breakdown voltage applied to electrodes coupled thereto, into a conducting state. The amorphous silicon material is located adjacent to a doped semiconductor region of a semiconductor substrate separated only by a relatively thin primarily metal ohmic contact. The resulting semiconductor structure for the semiconductor device or semiconductor memory device is primarily a single level metalization type structure. A write-once, read-only semiconductor memory array is also disclosed which uses, as each memory cell of the array, one of the disclosed semiconductor memory devices.

Abstract: An SRAM cell includes an open-base, bipolar transistor serving as a load device and one pull-down transistor having an associated leakage current. The amplification .beta. of the bipolar transistor controls the amount of load current through the bipolar transistor. The bipolar transistor provides the necessary load current to ensure the SRAM cell maintains its logic state.

Abstract: A semiconductor device having an increased integration density. The semiconductor device includes a memory cell array, and a peripheral circuit region formed over the memory cell array and to be in electrical connection to the memory cell array for controlling the input/output of the data signals. A large part of a semiconductor chip area can therefore be used for the memory cell array, thereby increasing the integration density of the semiconductor device.

Abstract: A gate electrode layer constituting a gate of a P-channel type MOS transistor formed on an upper layer is made of P-type polycrystal silicon and is connected to a diffusion region of an N-channel type MOS transistor formed on a lower layer by extending an end of the gate electrode layer into a contact hole above the diffusion region. Therefore, an aspect ratio of the contact hole becomes small and a coverage of a wiring for connecting the gate of the P-channel type MOS transistor and the diffusion region of the N-channel type MOS transistor is improved, so that the wiring is not snapped.

Abstract: A DRAM device has a first semiconductor region of one conductivity on the silicon film of a silicon-on-insulator substrate. A second and a third semiconductor region of the opposite conductivity type are formed in the first semiconductor region. A fourth semiconductor region of the same conductivity type as the first semiconductor region is formed within the second semiconductor region with higher doping concentration. An insulating layer is formed on the semiconductor surface. On top of the insulating layer, a gate electrode is formed and is at least partially overlapped with the first, the second, the third, and the fourth semiconductor region. A storage node is formed in the first semiconductor region between the second and the third semiconductor region where the information is stored. The amount of charge stored in the storage node is controlled by a first transistor including the fourth semiconductor region, the second semiconductor region, the storage node, and the gate electrode.

Abstract: A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.

Abstract: As a memory medium, a liquid crystal composite or a composite including a liquid crystal component in a molecule is used. The memory medium is heated by a heat generating layer which is heated by a pair of electrodes, thereby changing a phase of the memory medium. Thus, data is written into the memory medium. A change in a property or a phase transition of the memory medium is electrically or optically detected, thereby reading the data from the memory medium.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A semiconductor SRAM device is provided wherein the electrical characteristics of the memory cell of the SRAM device is enhanced by decreasing the OFF-current and by increasing ON-current of PMOS thin film transistor (TFT) load elements. An offset region is formed between the drain and channel regions of the PMOS TFT. The gate is formed below (or above) the channel region of the PMOS TFT, and an insulating layer is formed below the gate. A ground potential V.sub.ss conductive layer is formed below the insulating layer, facing the offset region, to thereby operate as a gate for the offset region. The ground potential of the conductive layer facing the offset region of the PMOS TFT is constantly ON because of the gate operation of the ground potential conductive layer. A higher ON/OFF current ratio results, and the electric characteristics of the PMOS TFT load elements and therefore the SRAM device are thereby enhanced.

Abstract: A storage capacitor incorporate in a semiconductor dynamic random access memory cell has an accumulating electrode of p-type polysilicon electricaly conencted to an n-type drain region of an associated switching transistor, a dielectric film structure covering the accumulating electrode and a counter electrode opposed through the dielectric film structure and formed of a p-type polysilicon, and the dielectric film structure is thinner than a critical thickness for a direct tunneling current by virtue of the wide potential barrier between the dielectric film structure and the p-type polysilicon and the Fermi level of the p-type polysilicon falling into the forbidden band of the other p-type polyslicon.

Abstract: A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses.

Abstract: A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.

Abstract: A circuit for programming an EEPROM 42 which is used to provide trim adjustment for an integrated circuit (IC). The programming circuit provides the capability of programming the EEPROM 42 indefinitely, employing interfaces which are available even after the IC is packaged and encapsulated. Furthermore, it provides the manufacturer or enduser the capability of disabling the programming function permanently, to thereby prevent any inadvertent modifications of the EEPROM 42 data. The programming circuit includes a one-bit EEPROM 32, a nonvolatile memory element which retains its programmed logic state whether or not it is powered up. EEPROM 32 is set during final probe test by the application of a voltage to a probe pad 30 coupled to its set input terminal. Probe pad 30 is exposed such that it may be contacted by a probe prior to IC encapsulation, but is inaccessible after encapsulation.

Abstract: In a semiconductor memory comprising first bit lines, second bit lines and first nonvolatile split gate memory cells and second nonvolatile split gate memory cells respectively having common source electrodes, memory gate electrodes connected to common memory gate lines, and drain electrodes connected, respectively, to the first bit lines and the second bit lines, a source voltage applying means applies a voltage VS different from a voltage applied to the substrate and meeting a relation represented by:min(VB1, VB2)<VS<max(VB1, VB2)where VB1 is a voltage of the first bit line, VB2 is a voltage applied to the second bit line, min(VB1, VB2) is the lower one of the voltages VB1 and VB2, and max(VB1, VB2) is the higher one of the voltages VB1 and VB2, to the source electrode in writing data on the first nonvolatile split gate memory cell.

Abstract: A differential analog memory cell provides output signals governed by precisely adjustable voltage levels having minimal drift. The memory cell comprises a pair of differentially connected floating gate MOSFETs, each MOSFET having its source connected to a common current source and its drain connected to one leg of a current mirror. The floating gate of each MOSFET is connected to one electrode of a tunneling capacitor and one electrode of a coupling capacitor. Voltages applied to the other electrode of the tunneling capacitor inject charges onto the corresponding floating gate, the voltage of which is determined by the size of the coupling capacitor. Output voltages taken from the drains of the floating gate MOSFETs can be precisely adjusted up or down by applying single polarity voltage pulses to one or the other injector nodes.

Abstract: A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. Theis reduces bit line sheet resistance and increases the punch through voltage between adjacent bit lines.

Abstract: Improvement of a fuse for use in the redundancy technique particularly for a semiconductor memory device. The fuse is constituted by an MIS type transistor having a gate insulating layer, which comprises at least two types of insulating films. Redundancy information is stored by shifting the threshold value of the MIS type transistor.

Abstract: A memory card includes a plurality of nonvolatile memories, each having a pad for applying a busy signal indicating that a respective memory is busy and a circuit for coupling the busy signal to the pad. The pad of each memory is coupled to a node external to the memories. A resistive circuit is used for coupling a first voltage to the node. When each of the memories does not output the busy signal at the pad, the node assumes a first voltage. When the pad of at least one of the memories outputs the busy signal, the node assumes a ground voltage. An output pin is used for supplying a card busy output signal when at least one of the memories is indicated busy and an input pin is coupled to the node for receiving the card busy output signal at the node. A pass logic is coupled to the input and output pins for passing the card busy output signal directly from the input pin to the output pin.

Abstract: A semiconductor memory device includes an array of rows and columns of field effect transistors (FETs) which provide memory locations. The FET gate electrodes in each row are connected to a respective row conductor and the FET first and second main electrodes in each column are connected to respective adjacent column conductors so that the second main electrodes in one column are connected to the first electrodes of the FETs in any adjacent column. Circuitry is provided for storing data at and reading data from the memory locations. The circuitry stores data at a desired memory location by applying a first predetermined voltage V.sub.g.sup.W to a selected row conductor and a second predetermined voltage V.sub.d.sup.

Abstract: A high capacitance multi-level storage node contact is proposed for high density SRAMs. The proposed contact connects several poly levels to diffusion and to a trench capacitor, in one contact. The high storage node capacitance provided by the trench capacitor substantially reduces the soft error rate probability of the cell. The use of a single contact to connect several levels reduces the area. The contact preferably uses TiN as a barrier layer to reduce dopant diffusion between different poly layers.

Abstract: A non-volatile memory cell according to the present invention includes: a semiconductor layer of a first conductivity type having an upper portion; a pair of impurity diffusion regions of a second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the pair of impurity diffusion regions in the upper portion of the semiconductor layer; a gate insulating film provided on the upper portion of the semiconductor layer, having thin portions covering at least part of the pair of impurity diffusion regions and a thick portion covering the channel region; floating gate electrodes provided on the thin portions of the gate insulating film; a control gate electrode provided on the thick portion of the gate insulating film and electrically insulated from the floating gate electrodes; and an insulating film provided between the control gate electrode and the floating gate electrodes, capacity-coupling the control gate electro

Abstract: A static read-only-memory (ROM) is derived from a gate array in which both P-channel transistor (24) and an N-channel transistor (30) are used to convey a logic 1 or 0 to a bitline (Bitline0). The invention maximizes the use of gate array transistors in a gate-array chip and achieves a high density of ROM bits per unit area. In CMOS gate arrays, transistors are arrayed in alternating rows of P-channel and N-channel transistors. A decoding scheme inverts the logic signal to each row of P-channel transistors to yield a functional ROM.