Abstract: The cell to be programmed is subjected to wet isotropic etching to remove the oxide from above, beside and partially beneath the strip of polycrystalline silicon which forms the cell gate. There follows implantation of a dopant of a type opposite to that of the source junction and drain junction performed through the gate strip. Finally reoxidation of the entire cell area is performed.

Abstract: An electrically programmable read only memory device formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate.

Abstract: The semiconductor memory device of the present invention is formed on an integrated substrate and is immune to alpha radiation. The device includes a semiconductor substrate of a first conductive type and a memory cell formed in the substrate which has a switching MOS transistor having at least a first impurity region of a second conductive type and a capacitor connected to the transistor for storing memory data. A second impurity region of the first conductive type and having a higher concentration than that of the substrate is provided on the substrate surface at a position covering the first impurity region.

Abstract: In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.

Abstract: A pass circuit (54) passes a boot signal through a first transistor (60) when the pass circuit (54) is selected by a select signal (106). A second transistor (100) is precharged prior to receiving the select signal (106). In response to the select signal (106), a high voltage is passed to the first transistor (60) and the voltage at the gate of the second transistor (100) is pulled above a high voltage. After a delay period, another transistor (88) conducts between the gate of the second transistor (100) and V.sub.cc, to discharge the gate voltage. With both the source and gate of the second transistor (100) at a high voltage, the second transistor (100) is put in a non-conducting state. As the boot signal passes through the first transistor (60), the gate voltage of the first transistor (60) is increased above a high voltage, but the voltage at the gate of the second transistor (100) is maintained at V.sub.CC, thus preventing junction breakdown.

Abstract: An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal silicon oxide which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

Abstract: The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and separate from that of the pickup transistor.

Abstract: An electronic circuit element with field-effect operation and with such characteristics that its source terminal (2) is to be connected, in the case of an N-type element (1a) to the positive, and in the case of a P-type element (1b) to the negative pole of a current source, said element (1) being non-conducting if its gate terminal is at the voltage of the pole connected with the drain terminal (3). This element (1) can be used as a memory circuit, for forming a trivalent switching circuit, and as an analogue amplifier with a negative resistance characteristic. Such an element (1) can be assembled from a series connection of an n-type and a p-type field-effect transistor (11a, 11b) having their source electrodes (12) interconnected, the gate terminal (4) being formed by the gate electrode (14) of the n-type or p-type transistor (11a, 11b) resp., the gate electrode (14) of the other transistor being connected with the drain electrode (13) of the first one.

Abstract: An electrically programmable and erasable memory device is disclosed, in which carriers such as electrons transfer between a floating gate electrode made of polycrystalline silicon and a drain region through a thin insulating film portion provided on a part of the drain region by an electric field induced in the thin insulating film portion. The floating gate electrode has such an impurity concentration distribution that the concentration of a portion adjacent to the thin insulating film portion is lower than the concentration of the remaining portion.

Abstract: A static-type semiconductor memory device having a three-layer structure: gate-electrode wiring lines being formed from a first conductive layer of, for example, polycrystalline silicon; word lines, ground lines, and power supply lines being formed from a second conductive layer of, for example, aluminum; and bit lines being formed from a third conductive layer of, for example, aluminum. The bit lines extending in a column direction, and the ground lines extending in a row direction. Thus, providing an improved degree of integration, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles.

Abstract: The present invention provides a single-poly electrically erasable programmable read only memory device which is formed in a semiconductor substrate of a first conductivity type. The memory device includes a pass cell comprising first and second regions of a second conductivity type, opposite to that of the first conductivity type, formed in the substrate. The first and second regions are separated by a first channel region formed by the substrate. A first conductive portion is formed over the first channel region and is separated from the first channel region by a dielectric material. A control cell comprising third and forth regions of the second conductivity type is also formed in the substrate. The third and forth regions are separated by a second channel region formed by the substrate. The first conductive portion extends over the second channel region and is separated from the second channel region by the dielectric material.

Abstract: An electrically alterable, non volatile memory device capable of enduring a high number of cycles utilizes an array of "semidouble" cells, each formed by a pair of elementary EEPROM cells connected substantially in parallel and a single select transistor. A special program lines biasing circuit generating a bias voltage representative of a condition wherein one of the two elementary EEPROM structure is broken and sense amplifiers comprising a comparator circuit comparing the current flowing through an addressed semidouble memory cell with the current flowing through a reference cell comprising a pair of virgin EEPROM type elementary cells to ensure operability of each bit of the memory also when one of the two elementary cells supporting the bit fails. Different from known memories, only the EEPROM structure is duplicated while column lines, select lines and ancillary circuitry don't require duplication.

Abstract: A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate.

Abstract: A semiconductor memory device comprises: a charge holding capacitor formed on a semiconductor substrate; an insulating layer formed on the capacitor; and a transistor formed on a monocrystalline or substantially monocrystalline semiconductor layer, which is provided by forming, on the insulating layer, a hetero material of a nucleation density sufficiently higher than that of the insulating layer and of a size smaller enough to allow growth of a single nucleus of a semiconductor layer, followed by crystal growth around a single nucleus formed on the hetero material.

Abstract: In an electrically-erasable/programmable nonvolatile semiconductor memory device according to the invention, a one-bit memory cell is constituted by a series circuit of a selecting MOS transistor and a data storage MOS transistor. A floating gate electrode and a control gate electrode are formed in the data storage MOS transistor, One portion of the floating gate electrode is formed on a channel region of the data storage MOS transistor through a gate insulating film. The other portion of the floating gate electrode is formed on a drain region of the data storage MOS transistor through a gate insulating film, a portion of which is sufficiently thinner than the gate insulating film. One and the other portions of the floating gate electrode are structurally separated from each other but are electrically connected with each other on a field region. A control gate electrode having substantially the same shape as that of the floating gate electrode is formed thereon through a gate insulating film.

Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.

Abstract: This invention provides a semiconductor memory device for an integrated circuit comprising a semiconductor substrate of a first conductivity type, a field insulation layer on the semiconductor substrate, and a switch. This switch includes a gate insulation layer, a gate electrode on the gate insulation layer, and a pair of impurity regions of a second conductivity type in the substrate adjacent to the gate electrode. The device also includes a capacitor including a first electrode connected to one impurity region, a second electrode connected to a predetermined voltage, insulation means for separating the first and second electrodes, and groove means extending into the substrate for increasing the capacitace area of the first electrode.A method for making the devices is also described.

Abstract: Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Abstract: A semiconductor memory (DRAM) device comprises memory cells, each of which is composed of an FET and a capacitor. The FET has an SOI structure. The capacitor is composed of a dielectric layer as an insulating layer for the SOI structure, an upper capacitor electrode as a semiconductor layer for the SOI structure, and a lower capacitor electrode as a semiconductor substrate. The substrate is biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage.

Abstract: A data processing LSI constructing a microcomputer has an EPROM for changing a program. The EPROM can be accessed directly through the external terminals of the data processing LSI. The EPROM is statically operated when it is written with data by direct access. However, the statically operated EPROM consumes relatively high power. This power consumption by the EPROM is reduced by dynamically operating its read circuit, address decoder and so on. For example, the read circuit is constructed of a sense amplifier and a latch circuit, and the sense amplifier has its operation interrupted after the latch circuit has latched the read data. The address decoder is composed of a load MOSFET and address MOSFETs. The load MOSFET is caused to act as a precharge element in the dynamic operation and as an opertion current feeding element in the static operation.

Abstract: A content-addressable memory cell and memory array are disclosed. Each cell comprises a random access memory storage component and a comparison component for performing the contact addressability function. In a disclosed CMOS embodiment, a DRAM cell and an exclusive-NOR gate are combined to form the CAM cell.

Abstract: A static RAM in which the source of a MOSFET of a memory cell is connected to a signal line which supplies a high level or a low level depending upon a reset signal, the memory cell containing a pair of data-holding MOSFET's of which the gates and drains are cross-coupled.

Abstract: In a semiconductor memory device, a memory cell comprises a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode connected to a word line. A charge storage electrode is connected to the drain of the first transistor and forms a capacitor with the gate electrode. A semiconductor layer is formed over the charge storage electrode. A second MOS transistor (Q2) of a second channel type formed in the semiconductor layer. The charge storage electrode forms a gate electrode of the second transistor. The drain of the second transistor is connected to a power supply. The source of the second transistor is connected to a bit line, which is either the same as or separate from the first-mentioned bit line. For writing data, a first potential is applied to the word line to make conductive the first transistor for writing data, and the potential applied to the source of the first transistor is varied depending on whether the data to be written is "0" or "1".

Abstract: A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

Abstract: A memory array comprised of floating gate, direct write nonvolatile memory cells having cell interiors which are interconnected by successive adjacent rows to share column lines between adjacent columns of cell and thereby reduce the column line pitch.

Abstract: A dynamic random access memory is disclosed which has memory cell units formed on a silicon substrate, each of which includes four memory cells, each of these including a MOS transistor and a MOS capacitor. One cell unit occupies a substantially square area of the surface of the substrate. The four memory cells included in this cell unit are arranged along the diagonal lines of the square area in the shape of a cross. The four transistors are connected to a common drain through a common drain region. The capacitors are respectively arranged at the four corners of the square area so as to have a relatively increased capacitor area, thereby obtaining a large capacitance.

Abstract: A one-transistor memory cell comprises a semiconductor body which has a thin insulating layer on a boundary surface and a conductive layer on the thin insulating layer, the conductive layer representing that electrode of a storage capacitor that is connected to a selection field effect transistor. The selection field effect transistor is realized in a layer applied as a polycrystalline semiconductor layer and is then recrystallized. The memory cell provides the smallest possible semiconductor surface. This is achieved in that the recrystallized semiconductor layer is disposed above the conductive layer 3 and is separated therefrom by an intermediate insulating layer, whereby it extends in the lateral direction, at most, up to the edge of the semiconductor layer 3.

Abstract: A semiconductor device has a first ROM and a second ROM on a single semiconductor chip. To write information in the first ROM, a contact mask pattern is used by which wirings are formed on the chip, while information is written in the second ROM when memory transistors are formed on the chip. The first ROM stores the non-commonly used information of the program to be stored, or a specific user supplied program, and the second ROM stores predetermined and commonly used information of the program to be stored. Thus, a semiconductor device having a fixed memory in which a large capacity of information is stored can be provided to a user within a short period of time.

Abstract: A ROM circuit is used in place of a conventional fuse type ROM which is incorporated in a semiconductor integrated circuit network together with other circuit blocks on a chip. The ROM circuit comprises a first transistor having a control and a floating gate and a depletion type second transistor having a gate formed as an extension of the floating gate. The second transistor outputs a high level control signal if hot electrons have been accumulated on the floating gate of the first transistor by the application of a predetermined high level input signal to the control gate thereof, and outputs a low level signal when the high level input signal has not been provided to the control gate. The first transistor is freed from a soft write problem because it is separated from a voltage source in the read mode.

Abstract: The gate electrode of a first CMOS inverter is connected to the drains of each transistor of a second CMOS inverter via an interconnection, and the gate electrode of the second CMOS inverter is connected to the drains of the first CMOS inverter via an interconnection, to form a flip-flop circuit. A pair of transfer transistors are connected to the nodes of this flip-flop circuit. A plurality of memory cells each constructed by the flip-flop circuit and the pair of transfer transistors are integrated in a matrix form to form a semiconductor memory device. The pair of gate electrodes are formed of a first polycrystalline silicon layer which includes an impurity of the first conductivity type. The pair of interconnections are formed of an impurity-doped second polycrystalline silicon layer and a high-melting point metal layer, and formed on a first interlayer insulation film.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: Word lines of a memory cell array are coupled to the output portion of a first decoder while the input portion of the first decoder is coupled to a plurality of signal lines which are elongated on the memory cell array. The signal lines are provided for a predetermined plurality of word lines, and each of said signal lines can be coupled to the word lines by switching devices. Preferably, the signal lines can be formed of a low resistance material such as aluminum to enhance the speed while the word lines can be formed of polycrystalline silicon to allow simultaneous formation with the memory cell gate electrodes. By virtue of providing each signal line for more than one word line, the design requirements for the signal lines are less stringent than previous arrangements wherein a one-to-one relationship has been attempted between polycrystalline silicon word lines and aluminum connection lines.

Abstract: The invention provides small size, high speed data latches comprising memory cells that are fabricated according to a Gallium Arsenide (GaAs) process. The memory cells are implemented by a relatively few number of depletion metal semiconductor field effect transistors (MESFETs), saturated resistors and diodes. A common gate MESFET is utilized in each memory cell configuration as part oif a non-inverting positive feedback path to provide the gain necessary for bistable operation.

Abstract: Unique EPROM and EEPROM devices are provided with a composite dielectric layer between the control gate and the floating gate which is sufficiently thick to provide electrical and physical integrity but also has a high equivalent dielectric constant. The use of the composite dielectric layer alleviates certain problems experienced in the prior art EPROM and EEPROM devices which utilize a polycrystalline silicon floating gate and a polycrystalline silicon control gate separated by an SiO.sub.2 dielectric layer, such as the problems of sharp silicon points resulting from polysilicon grain growth causing low dielectric breakdown strength. In contrast to the prior art, a composite dielectric layer serves as a partially relaxable dielectric between the control gate and the floating gate of an EEPROM or an EPROM. The composite dielectric layer provides high capacitance between the floating gate and the control gate without the insulative and breakdown problems encountered with prior art thin dielectric layers.

Abstract: A system for preventing forward biasing of the bit line junctions formed between the N-well and bit lines of a CMOS memory. The system includes a gating system for maintaining the bit line voltage at V.sub.CC /2 whenever the well voltage is less than V.sub.CC. A well regulator and well pump maintain the well voltage at a selected multiple of V.sub.CC.

Abstract: There is described a CMOS random access memory having memory access circuitry which substantially eliminates substrate noise caused by capacitive coupling of the bit lines to the substrate, and which allows the memory to have equal length access and cycle times. Access circuitry for each column of cells includes a pair of differential bit lines, at least one bit line equalization transistor, and a CMOS sense amp. The sense amp has two p-channel pull-up transistors, each having its source node connected to a common pull-up node, and two n-channel pull-down transistors, each having its source node connected to a common pull-down node.At the beginning of each memory access cycle the differential bit lines are equalized and the common pull-up and pull-down nodes are equalized. Then, substantially simultaneously, the common pull-up node is charged while the common pull-down node is discharged.

Abstract: A programmable non-volatile memory cell is disclosed that can be written into the "1," "0," or "previous" state in the presence of unfocused illumination, preferrably ultraviolet (UV) light. The programmed state is controlled by low electrical voltages. Once the illumination is removed the programmed state is non-volatile. The memory cell can be fabricated using conventional MOS processing techniques with no additional mask steps. The cell can thus be implemented on virtually all silicon gate nMOS and CMOS processes.

Abstract: An integrated RS flip-flop circuit comprises two cross-coupled inverters which respectively consist of a field effect transistor and a resistor connected in series. Each field effect transistor is connected to an additional logic element whose control input represents the R or the S input, respectively. Realization of a flip-flop circuit on the smallest possible semiconductor is achieved by designing the additional logic elements as hot electron transistors, each of which is combined with one of the field effect transistors to form a common component which assumes two transistor functions but only requires the area of one field effect transistor. The invention is particularly useful in VLSI circuits.

Abstract: In a high-density VLSI NMOS semiconductor such as a ROM, a voltage sensing mode amplifier in the output thereof, operative to sense relatively very low input signal swing bit read signals from the ROM with relative insensitivity to fabrication process variation. The structure includes a common gate amplifier for receiving the ROM signal, a very sensitive reference voltage circuit, a two-stage differential digital switching module operative to compatively receive the common gate and voltage reference signals to effectively distinguish relatively weak bit signals as read from the high-density VLSI ROM.

Abstract: In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.

Abstract: A five volt only E.sup.2 PROM cell including metal bit read and bit ground column lines and polysilicon word select and program row lines. An interconnected word select and stacked gate transistor serially connect the bit read and bit ground lines. The cell also includes a tunneling structure, disposed below the program row line, for charging or uncharging a floating polysilicon gate in the stacked gate transistor. The bit ground line is disconnected from ground during the charging and uncharging operations.

Abstract: A semiconductor read-only memory device includes first and second MOS field effect mode transistors (MOSFET) as memory elements storing either one of binary values of binary information. The first MOSFET has such a relatively long effective gate length that it becomes conductive upon receipt of a first relatively high gate voltage applied thereto as a memory selection signal and becomes non-conductive upon receipt of a second relatively low gate voltage. The second MOSFET, on the other hand, has such a relatively short effective gate length that it becomes conductive whether the first or second gate voltage is applied thereto.

Abstract: A semiconductor device includes storage cells which have a non-volatile storage transistor and an access transistor connected in series therewith, whereby parts of a word (bytes) can be selected for writing and erasing. By means of a second access transistor, which is added to each storage cell, and by means of switches which are controlled by lines used for driving these second access transistors, the current dissipation is reduced and in non-selected storage cells the potential of the insulated control electrodes of the storage transistors is fixed, as a result of which the risk of undesired change of the information content is reduced.

Abstract: A non-volatile random access memory device includes a plurality of memory cells, each of which has a bistable (flip-flop) circuit which acts as an ordinary random access memory cell and at least one non-volatile memory transistor. The bistable circuit has two output terminals (a true output terminal and a complementary output terminal). One of the two output terminals is coupled to a control electrode of the non-volatile memory transistor, and the other output terminal is coupled to the drain of the non-volatile memory transistor. The source of the non-volatile memory transistor is coupled to a driving voltage source (e.g. 5 V) via a switching gate which is turned on when a control signal is applied thereto. In a normal operation mode, a normal driving voltage (e.g. 5 V) is supplied to the bistable circuit. On the other hand, when data in the bistable circuit is to be sheltered in the non-volatile memory transistor, a high voltage (e.g.

Abstract: In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.

Abstract: A semiconductor integrated circuit memory device having a plurality of static type memory cells is disclosed, which has a high degree of circuit integration with improved layout structure of wiring layers. One of power supply supply lines, for instance Vcc line, extends in parallel to a word line, and by utilizing a double metallic layer technique, the other power supply line, i.e. ground line, is also extended in parallel to the word line. For example, the ground line is made of a first aluminium layer, and the two data lines intersecting at right angles with the ground line are made of a second aluminium layer provided by the intermediary of an insulating layer. With such a structure, reduction in size of a memory cell can be achieved without restriction by the wiring layers.

Abstract: A semiconductor memory device including a nonvolatile random access memory cell constituted by a combination of a static random access memory cell or a dynamic random access memory cell and a floating circuit element, is disclosed.In the device, the circuit constitution, the application of writing voltage, and the like, are improved. Thus, the number of the circuit elements, particularly the number of floating gate circuit elements, is reduced. As a result, the cell area can be decreased, high integration of the device can be increased. In addition, improvement of the circuit configuration increases the discretion allowed in the layout design, and the plurality of applications of the write voltage improves the storage efficiency.

Abstract: A static storage cell is formed of two cross-coupled inverters each containing a field effect transistor and a resistor element connected in series therewith. Each circuit node is thus connected via an additional logic element to a bit line allocated thereto. A storage cell is provided which is on as small as possible a semiconductor area and has a short access time. This is achieved by designing the additional logic elements as hot electron transistors which are respectively combined with one of the field effect transistors to form a common component which only requires the area of a field effect transistor. The cell is useful in VLSI semiconductor memories.

Abstract: A dynamic semiconductor memory cell has a field effect transistor and a memory capacitor formed on a semiconductor body. In addition to a first zone, doped oppositely with respect to the doping of the semiconductor body, further zones are formed parallel to the boundary surface of the body and doped with the same conductivity of the semiconductor body, but to a higher degree. The further zones lie below regions at the boundary surface which are doped opposite to the semiconductor body. The further zones include edge portions which extend up to the boundary surface and which limit the regions thereabove in the lateral direction. A gate is provided and in an area of the semiconductor body beneath the gate and adjacent to the boundary surface a region is provided, doped opposite to the semiconductor body and connecting the edge portions. The edge portions, at the boundary surface, form a two-part channel area of the field effect transistor.

Abstract: A quaternary FET read only memory is disclosed wherein each FET storage element in the array has its threshold adjusted by ion-implantation to one of four values. Each FET element in the array has its drain connected to a drain potential V.sub.DD. A binary input signal from a conventional binary, true/complement generator will then enable the gate of a selected FET storage cell and the output potential at the source of that selected storage cell will be V.sub.DD minus the customized threshold voltage of that storage cell, which is output at an output node. The signal on the output node is a quaternary signal which may be amplified by a quaternary sense amplifier circuit and then converted from quaternary to binary signal by means of a converter. The quaternary read only memory is capable of storing twice as much information per unit area as is a conventional FET binary read only memory. The concept may be expanded to N levels of information storage, using FET array devices with N different threshold voltages.