Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A non-volatile semiconductor memory circuit capable of improving data retention characteristics and decreasing an area thereof comprises a constant current circuit and a non-volatile memory cell connected in series. A connection point between the constant current source and the non-volatile memory cell is selected to be an output to thereby enable writing, in a reading mode or a retention mode, in the non-volatile memory cell which is in a write state. The non-volatile semiconductor memory circuit includes a power supply for data reading and retaining and a power supply for data rewriting which are provided independently, and a transistor connected between the output and the power supply for data rewriting, in which the transistor is brought into conduction state when data is rewritten.

Abstract: Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell.

Abstract: A flash memory device and a method for manufacturing the same are provided. The flash memory device can include first and second memory gates on a substrate, an oxide layer on sides of and on the substrate outside of the first and second memory gates, a source poly contact between the first and second memory gates, first and second select gates outside the first and second memory gates, a drain region outside the first and second select gates, and a metal contact on the drain region and the source poly contact.

Abstract: The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing an erase operation, counting an erase pulse application number once the erase operation is completed, comparing the counted erase pulse application number and a reference value, defining a post program start voltage based on the comparison result, performing a post program operation and a verify operation using the defined post program start voltage, and performing a program operation on cells on which the post program operation has been completed.

Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.

Abstract: A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.

Abstract: A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.

Abstract: A nonvolatile memory device includes; a memory cell array including a plurality of memory cells arranged in word lines and bit lines, a high-voltage generator generating a program voltage pulse applied to a selected word line among the word lines, and a pass voltage applied to a non-selected word line, and control logic iteratively increasing the program voltage pulse and adjusting the pass voltage according to a defined increment during a program operation.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

Abstract: The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.

Abstract: A method of programming a nonvolatile memory device comprises a bit line voltage set-up step of receiving a program command and data to be programmed and setting up a voltage of a selected bit line according to a state of program data; a program step of supplying a program voltage to a word line selected for a program in response to a control signal for setting up the program voltage, supplying a first pass voltage to unselected word lines, and then performing the program; and a program verification step of, in response to a control signal which is subsequent to the control signal for setting up the program voltage and is used to set a verification voltage, performing a program verification operation by supplying the verification voltage to the selected word line.

Abstract: A nonvolatile semiconductor memory comprising: a first semiconductor layer having a first stripe-shaped region and a second stripe-shaped region which is adjacent to the first stripe-shaped region; a first NAND string formed on the first stripe-shaped region, the first NAND string having a plurality of first memory cell transistors connected in series; a first insulating film formed above the second stripe-shaped region; a second semiconductor layer formed on the first insulating film; and a second NAND string formed on the second semiconductor layer, the second NAND string having a plurality of second memory cell transistors connected in series.

Abstract: A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.

Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

Abstract: Methods and apparatuses are disclosed for biasing the source-side and the drain-side of a nonvolatile memory to add electrons to the charge trapping structure.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

Abstract: A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.

Abstract: A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in series between selection transistors Qs1 and Qs2 on two terminals of a selected bit line; and a control circuit 11 for controlling writing of the data from the memory cell array 10. The control circuit 11 records two values for at least a plurality of first memory cell transistors Q0, Q1, Q32 and Q33 respectively adjacent to the selection transistors Qs1 and Qs2 on two terminals of the bit line, and records more than three values for a plurality of second transistors Q2˜Q31 other than the first memory cell transistors.

Abstract: A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.

Abstract: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.

Abstract: An integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, each memory cell including two doped regions and a channel region therebetween, each pair of adjacent memory cells sharing a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member. A first word line is coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell. Each of a plurality of bit lines is designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N?1)th memory cell. The integrated circuit also has a plurality of global bit lines, each of which coupled to two of the bit lines via a switch.

Abstract: This disclosure describes techniques for using environmental variables to improve calibration of flash memory by adapting to changing threshold-voltage distributions. These techniques effectively increase the speed and/or accuracy at which flash memory can be written or read.

Abstract: A non-volatile memory device and a driving method thereof. The non-volatile memory device includes a floating gate formed on and/or over a first type well, and transistors formed on and/or over a second type well and connected in series to the floating gate. One of the transistors is a first transistor for program and erase operations, and the other one is a second transistor for a reading operation.

Abstract: A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

Abstract: A non-volatile microelectronic memory that has a memory cell array, which includes memory cell string pairs that share a bitline contact, that have separate source lines, and that have at least two transistors within each memory cell string that may be programming for sharing the bitline contact.

Abstract: Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract: Apparatus configured to perform a programming operation on at least one memory cell of the memory array in response to original data, and further configured to perform a comparison of verified data of the at least one memory cell of the memory array to the original data following success of the programming operation. Certain apparatus may be configured to permit skipping the comparison.

Abstract: Programmable antifuse transistor, in particular n-channel MOS transistor, and a method for programming at least one such antifuse transistor, includes at least one gate with a gate terminal, source with a source terminal, drain with a drain terminal, and substrate with a substrate terminal, configured so that active circuits/circuit elements do not have to be located at a distance from the antifuse, minimizing area requirements, without additional process steps the level of the potential difference between source terminal and substrate terminal is less than about 0.5 volts, drain terminal and source terminal lie at different potentials. By adjusting drain-source voltage and/or the gate-source voltage a flow of charge carriers occurs between source and drain, causing semiconductor material between source and drain to be thermally heated and to locally melt, forming at least one permanently conducting channel between source and drain.

Abstract: A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

Abstract: Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.

Abstract: Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less than a nominal programming preparation voltage as used in the conventional art. Programming pulses can be applied to selected word lines of the memory cells to be programmed when the uninhibited bit lines are at 0V.

Abstract: An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.

Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.

Abstract: Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Abstract: A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels.

Abstract: A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a common source and/or an N-well region, grounding and/or floating a control gate, and/or grounding a word line and/or a bit line. A method of operating may include erasing a semiconductor memory cell by floating and/or grounding a word line, applying a preset erase voltage to a control gate, and/or grounding an N-well, a bit line and/or a common source. A method of operating may include reading a semiconductor memory cell by grounding and/or floating a control gate, applying a preset read voltage to an N-well and/or a common source, grounding a word line, and/or applying a preset drain voltage to a bit line.

Abstract: A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.

Abstract: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

Abstract: Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to bit line instead of per cell. Word lines can be formed as second polysilicon patterns, which are used as control gates, and are provided perpendicular to the longitudinal axis of the bit lines. During formation of the second polysilicon patterns, a dielectric film and exposed regions of the first polysilicon patterns can be etched to form floating gates below the second polysilicon patterns.

Abstract: The invention provides a method for reading a first data storage of a memory cell. The method comprises sensing a first current of the memory cell by applying a first bit line voltage on the memory cell. When the first current is larger than a first reference current with respect to the first bit line voltage, the first data storage is determined to be at an un-programmed state. Otherwise, a second current of the memory cell is sensed by applying a second bit line voltage on the memory cell. When the difference between the first current and the second current is larger than the difference between the first reference current and the second reference current, the first data storage is determined to be at the un-programmed state. Otherwise, the first data storage is determined to be at a programmed state.

Abstract: A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed.

Abstract: An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling.

Abstract: The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.

Abstract: A method of evaluating a semiconductor storage device of a floating gate type has calculating an electron density distribution of a tunnel insulating film of a memory cell by multiplying a change rate of a threshold voltage Vt of the memory cell of the semiconductor storage device with respect to the change of the logarithm of a time with ?*Cr*2k/Tox/q (where ? is the permittivity of the tunnel insulating film of the memory cell, Cr indicates a coupling ratio of the memory cell, Tox indicates the thickness of the tunnel insulating film, k indicates an attenuation rate of the existence probability when the charges are detrapped and is represented as k=(2mE/(h/2?)2)0.5, m indicates the mass of the electron, E indicates an energy level of the trap of the tunnel insulating film, h indicates a Planck's constant, and ? indicates a circumference ratio).

Abstract: A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by ?FN to tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.

Abstract: A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation.

Abstract: A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the stepwise increasing step pulses according to the number of the stepwise increasing step pulses.

Abstract: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.