Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

Abstract: A semiconductor device includes a page buffer configured to read data out of a memory cell array in response to a bias enable signal, and a control logic configured to generate the bias enable signal and a bias precharge signal that are used to control the memory cell array. The control logic activates the bias enable signal and the precharge signal before a ready/busy signal activating a read operation of the memory cell array is enabled.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament; and a control circuit configured to execute a write sequence that writes data to the memory cell, the write sequence including: a setting operation that applies a setting pulse having a first polarity to the memory cell; and a removing operation that applies a removing pulse having a second polarity opposite to the first polarity to the memory cell; and the control circuit, during execution of the write sequence, is configured to repeatedly execute the setting operation until the memory cell attains a desired data storing state, and then to execute the removing operation.

Abstract: A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.

Abstract: An electronic device of the present technique includes a controller part for controlling operations of a non-volatile memory and a volatile memory, a power supply controller for controlling power to the controller part and the volatile memory, and a register for retaining running information about a program read from the non-volatile memory. When power is supplied to the controller part from the power supply controller and the running information about the program is not retained in the register, the controller part reads the program from the non-volatile memory and stores it in the volatile memory so as to execute the program, and retains the running information about the program in the register. When the running information about the program is retained in the register, the program is read from the volatile memory so as to be executed.

Abstract: An electronic device according to the present technique includes a non-volatile memory in which a program is stored, a volatile memory in which the program read from the non-volatile memory is stored, a controller part for controlling operations of the non-volatile memory and the volatile memory, and a power supply controller for controlling power to the controller part and the volatile memory. The controller part includes a power supply part and a signal fixing part. The power supply part is separated from another power supply line, and power for an interface signal of the volatile memory is supplied from the power supply part thereto. A voltage is supplied from the power supply part to the signal fixing part, and the signal fixing part fixes an output logic of the signal supplied to the volatile memory according to the signal from the power supply controller.

Abstract: The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.

Abstract: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device, and particularly to a semiconductor memory device including a memory cell array and a method of operating the semiconductor memory device. The memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit configured to program a selected memory cell into a target program state, wherein the peripheral circuit performs a program operation by applying a bit line voltage determined according to the threshold voltage to a bit line of the selected memory cell when a threshold voltage of the selected memory cell is higher than a first verification voltage and is lower than a second verification voltage.

Abstract: Embodiments include a memory managing method of a nonvolatile memory device, which includes detecting whether sub-blocks of memory blocks are programmed, and programming write data at a memory block having a programmed sub-block from among the memory blocks, prior to programming a memory block having no programmed sub-blocks from among the memory blocks, according to the detection result. Embodiments also include programming the write data at a sub-block, closest to a common source line, from among unprogrammed sub-blocks of the memory block. Embodiments also include erasing at least one sub-block that is farthest from the common source line, prior to erasing other sub-blocks from among the programmed sub-blocks in the memory block. Embodiments also include selectively programming or erasing sub-blocks according to read merge times.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the NAND cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells. The second erase verify operation is an operation that applies the verify read voltage to a second group of memory cells different from the first group of memory cells, and applies a second read pass voltage different from the first read pass voltage to memory cells other than the second group of memory cells.

Abstract: A nonvolatile semiconductor memory device according to one embodiment comprises: a memory cell array comprising a plurality of NAND strings, each NAND string comprising a memory string comprising a plurality of memory cells and a dummy transistor; a plurality of word lines; a dummy word line; a plurality of bit lines; a source line; and a control circuit performing an erase sequence, the erase sequence repeating an erase operation to the memory cells and the dummy transistor and an erase verify operation of confirming whether the memory cells and the dummy transistor are changed to an erased state. The control circuit is configured to be able to perform, when the erase verify operation is unpassed, a dummy transistor erase operation of selectively changing the dummy transistor to an erased state and a dummy transistor erase verify operation of confirming whether the dummy transistor is changed to an erased state.

Abstract: A non-volatile semiconductor storage device includes a memory cell array where memory cells are arranged in a matrix shape; and a control unit which erases the memory cell by applying an erasing voltage to a well side of the memory cell and preliminarily erases the memory cell by applying a preliminary erasing voltage to the well side of the memory cell before the erasing while applying a voltage, which is higher than the voltage during the erasing, to a control gate electrode of the memory cell.

Abstract: A nonvolatile memory device includes a gate structure including a select gate formed over a substrate and a memory gate formed on one sidewall of the select gate and having a P-type channel, a drain region formed in the substrate at one sidewall of the gate structure and overlapping a part of the memory gate, and a source region formed in the substrate at the other sidewall of the gate structure and overlapping a part of the select gate. The memory gates include a grid of rows and columns with bits of 1's and 0's selectively forming a memory in a nonvolatile memory device.

Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.

Abstract: Provided are a non-volatile memory device and a method for erasing the non-volatile memory device having vertical channel layers formed with different widths varying by height and a plurality of memory cells stacked along the vertical channel layers, the method including increasing potentials of the vertical channel layers, and when potentials of word lines connected to the memory cells are increased, erasing the memory cells while lowering the potentials of the word lines beginning from a word line positioned in an area in which a width of the vertical channel layer is wide to a word line positioned in an area in which the width of the vertical channel layer is narrow.

Abstract: In a method of operating a nonvolatile memory device having a substrate and first through n-th word lines stacked in a direction perpendicular to the substrate, first through k-th word line voltages are applied to first through k-th word lines, respectively, which are formed adjacent to the substrate, among the first through n-th word lines. (k+1)-th through n-th word line voltages are applied to (k+1)-th through n-th word lines, respectively, which are formed above the first through k-th word lines, among the first through n-th word lines. An erase voltage, which is higher than the first through n-th word line voltages, is applied to the substrate, where n represents an integer equal to or greater than two, and k represents a positive integer smaller than n. Each of the (k+1)-th through n-th word line voltages is lower than each of the first through k-th word line voltages.

Abstract: An apparatus, system, and method are disclosed for managing erase operations for a data storage medium. A method includes determining whether a use threshold for one or more non-volatile storage cells is satisfied. A method includes performing a default erase operation for the one or more storage cells in response to determining that the use threshold is not satisfied. A method includes performing an extended erase operation for the one or more storage cells in response to determining that the use threshold is satisfied. An extended erase operation may include a greater number of erase pulse iterations than a default erase operation.

Abstract: Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

Abstract: A data erasing method of a solid state drive is provided. The solid state drive includes a memory module. The memory module includes a block. A data to be erased is stored in the block. The data erasing method includes steps of performing a first erasing operation to erase the block, programming the block after the first erasing operation, and performing a second erasing operation to erase the block.

Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal.

Abstract: A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.

Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.

Abstract: A data writing method, a memory storage device, and a memory controlling circuit unit are provided. The writing method includes: grouping logical erasing units into a first region and an second region; determining if a first logical erasing unit which a host system intends to write belongs to the first region or the second region; if the first logical erasing unit belongs to the first region, writing data to a spare physical programming unit, wherein the physical erasing unit to which the spare physical programming belongs further stores data belonging to another logical erasing unit; if the first logical erasing unit belongs to the second region, writing data to a physical erasing unit in which all the valid data belong to the first logical erasing unit. Accordingly, a speed of sequential writing is guaranteed to be greater than a target value.

Abstract: A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line supplied with an erase voltage; and an erase gate selection switch formed between the first memory cells and the second memory cells, wherein the erase gate selection switch connects the global erase gate line to the first erase gate line or the second erase gate line according to an erase control signal.

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command.

Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Abstract: A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string.

Abstract: According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract: A method for erasing a first sub-block of a plurality of sub-blocks included in a block of a non-volatile memory device, wherein the first sub-block includes at least one word line, includes applying an erase voltage to a substrate, applying a third voltage lower than the erase voltage to the word line of the first sub-block, applying a first voltage at least one word line adjacent to the word line of the first sub-block, and applying a second voltage that is the same as or similar to the erase voltage to the other word lines, where the first voltage has a level between the third voltage and the second voltage.

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract: A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

Abstract: A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.

Abstract: An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

Abstract: A memory module includes volatile memory and non-volatile memory. The module includes logic to check if a non-volatile memory comprises un-erased areas, and if the non-volatile memory comprises un-erased areas, to elevate a backup capacitor potential above a predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory. The module includes logic to ERASE the un-erased areas and to return the capacitor to the predetermined operating potential after the ERASE is complete.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.

Abstract: A method of operating a semiconductor device includes programming one of a drain dummy cell and a source dummy cell which are included in a cell string; and coupling a bit line to the cell string in response to program states of the drain dummy cell and the source dummy cell and a voltage level applied to a drain dummy line coupled to a gate of the drain dummy cell and a source dummy line coupled to a gate of the source dummy cell.

Abstract: The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of ?7V˜?10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC?6.5V˜VCC?4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V.

Abstract: A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in the semiconductor substrate. The control unit, during an erase operation where electric charges written in the charge storage region are extracted to the channel region, periodically varies a voltage which is to be applied between the control gate and the channel region.

Abstract: A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.

Abstract: A semiconductor memory device is operated by forming channels in a cell string including a plurality of memory cells and coupled between a bit line and a source line, applying first and second erase voltages having different levels to the channels through the bit line and the source line, respectively, and applying a first word line voltage to at least one word line among word lines coupled to the plurality of memory cells.

Abstract: A method of erasing charge trap devices includes applying a first erase voltage to the charge trap devices; applying an erase verify voltage to the charge trap devices; performing a current first fail bit check operation including comparing a first number of charge trap devices, which are determined to be an erase fail based on the erase verify voltage, to a first reference value and determining a pass or fail based on the comparison result; when the current first fail bit check operation is determined to be a fail, determining whether a previous first fail bit check operation performed during a previous erase loop was passed or not; and when the previous first fail bit check operation performed during the previous erase loop was passed, setting a third erase voltage to a same level as a second erase voltage used during the previous erase loop.

Abstract: A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.

Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.

Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.