Abstract: Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.

Abstract: A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

Abstract: According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.

Abstract: Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.

Abstract: A flash memory with low power consumption and rapid operations is disclosed, including a memory array of memory cells, a word line selection circuit for selecting a row of cells, a current-type sensing circuit electrically connected with each bit line for sensing the current of a selected bit line, and an erase unit erasing the cells in a selected block of the array. The erase unit includes: an erase sequence that determines whether the current of each bit line in the erased block is larger than a first value and ends the erasure if the result is “yes”, and a soft-program sequence that performs a soft program verification, which applies a soft-program voltage to all word lines in the erased block and determines whether the current of each bit line is lower than a second value, and ends the soft programming if the result is “yes”.

Abstract: A nonvolatile memory cell array is divided into first and second cell arrays, the page buffer circuit is arranged between the first and second cell arrays, a second latch circuit is arranged by the outside edge section of the first cell array, and the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array. The data writing to the first or second cell array is controlled by transmitting the writing data to the page buffer circuit via the global bit line from the second latch circuit, after the writing data is latched in the second latch circuit. The data reading of outputting the data read from the first or second cell array to the external circuit is controlled by transmitting data to the second latch circuit from the page buffer circuit via the global bit line.

Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.

Abstract: A method includes initiating a read process for a memory array of an electronic memory device to make data available at an I/O buffer of the electronic memory device for access by a controller. A method includes signaling completion of a read process prior to completion of one or more stages of the read process at a memory array.

Abstract: Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells.

Abstract: Apparatuses, systems, and methods are disclosed to manage non-volatile media. A method includes determining a configuration parameter for a set of storage cells of a non-volatile recording medium. A method includes reading data from a set of storage cells using a determined configuration parameter. A method includes adjusting a configuration parameter based on read data.

Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.

Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.

Abstract: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.

Abstract: A memory system comprises a nonvolatile memory and a phase change memory. The memory system can be operated by reading operation information of the nonvolatile memory from the phase change memory, adjusting voltage parameters of the nonvolatile memory based on the read operation information, and performing an operation of the nonvolatile memory based on the adjusted voltage parameters.

Abstract: A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively.

Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.

Abstract: A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.

Abstract: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.

Abstract: A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage. The control circuit is configured to, during the erase operation, set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the second voltage differing from the first voltage. In addition, the control circuit is configured to, during the erase operation, apply in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of dummy memory transistors in a dummy memory string, and apply a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks which store data. Each of the blocks is an erase unit. The controller controls an operation of the nonvolatile memory. The controller executes writes and erases with respect to a first block of the blocks in the nonvolatile memory for the first number of times during a first period. The controller executes writes and erases with respect to other blocks for the second number of times smaller than the first number of times during the first period.

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage.

Abstract: A memory cell, a memory array and an operation method are disclosed herein. The memory cell includes a substrate with a first conductivity type, a first doped region with a second conductivity type, a second doped region with the second conductivity type, a first floating gate, a second floating gate and a word gate. The first and the second doped region are disposed in the substrate. The first floating gate is disposed on the substrate and electrically coupled to the first doped region. The second floating gate is disposed on the substrate and electrically coupled to the second doped region. The word line gate is disposed on the substrate and between the first and second doped region, wherein the word gate includes a first part extending over the first floating gate and a second part extending over the second floating gate.

Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

Abstract: A method is provided for programming a multi-level cell flash memory device. The programming method includes programming a first memory cell of the multi-level call flash memory device to one of first through i-th program states, wherein i is a positive integer, by applying a first program pulse to the first memory cell in a first type programming operation, and programming a second memory cell to one of i+1-th through j-th program states, wherein j is an integer equal to or greater than three, by applying a second program pulse to the second memory cell in a second type programming operation. At least one of a second step voltage, a second bit-line forcing voltage and a second verification operation of the second type programming operation is different from a first step voltage, a first bit-line forcing voltage, and a first verification operation of the first type programming operation, respectively.

Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Abstract: A semiconductor memory device and a method of operating the same are provided. The method includes performing an overall erase operation such that each threshold voltage of all memory cells connected to even word lines and odd word lines in a selected memory cell block are lower than a first target level, performing an erase operation such that each threshold voltage of the memory cells connected to the even word lines are lower than a second target level which is lower than the first target level, and performing an erase operation such that each threshold voltage of the memory cells connected to the odd word lines are lower than the second target level.

Abstract: A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

Abstract: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.

Abstract: A system and method for reading memory cells in a multi-level cell memory device. A set of thresholds may be received for reading a current page of the memory cells. The set of threshold may include hard decision thresholds for hard decoding, soft decision thresholds for soft decoding, erase thresholds for erase decoding and/or other combinations of thresholds. The set of thresholds may be divided into a plurality of groups of thresholds. The current page may be simultaneously read using multiple thresholds, where each of the multiple thresholds is divided into a different group of thresholds.

Abstract: A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.

Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.

Abstract: Provided is a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are disposed on a substrate, arranged periodically and extended along a first direction. First inter-poly dielectric films are disposed on the substrate and respectively beneath the first word lines. Second inter-poly dielectric films are disposed on the substrate and respectively beneath the second word lines, wherein the first inter-poly dielectric films are thinner than the second inter-poly dielectric films. A floating gate is disposed between the substrate and each of the first and second inter-poly dielectric films. A tunnel oxide film is disposed between the substrate and each of the floating gates. Bit lines are disposed above the first and second word lines and extended along a second direction different from the first direction.

Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.

Abstract: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.

Abstract: An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

Abstract: Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).

Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

Abstract: In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.

Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.

Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.

Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.

Abstract: A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase operations, thus reducing wear, and providing higher endurance. Flags indicate whether blocks are recycled, and what parameters to use in programming and reading the blocks.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state.

Abstract: A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well.

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command.

Abstract: The semiconductor memory device includes a memory cell block including a plurality of memory cells, a peripheral circuit section configured to perform an erase loop including a supply operation supplying an erase voltage and an erase verification operation to erase data stored in the memory cells, a fail bit counter configured to count the number of memory cells not erased in an erase operation among the memory cells to generate a count signal based on a fail count corresponding to a counting result in the erase verification operation, and a controller configured to control the peripheral circuit section to set a new erase voltage by increasing an erase voltage, used in a previous erase loop, by a first step voltage or decreasing the erase voltage by a second step voltage based on the fail count, and perform the erase loop using the new erase voltage.

Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.

Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.

Abstract: A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for an erase verify operation of the memory block selected from the memory blocks, and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed.