Sense/inhibit Patents (Class 365/196)
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Patent number: 8625370Abstract: A semiconductor integrated circuit includes a P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply, an input terminal connected to a gate terminal of the P-type MOS transistor and gate terminals of the two or more N-type MOS transistors, an output terminal which is a connection node between the P-type MOS transistor and one of the two or more N-type MOS transistors connected to the P-type MOS transistor, and one or more capacitors connected to the output terminal. The drive capability of the P-type MOS transistor is higher than the overall drive capability of the two or more N-type MOS transistors connected together in series. Therefore, a semiconductor integrated circuit is provided in which fluctuations in the delay time of a delay circuit caused by variations in transistor characteristics can be reduced.Type: GrantFiled: August 25, 2011Date of Patent: January 7, 2014Assignee: Panasonic CorporationInventor: Yoshinobu Yamagami
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Patent number: 8625374Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.Type: GrantFiled: December 18, 2012Date of Patent: January 7, 2014Assignee: SoitecInventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
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Publication number: 20140003165Abstract: A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.Type: ApplicationFiled: March 18, 2013Publication date: January 2, 2014Applicant: SK hynix Inc.Inventors: Doo Chan LEE, Jong Yeol YANG
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Patent number: 8605496Abstract: A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.Type: GrantFiled: June 3, 2011Date of Patent: December 10, 2013Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Suk Kyoung Hong
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Patent number: 8605517Abstract: A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.Type: GrantFiled: January 9, 2012Date of Patent: December 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Young-Don Choi
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Patent number: 8576631Abstract: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the plurality of memory cells. The data sense amplifier circuitry may comprise first amplifier circuitry and resistive circuitry, wherein the first amplifier circuitry and the resistive circuitry may form a feedback loop.Type: GrantFiled: March 1, 2011Date of Patent: November 5, 2013Assignee: Micron Technology, Inc.Inventor: Jean-Michel Daga
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Patent number: 8570819Abstract: A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is configured to selectively couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a first bit line in the array to selectively couple the first input of the first sense amplifier to the first bit line in the array, the first input of the second sense amplifier to the second bit line in the array, and the second inputs of the first and second sense amplifiers to a reference voltage.Type: GrantFiled: March 9, 2012Date of Patent: October 29, 2013Assignee: Actel CorporationInventors: John McCollum, Fethi Dhaoui
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Patent number: 8559250Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.Type: GrantFiled: May 14, 2012Date of Patent: October 15, 2013Assignee: Renesas Electronics CorporationInventors: Hidetoshi Ikeda, Koichi Takeda
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Patent number: 8553480Abstract: A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.Type: GrantFiled: May 20, 2011Date of Patent: October 8, 2013Assignee: Nanya Technology Corp.Inventor: One-Gyun Na
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Patent number: 8520458Abstract: A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.Type: GrantFiled: June 22, 2012Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: John A. Gabric, Mark C. Lamorey, Thomas M. Maffitt
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Patent number: 8514640Abstract: A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and tType: GrantFiled: February 28, 2011Date of Patent: August 20, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Miakashi, Katsuaki Isobe, Noboru Shibata
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Patent number: 8509003Abstract: A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.Type: GrantFiled: September 20, 2011Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chun Lin, Hung-Chang Yu, Yue-Der Chih
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Patent number: 8509013Abstract: Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.Type: GrantFiled: April 30, 2010Date of Patent: August 13, 2013Assignee: Micron Technology, Inc.Inventor: Raed Sabbah
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Patent number: 8509002Abstract: A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase.Type: GrantFiled: May 28, 2010Date of Patent: August 13, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Hyun Choi, Jin Seok Kwak, Seong Jin Jang
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Patent number: 8498169Abstract: A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.Type: GrantFiled: September 2, 2011Date of Patent: July 30, 2013Assignee: QUALCOMM IncorporatedInventors: Hari M. Rao, Esin Terzioglu, Sei Seung Yoon
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Patent number: 8472273Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.Type: GrantFiled: May 27, 2011Date of Patent: June 25, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Takayama, Akira Kotabe, Kiyoo Itoh, Tomonori Sekiguchi
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Patent number: 8467251Abstract: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories.Type: GrantFiled: September 14, 2012Date of Patent: June 18, 2013Assignee: STMicroelectronics (Rousset) SASInventor: Francesco La Rosa
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Patent number: 8467257Abstract: A circuit is usable to generate a sense amplifier enable (SAE) signal for a static random access memory (SRAM) circuit. The circuit includes a first tracking bit line, a second tracking bit line, a tracking cell, and a control logic circuit. The second tracking bit line is electrically connected to the first tracking bit line. The tracking cell has a driving terminal and a non-driving terminal, where the non-driving terminal is connected to the second tracking bit line, and the driving terminal is connected to the first tracking bit line and configured to selectively charge or discharge a voltage on the first tracking bit line in response to a control signal. The control logic circuit is coupled to the first tracking bit line and configured to generate the SAE signal in response to the voltage level on the first tracking bit line.Type: GrantFiled: December 20, 2011Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jack Liu, Yi-Wei Lin
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Patent number: 8451680Abstract: A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the memory cell array. The sense amplifier controller selectively connects one of the upper and lower memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower memory cell arrays are not selected but overdriven.Type: GrantFiled: June 22, 2011Date of Patent: May 28, 2013Assignee: Hynix Semiconductor Inc.Inventor: Young-Bo Shim
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Patent number: 8446786Abstract: The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting data particular quantization of data can include enabling a particular one of a plurality of different quantizations of data. The particular one of the plurality of quantizations of data can then be output.Type: GrantFiled: January 20, 2011Date of Patent: May 21, 2013Assignee: Micron Technology, Inc.Inventor: Theodore T. Pekny
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Patent number: 8441851Abstract: The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier.Type: GrantFiled: February 23, 2011Date of Patent: May 14, 2013Assignee: Lapis Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Patent number: 8437211Abstract: A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.Type: GrantFiled: November 1, 2010Date of Patent: May 7, 2013Assignee: Hynix Semiconductor Inc.Inventor: Byoung-Kwon Park
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Patent number: 8432737Abstract: When performing a word line leak test to determine a leak state of the word lines, the control circuit applies, from the voltage control circuit to the word lines connected to the memory cell array written with test pattern data, voltages corresponding to the test pattern data. Thereafter, it switches the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state. After a lapse of a certain time from switching of the transfer transistors to a nonconductive state, it activates the sense amplifier circuit to perform a read operation in the memory cell array. Then it compares a result of the read operation with an expectation value corresponding to the test pattern data.Type: GrantFiled: August 25, 2011Date of Patent: April 30, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Hitoshi Shiga
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Patent number: 8432762Abstract: A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.Type: GrantFiled: January 14, 2011Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Joung-Yeal Kim, Seong-Jin Jang, Jin-Seok Kwak
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Patent number: 8422325Abstract: A precharge control circuit includes a precharge voltage supply unit for generating a precharge voltage according to a voltage level of a precharge control signal, a voltage generator for generating an operating voltage for controlling the voltage level of the precharge control signal in response to a first enable signal and a voltage control signal, and a signal generator for fixing the precharge control signal to a specific voltage level in response to a second enable signal and for linearly changing the voltage level of the precharge control signal according to a slope, determined by a level of the operating voltage, when the second enable signal is disabled.Type: GrantFiled: June 7, 2011Date of Patent: April 16, 2013Assignee: SK Hynix Inc.Inventor: Jea Won Choi
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Patent number: 8416636Abstract: Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns.Type: GrantFiled: December 29, 2010Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Eric S. Carman, Philippe Bruno Bauser, Jean-Michel Daga
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Patent number: 8411505Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed at least by a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of said NVM unit with at least a given set voltage.Type: GrantFiled: November 12, 2010Date of Patent: April 2, 2013Assignee: EM Microelectronic-Marin SAInventor: David A. Kamp
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Patent number: 8406078Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.Type: GrantFiled: February 11, 2011Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek C. Tao, Young Seog Kim
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Patent number: 8400824Abstract: A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of data is achieved in a unit cell in response to a variation of resistance, a reference cell array configured to include a plurality of reference cells, each of which has the same structure as that of the unit cell, a global reference current generation circuit configured to generate a global reference current corresponding to a position of the reference cell so as to verify data stored in the reference cell array, and a sense-amplifier configured to compare a current flowing in the reference cell array with the global reference current during a write verification operation of the reference cell array, and thus sense data.Type: GrantFiled: December 28, 2010Date of Patent: March 19, 2013Assignee: Hynix Semiconductor Inc.Inventor: Kwang Myoung Rho
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Patent number: 8395960Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers.Type: GrantFiled: May 12, 2010Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek Tao
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Patent number: 8369167Abstract: A semiconductor device includes the following elements. A sense amplifier amplifies signal on a bit line. A column switch is between the bit line and a local input-output line. A sub-amplifier amplifies signal on the local input-output line. A write switch is between the local input-output line and a main input-output line. A write amplifier amplifies write data and supplies the amplified write data to the main input-output line when data write operation is performed. A test circuit activates the sense amplifier while the test circuit deactivating the sub-amplifier and the write amplifier when a data read operation is performed in test mode. The test circuit places the column switch and the write switch in conductive state.Type: GrantFiled: January 4, 2011Date of Patent: February 5, 2013Assignee: Elpida Memory, Inc.Inventor: Tomohiro Sawada
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Patent number: 8363473Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.Type: GrantFiled: November 14, 2011Date of Patent: January 29, 2013Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin
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Patent number: 8358552Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.Type: GrantFiled: May 27, 2010Date of Patent: January 22, 2013Assignee: SoitecInventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
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Patent number: 8339883Abstract: A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.Type: GrantFiled: November 17, 2010Date of Patent: December 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Je-min Yu, Byung-chul Kim, Jun-hyung Kim, Sang-joon Hwang
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Patent number: 8335117Abstract: Disclosed herein is a memory device including: first and second wires; memory cells including a variable-resistance storage element having a data storage state making a transition by a change of a voltage applied and an access transistor connected in series between the first and second wires; driving control sections controlling a direct verify sub-operation by applying a write/erase pulse between the first and second wires in a data write/erase operation respectively for causing a cell current to flow between the first and second wires through the memory cell for a transition of the data storage state; sense amplifiers sensing an electric-potential change occurring on the first wire in accordance with control on the direct verify sub-operation; and inhibit control sections determining whether or not to inhibit a sense node of the sense amplifier from electrically changing at the next sensing time on the basis of an electric potential appearing at the sense node at the present sensing time.Type: GrantFiled: January 13, 2010Date of Patent: December 18, 2012Assignee: Sony CorporationInventors: Makoto Kitagawa, Tsunenori Shiimoto
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Patent number: 8320190Abstract: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.Type: GrantFiled: October 11, 2011Date of Patent: November 27, 2012Assignee: Chip Memory Technology, Inc.Inventor: Wingyu Lueng
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Patent number: 8312238Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.Type: GrantFiled: April 18, 2007Date of Patent: November 13, 2012Assignee: RENESAS Electronics CorporationInventors: Rika Ono, Hitoshi Suzuki
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Patent number: 8310887Abstract: A semiconductor device includes a bit line, a memory cell coupled to the bit line, the memory cell being configured such that a current flowing there the memory cell is varied in accordance with information stored M the memory cell, a first transistor coupled at a control electrode thereof to the bit line, a second transistor coupled to the bit line and supplied at a control electrode thereof with a first control signal, a global bit line, and a third transistor coupled in series with the first sistor between a node and the global bit line, the third transistor supplied at a control electrode thereof with a second control signal.Type: GrantFiled: September 19, 2011Date of Patent: November 13, 2012Assignee: Elpida Memory, Inc.Inventor: Kazuhiko Kajigaya
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Patent number: 8305814Abstract: Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell.Type: GrantFiled: November 12, 2009Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Shahid Ali, Raviprakash Suryanarayana Rao
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Patent number: 8305815Abstract: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories.Type: GrantFiled: October 19, 2010Date of Patent: November 6, 2012Assignee: STMicroelectronics (Rousset) SASInventor: Francesco La Rosa
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Patent number: 8300459Abstract: A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduce the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.Type: GrantFiled: March 30, 2012Date of Patent: October 30, 2012Assignee: SanDisk Technologies Inc.Inventors: Shou-Chang Tsao, Yan Li
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Patent number: 8300480Abstract: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.Type: GrantFiled: October 4, 2010Date of Patent: October 30, 2012Assignee: Elpida Memory, Inc.Inventor: Kiyohiro Furutani
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Patent number: 8295113Abstract: Disclosed is a semiconductor device including: a first switch controlling connection between a first data line pair a second data line pair; a first amplifier connected to the first data line pair; a second switch controlling the connection between the second data line pair and a third data line pair; a second amplifier amplifying data on the second data line pair and delivering the amplified data to the third data line pair; a third amplifier connected to the third data line pair; and a switch control circuit controlling the second switch. Based upon a first control signal that controls precharging and equalization of the first data line pair, the switch control circuit renders the second switch conductive when precharging and equalization of the first data line pair is not carried out, and renders the second switch non-conductive when precharging and equalization of the first data line pair is carried out.Type: GrantFiled: October 27, 2010Date of Patent: October 23, 2012Assignee: Elpida Memory, Inc.Inventor: Yuji Nakaoka
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Patent number: 8284605Abstract: An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell.Type: GrantFiled: December 27, 2010Date of Patent: October 9, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Rieko Tanaka, Makoto Iwai
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Patent number: 8279692Abstract: To provide a semiconductor device including switch transistor provided between a sub-data line and a main data line. Upon transferring data, the semiconductor device supplies a potential of a VPP level to a gate electrode of the switch transistor when causing the switch transistor to be a conductive state, and supplies a potential of a VPERI level to the gate electrode when causing the switch transistor to be a non-conductive state. According to the present invention, because a potential of the gate electrode is not decreased to a VSS level when causing the switch transistor to be a non-conductive state, it is possible to reduce a current required to charge and discharge a gate capacitance of the switch transistor. Furthermore, because the VPP level is supplied to the gate electrode when causing the switch transistor to be a conduction state, a level of a signal after transfer never drops down by the amount of the threshold voltage.Type: GrantFiled: October 22, 2010Date of Patent: October 2, 2012Assignee: Elpida Memory, Inc.Inventor: Yoshinori Matsui
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Patent number: 8264895Abstract: A method of sensing a data value stored at a resistance based memory is disclosed. The method includes receiving a data signal from a data cell. The data cell includes a resistance based memory element. A reference signal is received from a reference circuit. The reference circuit includes a resistance based memory element. The data signal is converted to a data output signal having a first frequency. The reference signal is converted to a reference output signal having a second frequency. A first output signal is generated when the first frequency exceeds the second frequency. A second output signal is generated when the second frequency exceeds the first frequency.Type: GrantFiled: November 30, 2009Date of Patent: September 11, 2012Assignee: QUALCOMM IncorporatedInventor: Hari Rao
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Patent number: 8254194Abstract: A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a correspondingType: GrantFiled: October 25, 2010Date of Patent: August 28, 2012Assignee: STMicroelectronics S.r.l.Inventors: Antonio Giambartino, Michele La Placa, Ignazio Martines
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Patent number: 8243524Abstract: A semiconductor storage device has a sense amplifier.Type: GrantFiled: March 15, 2010Date of Patent: August 14, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuya Suzuki, Toshiki Hisada, Yoshikazu Hosomura
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Patent number: 8238137Abstract: A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on.Type: GrantFiled: September 17, 2009Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Hashimoto, Daisaburo Takashima
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Patent number: 8238184Abstract: A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node.Type: GrantFiled: March 2, 2011Date of Patent: August 7, 2012Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Yi-Te Shih, Chun-Hsiung Hung