Abstract: A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation.

Abstract: A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse, and a storage unit for storing the decoded address signal, the decoded command signal and a data signal in response to the suspend pulse and providing the decoded address signal, the decoded command signal and the decoded data signal as a stored address signal, a stored command signal and a stored data signal, respectively, in response to the resume pulse.

Abstract: Method and device for controlling a memory access and correspondingly configured semiconductor memory A method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells of the memory cells of the memory such that a content of the at least one memory cell can be read out via the at least one dummy bit line. The at least one memory cell can be set to a predetermined potential. Each of said plurality of memory cells is connected to the at least one dummy bit line and to at least one dummy word line such that each of said plurality of memory cells can be set to the predetermined potential by means of the at least one dummy bit line and by means of the at least one dummy word line.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal.

Abstract: A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.

Abstract: Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed.

Abstract: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.

Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.

Abstract: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

Abstract: A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.

Abstract: A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node.

Abstract: A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.

Abstract: A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.

Abstract: A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as the ramp voltage is being applied, generating a respective control signal in response to sensing a predetermined threshold current along a respective bitline in the memory array, wherein each transistor in the memory array is in communication with a respective bitline in the memory array; and for each transistor in the memory array, latching a current value of the incrementing digital code in response to the respective control signal corresponding to the transistor being generated. The current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor.

Abstract: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.

Abstract: An exemplary embodiment of an efuse device is provided, operating in a write mode and a read mode and comprising a source line, a cell, a blow device, and a sensing circuit. The cell has a first terminal coupled to the source line and a second terminal. The blow device is coupled between the second terminal of the cell and a ground terminal. The blow device is turned on in the read mode. The sensing circuit is coupled to the first terminal of the cell and the ground terminal, and is arranged to determine a state of the cell.

Abstract: Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

Abstract: A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memory cell to cause the nonvolatile memory cell to output a plurality of pieces of readout data, and an OK/NG determination circuit for comparing the plurality of pieces of readout data to determine whether the nonvolatile memory cell is stable or not.

Abstract: A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.

Abstract: Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while preserving state-retention abilities of remaining ones of the plurality of memory cells. Weakening may include adjusting one or more resistances between one or more power supplies and the plurality of memory cells. Dynamic control may be selectively performed on portions of each of the memory cells in response to an input data logic state. Dynamic control may reduce a write contention within the subset of memory cells without disabling state-retention abilities of remaining ones of the plurality of memory cells, and may improve write response times of the memory cells.

Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.

Abstract: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.

Abstract: A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-memory banks are included in different row memory cell arrays, and each of the sub-memory banks includes multiple physical sectors. The sense amplifiers are dedicated to the sub-memory banks, respectively.

Abstract: An apparatus, system, and method are disclosed for detecting the formation of a short between a magnetoresistive (“MR”) head and a head substrate. The apparatus is presented with a logic unit containing a plurality of modules configured to functionally execute the necessary steps of generating a baseline electric potential level between a head substrate and ground, monitoring the level of the electric potential between the head substrate and ground, and detecting the formation of a short circuit between the MR head and the head substrate by detecting a change in the electric potential level monitored by the monitoring module from the baseline level to a predetermined threshold level. Beneficially, such an apparatus, system, and method would reduce read errors on the magnetic tape storage system, the time and resources required to recover from such errors, and allow for preventative measures to obviate contamination short related failures of tape drive systems.

Abstract: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

Abstract: A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal reading from the memory cell is reduced, wherein the amplifier amplifies a signal outputted from an input/output terminal through the use of a single MOS transistor that has a single-ended structure.

Abstract: Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. Another ROM includes a first transistor comprising a gate, electrically connected to a word line to provide a read signal, a drain, electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal.

Abstract: A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data storage device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the memory control circuit with access to a set of common data. A power-reservoir circuit includes two or more capacitor cells that respectively hold charge to provide operating power to the data storage device to permit transfer of the data from the volatile memory circuit to the solid-state memory circuit in the event of a power loss. A detection circuit is connected to a center tap between the capacitor cells and uses the tap to detect characteristics of the cells relative to one another, and to provide an output that can be used to characterize the cells' electrical characteristics relative to one another.

Abstract: A high-density dynamic memory device with compact sense amplifier circuit is described. The memory device achieves high density through the use of a compact sense amplifier circuit that employs a single transistor to sense stored dynamic data. Functionality of the device is enabled by an architecture and method of operation that support a compact sense amplifier circuit. Enabling techniques include sequential sensing of memory columns, a two-pass write operation, a two-step refresh operation, a reference scheme that uses reference data stored in regular memory cells, and the application of digital signal processing to determine sensed data and cancel crosstalk noise.

Abstract: A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation.

Abstract: Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier.

Abstract: A read data path circuit for use in the semiconductor memory device includes a bit line sense amplifier, a local input/output line sense amplifier, a column selection unit operationally coupling a bit line pair with the local input/output line pair in response to a column selection signal, where the bit line pair is coupled to the bit line sense amplifier and the local input/output line pair is coupled to the local input/output line sense amplifier, and a bit line disturbance preventing unit configured to equalize signal levels of the local input/output line pair before the column selection signal is activated, and configured to sense and amplify signal levels of bit line data transferred to the local input/output line pair after the column selection signal is activated.

Abstract: A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.

Abstract: According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A memory refresh system includes a comparative detection circuit, a logic circuit, and a timing circuit. The comparative detection circuit detects a voltage of the storage capacitor of a memory cell of the memory and generates a corresponding digital code by comparing the voltage with a reference voltage. Each memory cell has a corresponding digital code. The combination of the digital codes of the memory cells forms a first state. After a specific period of time, the voltages of the storage capacitors of the memory cells are once detected by the comparative detection circuit, and corresponding digital codes are generated and combined to form a second state. The logic circuit compares the first state and the second state to determining whether or not to change the refresh period of a refresh period detecting process. The timing circuit changes the refresh period according to the determination result of the logic circuit.

Abstract: A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines.

Abstract: A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the memory cell array. The sense amplifier controller selectively connects one of the upper and lower memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower memory cell arrays are not selected but overdriven.

Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other.

Abstract: A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by comparing data read from the nonvolatile memory with the enabled data for comparison, and a path configured to output the result of comparison output from the check circuit to outside the semiconductor device, wherein no path to output the data read from the nonvolatile memory to outside the semiconductor device is in existence.

Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.

Abstract: A memory includes memory cells, wherein during a first write operation in which first logical data is written in all memory cells connected to a first word line, a source line driver and a word line driver, the source line driver shifts a voltage of a selected source line corresponding to the first word line in a direction away from the voltage of the first word line and the word line driver shifts a voltage of a second word line in a same direction as a transition direction of voltage of a selected source line, and during a second write operation in which second logical data is written in a selected cell connected to the first word line, the source line driver and the word line driver shift voltages of the selected source line and the second word line in a direction approaching the voltage of the first word line.

Abstract: A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode.

Abstract: In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.