Abstract: A memory device and a memory peripheral circuit are provided. The memory peripheral circuit includes a redundancy column data circuit and a column selection control circuit. The redundancy column data circuit is configured to provide a redundancy test mode data signal and a column address signal. The column address signal includes a redundancy column address signal. The column selection control circuit includes a column decoder and a redundancy column decoder. The column decoder disables a bad column address of a main memory block according to the redundancy test mode data signal and the redundancy column address signal. The redundancy column decoder latches the redundancy column address signal, compares the column address signal with the latched redundancy column address to obtain a comparison result, and enables a redundancy column address of a redundancy memory block according to the comparison result.

Abstract: The present invention provides a security system, and methods useful for vehicle CAN bus communication mapping and attack originator identification, comprising: a CAN Bus Monitor, (CBM), configured to monitor the CAN bus communication comprising one or more frames, to and/or from at least one Electronic Control Unit, (ECU); a characterization module in communication with the CBM, configured to generate at least one characteristic for the monitored communication from each the ECU and at least one characteristic for each communication frame; (c) a comparator unit in communication with the characterization module, configured to compare one or more the characteristics of at least one frame against characteristics of each the ECU communication in order to detect at least one anomaly; and, (d) one or more Identification module in communication with the comparator, configured to identify at least one ECU originating an attack on the CAN bus.

Abstract: A memory device includes a plurality of memory cell arrays, a plurality of data transmitters corresponding to the plurality of memory cell arrays, respectively, and suitable for transmitting data read in parallel from the corresponding memory cell arrays, and a test circuit suitable for selecting one data transmitter among the plurality of data transmitters, and sequentially outputting data transmitted in parallel from the selected data transmitter to one data input/output pad among a plurality of data input/output pads, during a test mode.

Abstract: A testing method for a semiconductor memory includes determining which memory blocks are defective based on the number of defective cells in the block. The method includes determining whether the number of defective blocks exceeds a first threshold value and judging the semiconductor memory to be defective if the number of defective blocks is equal to or greater than the first threshold value. The method also includes comparing the number of defective blocks with a second threshold value equal to or less than the first threshold value and repeating the process of measuring and judging of the memory cells and memory blocks until the number of defective blocks is at least equal to the second threshold value, and then managing access to the defective blocks in a different manner from accesses to other blocks.

Abstract: Embodiments include a system, method, and a computer program product for notifying a technician when a repair task the technician is addressing may be negatively impacted by a nearby fault and/or if the technician is qualified to repair a nearby fault. The technician is qualified if the technician has the necessary skills, parts (e.g., materials), and/or equipment (test equipment) required to repair the nearby fault. In addition, embodiments include receiving and responding to queries from a technician to: determine whether any of the repair tasks associated with the technician's assigned tickets are futile tasks based on newly received faults or pending tickets; and determine whether the querying technician is qualified to address (e.g., repair) any newly received faults or pending tickets.

Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Abstract: A method includes receiving, by a host server on a public cloud including one or more physical data centers associated with one or more logical zones, a pairing request by a client device associated with a private cloud, allocating, by the host server, access to resources on the one or more physical data centers to the client device, and pairing, by the host server, the private cloud to the public cloud based on receiving an identity provider token from an identity provider.

Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Abstract: Provided herein is a memory device and a method of operating the memory device. The memory device may include a one or more memory blocks, one or more peripheral circuits configured to perform an erase operation and a threshold voltage distribution scan operation on a selected memory block, and a control logic configured to control the one or more peripheral circuits, and determine the selected memory block to be a normal memory block or a defective memory block based on a result of the threshold voltage distribution scan operation.

Abstract: A semiconductor switch according to an embodiment includes: a first sub-switch and a second sub-switch. A first input signal is inputted into the first sub-switch and a second input signal is inputted into the second sub-switch. The first input signal is either a first voltage or a third voltage, the second input signal is either a second voltage or a fourth voltage, the second voltage is lower than the first voltage, the third voltage is lower than the first voltage and the fourth voltage is lower than the third voltage. The second voltage is inputted into the second sub-switch when an output from the first sub-switch is outputted from the semiconductor switch, and the third voltage is inputted into the first sub-switch when an output from the second sub-switch is outputted from the semiconductor switch.

Abstract: Provided is a semiconductor device including a regulator that generates a first voltage and applying the first voltage to a first line; an external terminal that is connected to the first line and externally connects an external component; and a test circuit that inspects a connection state of the external component. The test circuit includes a test discharge execution unit that is configured, upon receiving a test start signal, to stop the operation of the regulator and discharge the external component by connecting the first line to a predetermined potential; and a discharge duration measurement unit that measures a time required from the reception of the test start signal to a drop of the voltage of the first line below a predetermined second voltage, as a discharge duration of the component, and generate discharge duration information about the discharge duration.

Abstract: A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST.

Abstract: Techniques change a type of a storage system. The techniques involve: determining, from a resource pool associated with the storage system, a set of used disks utilized by one stripe of the storage system and a set of spare disks unutilized by the stripe; determining a neighboring relationship between spare disks in the set of spare disks and used disks in the set of used disks, the neighboring relationship indicating a number of adjacencies between the spare disks and the used disks in a period of history time; selecting, based on the neighboring relationship, one spare disk from the set of spare disks as an expanded disk of the stripe; and updating the stripe of the storage system using extents of the expanded disk. Accordingly, the type of the storage system may be changed based on the existing resources to improve reliability and operating efficiency.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reclaiming one or more portions of storage resources in a computer system serving one or more virtual computing instances, where the storage resources in the computer system are organized in clusters of storage blocks. In one aspect, a method includes maintaining a respective block tracking value for each storage block that indicates whether a call to reclaim the storage block is outstanding; determining, from the block tracking values, a respective cluster priority value for each of the clusters based on a count of storage blocks in the respective cluster for which a call to reclaim is outstanding; and reclaiming a first portion of storage resources in the computer system in accordance with the cluster priority values.

Abstract: The present disclosure relates to a memory device including a BIST circuit and an operating method thereof. The memory device includes a comparison circuit comparing test pattern data with sensing data to generate a comparison signal, a status information generating circuit generating a fail mask signal by marking data in which a failure occurs in the sensing data in response to the comparison signal, a column address generating circuit generating column addresses sequentially increasing in response to an input/output strobe signal, a latch enable signal generating circuit generating a latch enable signal in response to the fail mask signal, and an input/output circuit receiving the column addresses and selectively latching a column address in which a failure occurs among the column addresses in response to the latch enable signal.

Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.

Abstract: There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Abstract: Provided is a phase difference film formed of a resin containing a polymer having crystallizability, and having an NZ factor of less than 1. A production method of the phase different film includes: bonding a second film to one or both surfaces of a first film formed of a resin containing the polymer having crystallizability and having a glass transition temperature Tg (° C.) and a melting point Tm (° C.), to obtain a third film, the second film having a shrinkage percentage in at least one direction at (Tg+30)° C. of 5% or more and 50% or less; heating the third film to Tg° C. or higher and (Tg+3)° C. or lower to obtain a fourth film; and heating the fourth film to (Tg+50)° C. or higher and (Tm?40)° C. or lower.

Abstract: For controlling device performance based on temperature differential, an apparatus includes a plurality of sensors positioned at different locations of the apparatus, a controller, and a memory that stores code executable by the controller. The controller determines a plurality of temperatures using the plurality of sensors. Here, each temperature corresponds to a different location of the apparatus. The controller calculates a temperature differential for the apparatus using the plurality of temperatures. The controller maintains device performance in response to the temperature differential being within a threshold amount and throttles device performance in response to the temperature differential exceeding the threshold amount.

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

Abstract: In various example embodiments, a system and method for enhancing a user's on-line experience by utilizing a computer-implemented on-line session trace system is provided. The on-line session trace system is provided in connection with an on-line trading platform. The on-line session trace system records and stores a state of an on-line session associated with a user identification and permits a user associated with the user identification to commence a further on-line session from a state corresponding to the saved state of a previous on-line session.

Abstract: An indication that a test resource of a test platform has failed can be received. The test resource can be associated with performing a portion of a test of memory components. A characteristic of the test resource that failed can be determined. Another test resource of the test platform can be identified based on the characteristic of the test resource that failed. The portion of the test of memory components can be performed based on the another test resource of the test platform.

Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines. Additionally, the memory device may include one or more counters to assist in accessing the memory cells of the memory array.

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

Abstract: Exemplary methods, apparatuses, and systems include a controller that determines that a group of memory cells of a first memory device has an elevated error rate. In response to determining the elevated error rate, the controller identifies a spare group of memory cells. The group of memory cells and the spare group of memory cells span a first dimension and a second dimension that is orthogonal to the first dimension. The controller reads a portion of a logical unit from the group of memory cells along the first dimension of the group. The controller further determines that the group of memory cells and the spare group of memory cells have strong disturb effects in different dimensions and, in response to that determination, writes the portion of the logical unit to the spare group of memory cells along the second dimension of the spare group.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Abstract: A semiconductor device and a system including the semiconductor device are disclosed, which relate to a technology for detecting a defective or failed part during a probe test of the semiconductor device. The semiconductor device includes a test controller configured to perform counting of a read flag signal during activation of a test signal and to control a data mask signal to be toggled at an N-th activation time of the read flag signal. The semiconductor device further includes a cell array configured to receive and store an output signal of the test controller through a data line during a write operation and to output the stored data to a test device during a read operation.

Abstract: Methods and systems for encoding digital information in nucleic acid (e.g., deoxyribonucleic acid) molecules without base-by-base synthesis, by encoding bit-value information in the presence or absence of unique nucleic acid sequences within a pool, comprising specifying each bit location in a bit-stream with a unique nucleic sequence and specifying the bit value at that location by the presence or absence of the corresponding unique nucleic acid sequence in the pool But, more generally, specifying unique bytes in a bytestream by unique subsets of nucleic acid sequences. Also disclosed are methods for generating unique nucleic acid sequences without base-by-base synthesis using combinatorial genomic strategies (e.g., assembly of multiple nucleic acid sequences or enzymatic-based editing of nucleic acid sequences).

Abstract: A semiconductor memory apparatus includes a test decoding select circuit. The test decoding selective circuit is configured to generate a normal decoding enable signal, a redundancy decoding enable signal, and a dummy decoding enable signal, in response to a test entry signal, a test code, and an active signal.

Abstract: A system and a method for error-correction code (“ECC”) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: According to one embodiment, there is provided an integrated circuit. The integrated circuit includes a plurality of SRAMs including a first SRAM and a second SRAM, and a switching unit that enables switching between an electrically connected state where a first circuit portion on a source side of the first SRAM is electrically connected with a second circuit portion on a source side of the second SRAM and an electrically disconnected state where the first circuit portion is electrically disconnected from the second circuit portion.

Abstract: A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages.

Abstract: Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.

Abstract: A computer-implemented method includes receiving probability distribution function (PDF) data corresponding to bit-error-rate (BER) data for each of a plurality of data blocks within a qualified set of NVRAMS, collecting non-exhaustive bit-error-rate data for each of the data blocks on a tested NVRAM to produce non-exhaustive test data for each of the data blocks, determining a plurality of stable data blocks on the tested NVRAM based on the non-exhaustive test data and the probability distribution function data for each of the data blocks, determining, from the non-exhaustive test data, an inferior data block for the stable data blocks on the tested NVRAM, collecting exhaustive bit-error-rate data on the inferior data block to produce exhaustive test data for the tested NVRAM, and routing the tested NVRAM according to the exhaustive test data. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.

Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.

Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract: A memory device and a method for test reading and writing thereof are provided. A precharge voltage control circuit is based on the precharge reference voltage to provide a first precharge voltage and a second precharge voltage. A sense amplifier circuit is coupled between a bit line and a complementary bit line and configured to sense data of a memory cell coupled to the bit line, and also coupled to the precharge voltage control circuit to make the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage respectively, the first precharge voltage and the second precharge voltage are on the same voltage level during the precharge operation, but during a test write sensing period and a test read sensing period after the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are different.

Abstract: A method for detecting a flash memory array includes a plurality of word lines, a plurality of bit lines, and a source line, includes executing a first detection process. The first detection process includes: applying a first positive voltage to a P-type well of the flash memory array; applying a ground to all the word lines; floating the bit lines and the source line; determining whether a leakage current flowing through the P-type well exceeds a leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is short-circuited with at least one of the bit lines or the source line.

Abstract: A system for controlling a solid state drive is disclosed that includes a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks. A pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices. An effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device.

Abstract: An optical decoding system is applied to mode conversion of a memory. The optical decoding system includes an optical sensor and a processor. The optical sensor is utilized to sense an intensity of a pattern, and variation of the intensity containing an activation code. The processor is electrically connected with the optical sensor. The processor is adapted to analyze the variation of the intensity and to switch the memory from a normal mode to a configuration mode in accordance with the activation code. Normal operation of the memory is paused while the memory is set in the configuration mode.

Abstract: In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Abstract: An input/output (I/O) interface-based signal output method and apparatus. The method includes determining whether a voltage output by a core power supply domain of a first chip is lower than a preset threshold voltage of the first chip, and when the voltage output by the core power supply domain is lower than the threshold voltage, generating a first level signal according to a control function of the first chip over a second chip, where the first level signal is used to enable the second chip to be in an ignoring state after the second chip receives the first level signal, and sending the first level signal to the second chip through an I/O interface, where the ignoring state indicates that the second chip ignores a control signal and a data signal that are sent by the first chip where the method improves stable performance of a chip product.