Abstract: A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically.

Abstract: Systems, methods, and computer program products to perform an operation comprising determining, based on actual coverage point data for a first time interval and expected coverage point data, that a first set of lines of source code associated with the actual and expected coverage point data have not been executed by a system, instantiating, in the system, an action code associated with the first set of lines of source code and an effect code associated with the action code, and determining, based on a final state of the effect code, whether the action code executed correctly in the system.

Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.

Abstract: In a data processing system that comprises a memory 8 comprising N memory banks 11, a memory controller is configured to store one or more N data unit×N data unit arrays of data in the memory 8 such that each data unit in each row of each N×N data unit array is stored in a different memory bank of the N memory banks 11, and such that each data unit in each column of each N×N data unit array is stored in a different memory bank of the N memory banks 11.

Abstract: An apparatus for performing an electrical test at a device is described. In one general implementation, an apparatus may include a memory, a receiver, and a processor. The receiver is configured to receive a test signal, convert the test signal into a digital test signal (bit stream) and store the digital test signal in the memory. The receiver identifies when a pre-defined number of bits of the bit stream are available in the memory. The processor is configured to perform a logic operation on the bit stream and a reference signal, generate a test result based on the logic operation, and determine whether the test result satisfies a condition. In some implementations, the processor may be configured to synchronize the digital test signal with the reference signal prior to performing of the logic operation.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: Disclosed is a static random access memory including an assist circuit. More particularly, a static random access memory according to an embodiment of the present disclosure may include a bit cell part including at least one bit cell connected between a first ground voltage node and a second ground voltage node; and a controller including a first transistor configured to control connection between the first ground voltage node and the second ground voltage node, a second transistor configured to float a first ground voltage of the first ground voltage node, and a third transistor configured to float a second ground voltage of the second ground voltage node, wherein the controller controls the first and second ground voltages supplied to the bit cell part using the first, second, and third transistors.

Abstract: A semiconductor device includes a memory circuit and a data output circuit. The memory circuit outputs first internal data having a first burst length in a first mode and outputs the first internal data and second internal data in a second mode. A sum of the first and second internal data has a second burst length. The data output circuit outputs the first internal data as first output data through a first input/output line in the first mode. The data output circuit outputs the first internal data as the first output data through the first I/O line and outputs the second internal data as second output data through a second I/O line in the second mode. The data output circuit controls an internal current according to a logic level combination of the first and second internal data to generate the first and second output data in the second mode.

Abstract: A circuit includes a data line, a first cell in a first row of a memory array, and a second cell in a second row of the memory array. The first cell is electrically coupled with the data line and the second cell is electrically coupled with the data line. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a first read operation on the first row.

Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

Abstract: A method of detecting random telegraph noise defects in a memory includes initializing a first bit cell of the memory to a first value and reading the first value from the first bit cell. The method also includes writing a second value to the first bit cell and performing back to back read operations on a second bit cell adjacent to the first bit cell, after writing the second value. The method further includes attempting to read the second value from the first bit cell and determining whether the first bit cell is defective based on whether the second value was read from the first bit cell.

Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Abstract: A random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing circuit has an input terminal and an inverted input terminal. When a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read cycle, the sensing circuit judges a storage state of the selected cell according to a first charging current of the bit line and a second charging current of the inverted bit line, and determines a bit of a random code according to the storage state of the selected cell.

Abstract: An electronic device includes a pulse generator, a signal synthesizer, and a first storage circuit. The pulse generator generates a mode active pulse and a mode pre-charge pulse in response to an operation mode signal. The signal synthesizer synthesizes an active signal and the mode active pulse to generate a synthesized active signal. The signal synthesizer synthesizes a pre-charge signal and the mode pre-charge pulse to generate a synthesized pre-charge signal. The first storage circuit performs an active operation, a read operation, or a pre-charge operation in response to the synthesized active signal, a read signal, and the synthesized pre-charge signal in each of a first read mode and a second read mode.

Abstract: There is provided a communication apparatus. A communication control controls a communication unit so as to connect to one of a plurality of external apparatuses. A transfer unit transfers a data item to an external apparatus to which the communication unit has connected. In a case that a transfer of the data item is failed, a storage control unit stores transfer failure information in which the data item is associated with a transfer-destination external apparatus. In a case that the communication unit has connected to a first external apparatus, a transfer control unit controls a transfer of a data item. If a data item included in the transfer failure information is associated with the first external apparatus, the transfer control unit performs control so as to automatically transfer the data item to the first external apparatus.

Abstract: Several embodiments of memory devices and systems with walking read level calibration are disclosed herein. In one embodiment, a system includes a memory component having at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to perform iterative calibrations of the memory region by determining a first read level offset value during a first calibration. A new base read level test signal is determined based on the first read level offset value. During a second calibration using the new base read level test signal, a second read level offset value is determined.

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract: System and method for managing devices comprising a memory store having memory locations, wherein each memory location stores one or more attributes associated with one or more devices. Device manager arranged to execute commands to take an action on the one or more attributes stored in the memory locations, and to receive from the one or more devices values of the corresponding one or more attributes. Synchronizer configured to maintain synchronization between the attributes stored in the memory store and the attributes associated with the devices.

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a command and an address, and inputting/outputting data. The semiconductor system may include a second semiconductor device including first and second registers, wherein first corrected data, which is generated by correcting an error of internal data outputted in a first error correction operation, may be stored in the first register, and second corrected data, which is generated by correcting an error of the internal data outputted in a second error correction operation, may be stored in the second register, based on the command and the address.

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number.

Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a non-target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, one or more non-target access CS signals disabling target access to one or more non-target memory ranks of the first plurality of memory ranks coupled to the non-target local controller; and the memory controller being further configured to provide to a target local controller of the second plurality of local controllers, out of the first plurality of CS signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers a command and address (CA) sign

Abstract: A system and integrated circuits are provided for determining performance metrics over a plurality of cycles of an input signal using on-chip diagnostic circuitry. The system comprises a trigger generation module configured to generate a trigger signal, and diagnostic circuitry coupled with the trigger generation module. The diagnostic circuitry comprises a memory comprising a plurality of data lines, and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines. The diagnostic circuitry is configured to receive at least one input signal, and write, upon receiving the trigger signal, values on the plurality of data lines to the memory, thereby acquiring samples of a plurality of cycles of the input signal.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: Big data analysis using low power circuit design including storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline; precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit; activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells; and measuring a resulting voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result.

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Abstract: A floating gate setup method, system, and computer program product include, in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight, performing a feedback to the input line to set a voltage to change the floating gate FET VT and the current weight, and checking that the current weight is within a predetermined tolerance of the desired weight.

Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Abstract: A memory control device that is capable of making a nonvolatile memory of an information device exhibit the performance thereof certainly. A detection unit detects whether a data writable semiconductor memory is a nonvolatile memory or a volatile memory. A setting unit performs a setting to a volatile memory and performs a different setting to a nonvolatile memory that is detected with the detection unit.

Abstract: To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.

Abstract: The disclosure relates to technology performing a cyclic redundancy check (CRC). Data is divided into a plurality of blocks, each of the plurality of blocks having a fixed size equal to a degree of a generator polynomial. A CRC computation is independently performed on each of the plurality of blocks, and the CRC computation for each of the plurality of blocks is combined by application of an exclusive or (XOR) operation.

Abstract: Methods and system are provided for determining a maximum number of users of a system or network. A system capacity can be determined by performing a plurality of capacity tests. Each capacity test of the plurality of capacity tests can produce capacity test results that can be used to define a region of the system capacity from which the system capacity can be selected based on network conditions. The system capacity can be used to determine a user capacity of the system which can indicate the maximum number of users that can be active at any given time on the system. The system capacity can be used with a percentage weight of a plurality of user events performed on the system by active users to determine the maximum number of users.

Abstract: Various systems and methods for providing a memory monitor are provided herein. An integrated circuit and memory are disposed in a computer system. The integrated circuit to monitor main memory includes: a detection circuit to detect that the computer system enters a sleep state; a test circuit to test for the presence of the main memory; and a recovery circuit to perform a recovery process when the test fails.

Abstract: A method for screening bad columns applicable to a data storage medium is disclosed. The method for screening bad columns includes steps of: reading out written data of at least one of the data pages of at least one of the data blocks; comparing the written data with predetermined data to obtain a number of error bits in each of the columns in each of the segments in the at least one of the data pages, and accordingly calculating a total number of error bits in each of the segments; determining a segment having a largest total number of error bits from the segments, and determining and recording a column having a largest number of error bits from the segment having the largest total number of error bits as a bad column. A data storage device saving a bad column summary table is also disclosed.

Abstract: An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.

Abstract: A method of making measurements in a testing arrangement having a plurality of devices under test is described. The method comprises configuring a device interface board with the plurality of devices under test; running a set of test vectors in a plurality of loops on each device under test of the plurality of devices under test, wherein the set of test vectors is run in parallel on the plurality of devices under test and comprises edge shifted test vectors which are shifted by a predetermined edge shift step during each loop; receiving test result data for the plurality of devices under test; and determining, for each device under test, fail information to identify when the device under test failed based upon a number of edge shift steps. A system for making measurements in a testing arrangement having a plurality of devices under test is also described.

Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit, an accessing device and a refresh device. The refresh unit has a plurality of memory rows. The accessing device is configured to access the memory rows. The refresh device is configured to refresh the refresh unit in a first manner in response to a first event, in which a quantity of accessed memory rows of the refresh unit is not greater than a threshold quantity. The refresh device is configured to refresh the refresh unit in a second manner in response to a second event, in which the quantity of accessed memory rows of the refresh unit is greater than the threshold quantity.

Abstract: Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via corresponding access transistors. One of the first and second data lines can be driven to a ground voltage level to write a zero or one into a selected memory cell in the group. A first dummy data line can be formed adjacent to the first data line, whereas a second dummy data line can be formed adjacent to the second data line. During data loading operations, at least one of the dummy data lines can be pulsed to temporarily drive the voltage on the associated data line to below the ground voltage level. Operated in this way, the write operation of the memory cells can be improved.

Abstract: A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ECC (Error Correction Code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Abstract: Aspects include testing distributed file systems by selecting a file in a multiple writer environment and selecting an offset of a block in the file. Test data is generated for the block by randomly selecting a starting value from a plurality of possible starting values. A test header that includes the starting value and a test data sequence that starts with the starting value is created. A file system that is being tested writes the test header and the test data sequence to the block. Contents of the block are read by the file system that is being tested, and expected contents of the data sequence are determined based on contents of the read header. The expected contents of the data sequence are compared to the read data sequence and an error indication is output based on the expected contents not being equal to the read contents.

Abstract: A transmission relaying apparatus includes a signal receiving unit receiving a signal, transmitted from a transmission path, as a received signal; an abnormality detection unit detecting whether abnormality occurs in the received signal; and a threshold setting unit setting a preset threshold to be used for detection of abnormality by the abnormality detection unit. The threshold setting unit includes a peak value detection unit detecting a peak value of the signal level of the test signal received as the received signal by the signal receiving unit, when a test signal is output from a communication diagnostic apparatus; a threshold obtaining unit obtaining the preset threshold based on the peak value detected by the peak value detection unit; and a threshold holding unit storing the preset threshold, obtained by the threshold obtaining unit, as a preset threshold to be used by the abnormality detection unit.

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

Abstract: Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels associated with soldering, starting up the memory device and testing pre-programmed data using control circuitry of the memory device. When results of the testing indicate repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device indicative of a desire for the memory device to repair the pre-programmed data, and in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.