Abstract: A bipolar segment read circuit is applied for reading NOR flash memory such that cell current is converted to voltage by discharging bit line, which voltage is amplified by the bipolar segment read circuit, and then the voltage difference is converted to time difference by a block read circuit. In this manner, a reference signal is generated by reference cells storing low threshold data, which signal is delayed by a tunable delay circuit for generating a locking signal. Thus the locking signal effectively rejects latching high threshold data in latch circuits because high threshold data is arrived later. Furthermore, by adopting multi-divided bit line architecture, discharging time of bit line is reduced. And the memory cell can be formed from single crystal silicon or thin film polysilicon because the memory cell only drives lightly loaded bit line, even though thin film transistor can flow relatively low current, which realizes multi-stacked memory.

Abstract: A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.

Abstract: The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains several electronic components and an input. The electronic components receive a reduced voltage from the input to the cell. The reduced voltage reduces the current leakage of the electronic components within the cell. Some embodiments provide a memory circuit that has a level converter. The level converter receives a reduced voltage and converts the reduced voltage into values that can be used to store and retrieve data with stability in the cell. Some embodiments provide a method for storing data in a memory circuit that has a storage cell. The method applies a reduced voltage to the input of the cell. The method level converts the reduced voltage. The reduced voltage is converted to a value that can be used to store and retrieve data with stability in the cell. The reduced voltage reduces a current leakage of electronic components within the cell.

Abstract: A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.

Abstract: A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair of the memory cell array block; a first driver for driving a power supply line of the bit line sense amplifier block to a voltage of a node connected with the first power supply in response to a driving control signal; a plurality of second drivers for driving the node to an overdriving voltage higher than the normal driving voltage; and an overdriving drivability controller for selectively activating the second drivers in response to a test-mode drivability control signal inputted during an activation period of an overdriving signal.

Abstract: The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and a bit line-bar during non-accessing mode. During data accessing mode, one P-type device of an SRAM memory cell pulls up bit line or bit line-bar node slowly to minimize the inductive coupling noise and VDD, Ground bouncing, hence allows smaller amount of differential voltage input to the sense amplifier and results in lower power consumption. A self-timer counts the needed time and sends a signal to enable the current driven sense amplifier and to turn off the word line to avoid further pulling up the bit line or bit line-bar voltage and to reduce the power dissipation.

Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

Abstract: A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

Abstract: A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

Abstract: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.

Abstract: A memory sensing circuit and method that can achieve both a wide read margin and a fast read time. Roughly described, a target cell draws a target cell current from a first node when selected. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node when selected, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node.

Abstract: A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a dummy word line which selects the first dummy cell group, a dummy bit line to which data of the first dummy cell group is transferred, a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line, and a potential generating circuit which generates a first source potential applied to the first dummy cell group. The first source potential is different from a power supply potential.

Abstract: A sense amplifier for reading a memory cell is provided.

Abstract: An input/output (I/o) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in response to an output signal of the buffer unit. The precharge unit is driven by the first level voltage to precharge an output signal of the sense amplifier in response to the output signal of the buffer unit.

Abstract: In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract: A semiconductor memory device includes first and second global bit lines; first, second, third and fourth local bit lines; first, second, third and fourth hierarchical switches for respectively connecting the first global bit line and the first local bit line to each other, the second global bit line and the second local bit line to each other, the first global bit line and the third local bit line to each other, and the second global bit line and the fourth local bit line to each other; and first and second precharge circuits for respectively precharging the first and second global bit lines. When a memory cell connected to the first local bit line is read, the third hierarchical switch is turned off, and the first precharge circuit terminates its precharge operation after the third hierarchical switch is turned off and before a selected word line connected to the memory cell to be read is activated.

Abstract: A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the global input/output line pair. The detect control signal generating unit disables an operation of the sense amplifier and precharges the global input/output line pair to a predetermined voltage. A precharge operation of a memory device may be performed at a higher speed so that a high speed operation of the memory device may be achieved. In addition, the operating time of the sense amplifier may be decreased so that the power consumption of the memory device may be reduced.

Abstract: An input/output (I/O) line sense amplifier includes a first sense amplifier configured to amplify a signal of an I/O line in response to a strobe signal, and a second sense amplifier configured to latch and amplify an output signal of the first sense amplifier in response to the strobe signal.

Abstract: A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line.

Abstract: A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

Abstract: A semiconductor memory device prevents deterioration of refresh operation caused by sensing noise and a driving method thereof. First pull-down and second pull-down voltages which are different from each other are as a pull-down voltage of a bit line sense amplifier. The first and the second pull-down voltages are used in different driving periods to protect data from noises caused by another memory bank. A driving period can be separated into an initial sensing period, wherein large currents are consumed and significant noise is generated, and a subsequent stable period. The driving period can be separated into a pre-precharge period and a post-precharge period.

Abstract: Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amplifier from a memory array segment when it is unselected. When a memory array segment is being accessed, (such as during self-refresh), the multiplexers are latched into a selected state thereby eliminating the multiplexer switching current while the memory array segment is being accessed.

Abstract: A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first sense amplifier in response to a second control signal, and a disabling unit for disabling the first control signal in response to an output signal of the second sense amplifier.

Abstract: A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side of bit lines and switching a connecting state between the other row of sense amplifiers and the other side of bit lines; a control means which sets at least one row of sense amplifiers as a cache memory, and when performing refresh operation of the unit block where row of sense amplifiers to be used as cache memory holds data, controls switch means so that the row of sense amplifiers used as cache memory is disconnected from bit lines and only the row of sense amplifiers not used as said cache memory is used in refresh operation.

Abstract: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.

Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.

Abstract: A sense amplifier overdriving circuit includes a first voltage driver which supplies an internal voltage from an internal voltage terminal to a sense amplifier in response to a first enabling signal, a logic unit which logically operates a block select signal for selection of a cell block and a second enabling signal enabled for a predetermined time after enabling of the first enabling signal, and outputs the resultant signal, and a second voltage driver which supplies an external voltage to the internal voltage terminal in response to the signal output from the logic unit. The sensing amplifier overdriving circuit may be used in a semiconductor device.

Abstract: A semiconductor memory device including a bit-line sense amplifier is not affected by variation in manufacturing process and has a stable driving scheme. The semiconductor memory device includes: a unit memory cell for storing a data; a sense amplification unit including a bit-line sense amplifier (BLSA) for sensing and amplifying a voltage difference of a bit-line pair receiving the data of the unit memory cell; a variation detection unit for detecting a variation of a manufacturing process to output a detecting signal; and a sense amplifier controlling unit for controlling the BLSA to be activated after a predetermined time from an activation of unit memory cell in response to the detecting signal.

Abstract: A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refreshed to the fixed logic level. A sense amplifier includes a clamping circuit adapted to connect one of a digit line and an I/O line to a fixed logic level in response to an erase signal during a refresh of the selected block of memory cells.

Abstract: Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.

Abstract: A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines. A design structure embodied in a machine readable medium used in a design process, includes such a circuit for accessing a memory cell.

Abstract: A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed.

Abstract: The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying means coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying means in response to a control signal.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: One of a pair of data output units outputs data to one of the data line pair precharged to a reference voltage. A switch control unit couples the other of the data line pair to the data line, which corresponds to a data line to which data are not output, in a data output unit which does not output data during a period after data are output to one of the data line pair until a differential amplifier starts an amplifying operation. Thus, the load amount on the other of the data line pair increases. Therefore, change of the voltage on the other of the data line pair due to the influence of a coupling capacitance during data output can be prevented. That is, decrease of the read margin of data due to the coupling capacitance can be prevented.

Abstract: A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide a current to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.

Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

Abstract: In a reference current generator, a current mirror has a referent branch with a first current flowing thereon and a mirror branch to produce a second current by mirroring the first current, a first transistor is coupled to the referent branch, a second transistor is coupled to the mirror branch and has a gate coupled to the gate of the first transistor, one or more third transistors each produces a reference current by mirroring the first current or the second current to supply for a load, and a resistor having a resistance proportional to the absolute temperature is coupled to the first transistor such that a third current equal to the summation of the first current and all the mirrored reference currents flows through the resistor.

Abstract: Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.

Abstract: A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second switch, a second sub-array coupled to the cell input terminal through a third switch and coupled to the reference input terminal through a fourth switch, and a reference cell array coupled between the second switch and the fourth switch and coupled to the reference input terminal.

Abstract: A method of operating a memory device adapted for determining a program/erase state of a memory cell in the memory device. The method includes applying a drain operation voltage to a drain of the memory cell so that the memory cell generates a working voltage. The working voltage is a function of the drain operation voltage. Then, the working voltage to the drain operation voltage is differentiated to obtain a slope of the working voltage to the drain operation voltage. The program/erase state of the memory cell is determined according to the slope.

Abstract: A semiconductor memory device comprising multiple memory cells, main bit lines, a sub-bit line, a differential amplifier circuit, a precharge circuit, a first control circuit generating first and second control signals, and a second control circuit generating third and fourth control signals, wherein the differential amplifier circuit amplifies the voltage difference between the sub-bit line and the main bit line according to the first and second control signals; the precharge circuit charges the sub-bit line and the main bit line to a first voltage when the third and fourth control signals are activated and charges only the sub-bit line when the third and fourth control signals are inactivated, whereby the voltage of the main bit line is set so as to be lower than the voltage of the sub-bit line, and both the stabilization of reading operation and the increase in capacity are attained.

Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.

Abstract: Disclosed is a method for detecting a column fail by controlling a sense amplifier of a memory device. The method includes the steps of enabling a word line of a memory cell of the memory device, adjusting a timing of a high-level driving voltage and a low-level driving voltage applied to the sense amplifier, and detecting an amplification result of the sense amplifier.

Abstract: In a signal transmission system between a plurality of semiconductor apparatuses, a logic level decision circuit deciding a logic level of an input signal in accordance with which of two reference signals a signal level of the input signal is close to, by using two reference signals Vref1, Vref0 having a “1” level and a “0” level as reference signals for deciding the logic level of the input signal having a binary logic level, is used as an input receiver of the each semiconductor apparatus.

Abstract: Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a first bitline and a second bitline. The method includes precharging the first bitline and the second bitline to a low voltage. A wordline voltage is asserted to access the twin memory cell. A voltage difference between the first and second bitline is created by a data value and a complement of the data value stored in the twin memory cell, and the voltage difference is sensed.

Abstract: An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to “post-sense coupling” effects upon activation of the sense amplifiers in conjunction with capacitive coupling effects between bit lines, potential changes occur on adjacent bit lines. The integrated semiconductor memory makes it possible to simulate parasitic coupling effects between adjacent bit lines in a functional test in which the first and second sense amplifiers can be activated in temporarily delayed fashion. As a result, the test severity can be improved and test time can be saved.

Abstract: Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.