Abstract: In a particular embodiment, a method is disclosed that includes receiving a first sense output and a second sense output of a sense amplifier at a first tri-state device coupled to a first bus, receiving the first sense output and the second sense output of the sense amplifier at a second tri-state device coupled to a second bus, and selectively activating one of the first tri-state device and the second tri-state device to drive the first bus or the second bus in response to a bus selection input.

Abstract: A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.

Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

Abstract: A redundant circuit includes a plurality of bit line sense amp arrays including different local data buses, sharing one bit line sense amp, and being formed adjacently to each other, an input/output fuse unit for outputting a selection signal with different logic state depending on whether or not a first fuse is cut upon activation of a row active operation control signal, a fuse set for providing a redundant signal with different logic state based on whether or not a second fuse is cut and repair addresses upon activation of the row active operation control signal, and a redundant controller for logically operating the selection signal, the redundant signal and a strobe signal to thereby generate a bus control signal to selectively connect the bit line sense amp to the different local data buses.

Abstract: A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair of the memory cell array block; a first driver for driving a power supply line of the bit line sense amplifier block to a voltage of a node connected with the first power supply in response to a driving control signal; a plurality of second drivers for driving the node to an overdriving voltage higher than the normal driving voltage; and an overdriving drivability controller for selectively activating the second drivers in response to a test-mode drivability control signal inputted during an activation period of an overdriving signal.

Abstract: The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying means coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying means in response to a control signal.

Abstract: A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/output (I/O) switching unit for transferring the read data from a segment data line pair to the local data line pair and for transferring the write data from the local data line pair to the segment data line pair, wherein each of the local data line pair and the segment line pair includes a VDD precharge block.

Abstract: A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.

Abstract: A method of storing data includes transferring first data from a data line to a first sense amplifier, transferring the first data from the first sense amplifier to a first bit line, and transferring second data from the data line to a second sense amplifier. In the above operation, a period of the data storing operation of the second data from the data line to the second sense amplifier and a period of the data storing operation of the first data from the first sense amplifier to the first bit line are overlapped.

Abstract: A semiconductor memory device includes: a first bit line sense amplifier array for amplifying a data input to a first bit line pair coupled to cells; a second bit line sense amplifier array for amplifying a data input to a second bit line pair coupled to the cells; and a control unit for activating one of the first and second bit line sense amplifier arrays and, after a predetermined time, for activating the other bit line sense amplifier array in response to an active signal and a column address information signal.

Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Abstract: A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that addresses a selected one of the array of memory cells in a selected one of the plurality of columns in response to a memory address. A sense amplifier generates a data output by sensing a differential voltage from the corresponding bitline pair of the selected one of the plurality of columns in response to a sense amp enable signal. A sense amp enable signal generator generates the sense amp enable signal with adjustable timing, based on sense amp feedback signals.

Abstract: A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells; and at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell.

Abstract: A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry.

Abstract: A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type are configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

Abstract: This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors, a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or more pass transistors, and a cell plate connected to both a second terminal of at least one memory cell capacitor and a second terminal of at least one reference cell capacitor, wherein the cell plate is biased at approximately one half of a voltage difference between a positive supply voltage (Vdd) and a complementary lower supply voltage (Vss), and wherein the reference cell capacitor does not store any charge prior to a reading operation, and wherein both the first and second bit-lines are pre-charged to either Vdd or Vss prior to the reading operation.

Abstract: A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines.

Abstract: A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

Abstract: Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.

Abstract: An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell field region, and for connecting/disconnecting the sense amplifier to/from from a bit line of a second cell field region, as a function of the state of control signals applied at control lines. Driver devices drive the control signal. Additional switches change the state of the control signals.

Abstract: A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.

Abstract: An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the array 24 and modelling behaviour of the bit cells 32 in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array 24.

Abstract: A memory device, and method of operating the same, wherein the device includes resistive memory cells being switched between a low-resistive state and a high-resistive state; an evaluation unit, being coupled to a resistive memory cell to determine a resistive state of the resistive memory cell; and a voltage regulation circuit, being coupled to the resistive memory cell and to the evaluation unit. The voltage being applied to the resistive memory cell is regulated with respect to a target voltage.

Abstract: An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable.

Abstract: Structures of balanced sense amplifier circuits and methods for operating the same. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively. The structure also comprises a control circuit, which is electrically coupled to the first and second transistor bodies. The structure further comprises a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit. The testing circuit is capable of determining whether strengths of the first and second transistors are different. In response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first transistor body.

Abstract: An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a second bit line via a second output connection. A memory cell to store a first or a second memory state is connected to the first bit line. When writing/reading the first memory state, the sense amplifier produces a negative voltage at the first output connection and a positive voltage at the second output connection, and when writing/reading the second memory state, it produces the positive voltage at the first output connection and the negative voltage at the second output connection. The production of a negative voltage results in one of the two bit lines being charged approximately to a ground potential during a read or write access.

Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refreshed to the fixed logic level. A sense amplifier includes a clamping circuit adapted to connect one of a digit line and an I/O line to a fixed logic level in response to an erase signal during a refresh of the selected block of memory cells.

Abstract: A sensing amplifier comprising a program cell current sensing circuit, an erase cell current sensing circuit and a latch circuit is provided. Each of the program and erase cell current sensing circuits further comprises a plurality of program/erase memory cells, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth PMOS transistor. Wherein, one of the drain/source of the first NMOS transistor is electrically coupled to both the program/erase memory cells and a gate of the third NMOS transistor to form a node. In addition, one of the drain/source of the third NMOS transistor is coupled to the latch circuit. Moreover, the program/erase memory cell provides a program/erase current to the first NMOS transistor. The latch circuit will be driven once the amount of the electric charges accumulated at the node caused by the program/erase current overcomes a threshold voltage of the third NMOS transistor.

Abstract: A method of operating a memory device adapted for determining a program/erase state of a memory cell in the memory device. The method includes applying a drain operation voltage to a drain of the memory cell so that the memory cell generates a working voltage. The working voltage is a function of the drain operation voltage. Then, the working voltage to the drain operation voltage is differentiated to obtain a slope of the working voltage to the drain operation voltage. The program/erase state of the memory cell is determined according to the slope.

Abstract: Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.

Abstract: A high speed read-only memory (ROM). Data stored in a memory cell in the ROM array is provided to a sense amplifier in a differential form. Two transistors storing complementary logic states form a memory cell and store a data bit. One transistor has a source terminal connected to a ground terminal while the other transistor has a source terminal left unconnected. The drain terminals of each of the two transistors is connected to a corresponding one of a differential bit-line pair which provides a differential signal representing the stored data bit to a sense amplifier.

Abstract: An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterised in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.

Abstract: A semiconductor memory apparatus according to an embodiment of the present invention includes a plurality of cell mats each having a plurality of cells, a plurality of sense amplifier arrays, each having a plurality of sense amplifiers for sensing the cells in response to a power terminal driving signal and a ground terminal driving signal, and a sense amplifier activation control unit that adjusts a timing, at which the sense amplifier arrays are activated, in response to a refresh signal.

Abstract: A semiconductor memory device controls an over driving period according to fluctuation of a supply voltage VDD. The semiconductor memory device includes a bit line sense amplifier, a sense amplifying driver and an over driving controller. The over driving controller includes a delay unit for delaying an input signal, a supply voltage detector for detecting the level of the supply voltage VDD, a delaying controller for controlling a delay time of the delay unit in response to an output of the supply voltage detector, and an output unit for outputting a over driving pulse, whose width is controlled according to the fluctuation of the supply voltage VDD, by performing a logic operation to the input signal and an output of the delay unit.

Abstract: A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.

Abstract: A semiconductor memory device, for performing a writing operation faster without expanding a driver for the writing operation, includes a bit line sense amplifier (BLSA) for sensing and amplifying a value in a bit line pair, a supply line driver for driving a supply line of the BLSA, a driving controller for controlling the supply line driver in response to a sense amplifier enabling signal, and a sense amplifier enabling signal generator for generating the sense amplifier enabling signal, which is activated based on active and precharge command signals and inactivated during a predetermined part of an writing operation. A driving method of a semiconductor memory device includes enabling the BLSA in response to an active command signal, disabling the BLSA during a predetermined part of an writing operation, enabling the BLSA after the predetermine part, and disabling the BLSA in response to a precharge command signal.

Abstract: A semiconductor memory device includes a plurality of sense amplifiers each supplying a higher write potential and a lower write potential to each of memory cells; a driver circuit supplying the higher write potential to each of the sense amplifiers; a driver circuit supplying the lower write potential to each of the sense amplifiers; and an auxiliary driver circuit supplying either the lower write potential or an auxiliary potential lower than the lower write potential to each of the sense amplifiers. It is thereby possible to suppress a fluctuation in the lower write potential at start of a sensing operation. Therefore, the sensing operation can be accelerated as compared with a sensing operation performed by sense amplifiers in a conventional semiconductor memory device.

Abstract: Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

Abstract: A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number.

Abstract: A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines.

Abstract: The present invention provides an apparatus and method to reduce the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring Sense Amplifier Assist (SAA) circuitry. In particular, the present invention is an apparatus and method that limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.

Abstract: A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side of bit lines and switching a connecting state between the other row of sense amplifiers and the other side of bit lines; a control means which sets at least one row of sense amplifiers as a cache memory, and when performing refresh operation of the unit block where row of sense amplifiers to be used as cache memory holds data, controls switch means so that the row of sense amplifiers used as cache memory is disconnected from bit lines and only the row of sense amplifiers not used as said cache memory is used in refresh operation.

Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.

Abstract: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

Abstract: A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.

Abstract: A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination.

Abstract: A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

Abstract: When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period ?). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period ?).