Semiconductor Patents (Class 365/212)
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Patent number: 7272042Abstract: A semiconductor integrated circuit device includes a global-bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which selects one of the first and the second transistors, and a data latch circuit. The data latch circuit includes a data amplifier circuit which amplifies readout data from the first and the second section bit lines, a first data holding circuit which holds readout data and programming data to the first section bit line, and a second data holding circuit which holds readout data and programming data to the second section bit line.Type: GrantFiled: April 17, 2006Date of Patent: September 18, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Hiroto Nakai
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Patent number: 7272063Abstract: Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperature measured by the temperature sensor and configured to generate a code word indicative of the measured temperature and a type of the temperature sensor, the temperature sensor being selected from one of at least two different temperature sensor types.Type: GrantFiled: March 21, 2006Date of Patent: September 18, 2007Assignee: Infineon Technologies AGInventors: Jens Christoph Egerer, Georg Braun
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Publication number: 20070211512Abstract: A ferroelectric memory device includes a memory cell, read circuit, temperature sensing circuit, and read controller. The memory cell includes a ferroelectric capacitor. The read circuit is configured to read data from the memory cell. The temperature sensing circuit is configured to sense the ambient temperature of the memory cell. The read controller is configured to receive a temperature sensing signal from the temperature sensing circuit, and inhibit a data read operation by the read circuit when the temperature sensed by the temperature sensing circuit is higher than a preset temperature.Type: ApplicationFiled: August 29, 2006Publication date: September 13, 2007Inventor: Susumu Shuto
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Patent number: 7260007Abstract: Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.Type: GrantFiled: March 30, 2005Date of Patent: August 21, 2007Assignee: Intel CorporationInventors: Sandeep Jain, David Wyatt, Jun Shi, Animesh Mishra, John Halbert, Melik Isbara
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Publication number: 20070171751Abstract: A control device and method are used for adjusting the refresh rate of a memory module in a computer system. The device includes a thermo sensor and a control circuit. In the control method, the thermo sensor actively outputs a temperature change signal in response to the temperature change in the memory module when a capacitor of the memory module incurs an aggravated current leakage due to the temperature rise. Next, the control circuit adjusts the refresh rate in response to the temperature change signal and refreshes the memory module at the refresh rate.Type: ApplicationFiled: June 21, 2006Publication date: July 26, 2007Applicant: Via Technologies, Inc.Inventor: Kuan-Jui Ho
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Patent number: 7248524Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.Type: GrantFiled: June 29, 2005Date of Patent: July 24, 2007Assignee: Thin Film Electronics ASAInventors: Per-Erik Nordal, Geirr I. Leistad, Per Bröms, Hans Gude Gudesen
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Patent number: 7236415Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.Type: GrantFiled: September 1, 2004Date of Patent: June 26, 2007Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, David R. Cuthbert
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Patent number: 7234087Abstract: High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes sector data in one of the first memory and second memory, and next sector data in the other of the first and second memory. Sector data is read out from one of the first memory and second memory to the host computer, and simultaneously, next sector data is read out from the other of the first memory and second memory, and error detection and correction performed in the error correcting means. During a next cycle, the sector data read out from one of the first memory and second memory is outputted to the host computer, and simultaneously, error detection and error correction of the next sector data read out from one of the first computer and second computer is performed in the error correcting means.Type: GrantFiled: December 31, 2003Date of Patent: June 19, 2007Assignee: Renesas Technology Corp.Inventors: Takayuki Tamura, Shigemasa Shiota, Kunihiro Katayama, Masashi Naito
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Patent number: 7227774Abstract: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.Type: GrantFiled: November 23, 2005Date of Patent: June 5, 2007Assignee: Micron Technology, Inc.Inventors: Mark E. Tuttle, D. Mark Durcan
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Patent number: 7209401Abstract: An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.Type: GrantFiled: May 2, 2006Date of Patent: April 24, 2007Inventors: Robert D Norman, Dominik J. Schmidt
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Patent number: 7184349Abstract: A semiconductor memory device is provided for minutely changing a refresh interval according to a detected temperature and thereby lowering its power consumption. A temperature detector detects a temperature of a chip and outputs the corresponding temperature signal. A reference temperature signal output unit outputs the corresponding reference temperature signal with each of different reference temperatures to be compared with the chip temperature according to a selection signal. A temperature comparison unit compares the chip temperature with the reference temperature through the temperature signal and the reference temperature signal. A selection signal output unit outputs the selection signal according to the compared result of the temperature comparison unit. A refresh interval control unit changes the refresh interval according to the compared result of the temperature comparison unit.Type: GrantFiled: July 5, 2005Date of Patent: February 27, 2007Assignee: Fujitsu LimitedInventor: Atsumasa Sako
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Method and system for regulating a program voltage value during multilevel memory device programming
Patent number: 7184311Abstract: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.Type: GrantFiled: May 5, 2005Date of Patent: February 27, 2007Assignee: Atmel CorporationInventors: Massimiliano Frulio, Simone Bartoli, Davide Manfre′, Andrea Sacco -
Patent number: 7145823Abstract: In one embodiment, a method includes periodically charging a capacitor mounted on an electronic component; initializing a timer to count down from a counter value, once the capacitor is charged; determining if the capacitor has discharged before the timer has counted down to zero; and if the capacitor has discharged before the timer has counted down to zero then generating an interrupt.Type: GrantFiled: June 30, 2004Date of Patent: December 5, 2006Assignee: Intel CorporationInventors: Sandeep K. Jain, Animesh Mishra
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Patent number: 7145824Abstract: Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit and an array core with a temperature variable select device. The array core can consist of a thin film diode in series with a nanoscale resistive memory cell. The temperature sensitive bias circuit can include a thin film diode in series with two resistors, and provides a temperature compensating bias voltage to the array core. The thin film diode of the temperature sensitive bias circuit tracks the diode of the array core, while the two resistors create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core. The compensating bias reference voltage is generated by the temperature sensitive bias circuit, duplicated by a differential amplifier, and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell.Type: GrantFiled: March 22, 2005Date of Patent: December 5, 2006Assignee: Spansion LLCInventors: Colin S. Bill, Wei Daisy Cai
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Patent number: 7120074Abstract: A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.Type: GrantFiled: August 4, 2004Date of Patent: October 10, 2006Assignee: Infineon Technologies AGInventors: Manfred Proell, Herbert Benzinger, Manfred Dobler, Joerg Kliewer
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Patent number: 7092304Abstract: A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.Type: GrantFiled: September 2, 2004Date of Patent: August 15, 2006Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies AGInventors: Ryu Ogiwara, Daisaburo Takashima, Thomas Roehr
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Patent number: 7085185Abstract: A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.Type: GrantFiled: July 16, 2004Date of Patent: August 1, 2006Assignee: Infineon Technologies AGInventors: Stephan Schröder, Aurel von Campenhausen, Manfred Pröll, Koen Van der Zanden
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Patent number: 7079438Abstract: This invention provides a controlled temperature, thermal-assisted magnetic memory device. In a particular embodiment, there is an array of SVM cells, each characterized by an alterable orientation of magnetization and including a material wherein the coercivity is decreased upon an increase in temperature. In addition, at least one reference SVM (RSVM) cell substantially similar to and in close proximity to the SVM cells of the array is provided. A provided feedback control temperature controller receives a feedback voltage from the reference SVM cell, corresponding to temperature, and adjusts power applied to the RSVM cell and SVM cell. An associated method of use is further provided.Type: GrantFiled: February 17, 2004Date of Patent: July 18, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Frederick A. Perner, Manoj K. Bhattacharyya
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Patent number: 7075847Abstract: An apparatus for controlling a refresh cycle in a semiconductor memory device includes a temperature detection controller for generating a detection control signal and a converting control signal; a temperature detection block, which is enabled by the detection control signal, for generating an analog detection voltage in response to a temperature variation; an analog to digital converter, which is enabled by the converting control signal, for converting the analog detection voltage into a digital control code; and a refresh controller for generating a refresh cycle control signal based on the digital control code in order to control the refresh cycle.Type: GrantFiled: June 23, 2004Date of Patent: July 11, 2006Assignee: Hynix Semiconductor Inc.Inventors: Se-Jun Kim, Sang-Hoon Hong, Jae-Bum Ko
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Patent number: 7068557Abstract: An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.Type: GrantFiled: January 25, 2005Date of Patent: June 27, 2006Inventors: Robert D Norman, Dominik J. Schmidt
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Patent number: 7064994Abstract: In one embodiment, a memory controller is coupled to a memory subsystem and controls accesses to the memory subsystem. In addition, a temperature sensor is positioned to detect a temperature associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the sensed temperature. In a further embodiment, a sensor is positioned to detect a power condition associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the detected power condition.Type: GrantFiled: January 30, 2004Date of Patent: June 20, 2006Assignee: Sun Microsystems, Inc.Inventor: Chung-Hsiao R. Wu
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Patent number: 7046541Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array including a memory cell having a ferroelectric capacitor having first and second electrodes. A first bit line is electrically connected to the first electrode. A first potential generation circuit supplies a first potential to the second electrode to apply a voltage which drops at a first rate of change with a rise of temperature to the ferroelectric capacitor. A sense amplifier amplifies a potential difference between the first bit line and a second bit line complementary to the first bit line.Type: GrantFiled: April 23, 2004Date of Patent: May 16, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Ryu Ogiwara, Daisaburo Takashima
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Patent number: 7038967Abstract: A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.Type: GrantFiled: June 10, 2004Date of Patent: May 2, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshitaka Uchikoba, Tomonori Fujimoto, Kiyoto Ohta
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Patent number: 7028149Abstract: A method and apparatus for resetting and modifying special registers in a security token is described. In one embodiment, a register may be reset when a reset flag is true when a special transmission on a bus demonstrates the mutual locality of the associated processor and chipset. A modify flag may also be used to indicate whether the register contents may be modified. Modifications may also be dependent upon demonstration of mutual locality.Type: GrantFiled: March 29, 2002Date of Patent: April 11, 2006Assignee: Intel CorporationInventors: David W. Grawrock, James A. Sutton, II
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Patent number: 6999339Abstract: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.Type: GrantFiled: April 22, 2003Date of Patent: February 14, 2006Assignee: Micron Technology, Inc.Inventors: Mark E. Tuttle, D. Mark Durcan
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Patent number: 6999355Abstract: A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.Type: GrantFiled: May 10, 2004Date of Patent: February 14, 2006Assignee: Infineon Technologies AGInventors: Herbert Benzinger, Koen Van der Zanden, Stephan Schröder, Manfred Pröll
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Patent number: 6992940Abstract: The invention relates to a semiconductor memory apparatus in which the connections of the connecting contacts can be varied. The invention also relates to a semiconductor apparatus which comprises at least two semiconductor memory apparatuses according to the invention.Type: GrantFiled: August 22, 2003Date of Patent: January 31, 2006Assignee: Infineon Technologies AGInventor: Andreas Täuber
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Patent number: 6985384Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.Type: GrantFiled: October 1, 2002Date of Patent: January 10, 2006Assignee: International Business Machines CorporationInventors: Gregory Costrini, John Hummel, Kia-Seng Low, Igor Kasko, Frank Findeis, Wolfgang Raberg
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Patent number: 6970391Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.Type: GrantFiled: May 20, 2003Date of Patent: November 29, 2005Assignee: Renesas Technology CorporationInventors: Takao Watanabe, Ryoichi Hori, Goro Kitsukawa, Yoshiki Kawajiri, Takayuki Kawahara, Kiyoo Itoh
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Patent number: 6914834Abstract: A system and a method for functionally testing fast semiconductor memory chips. The data shifting method proposed here is based on the fact that a low speed tester writes data and data strobe test patterns to a memory block with a low clock frequency. The connection between the tester and the memory chip is subsequently disconnected for all the data and data strobe lines. This can be done by a relay or integrated circuits on an external circuit board or by test modes in the output circuit of the memory chip, that is to say on-chip. The data and data strobe lights are subsequently divided into two groups of the same size and connected to one another. The data and data strobe test pattern written to the first memory block is then shifted with a high clock frequency into a second memory block, from where it is then shifted back into the first memory block in a further read-write cycle with the high clock frequency.Type: GrantFiled: April 28, 2003Date of Patent: July 5, 2005Assignee: Infineon Technologies AGInventor: Peter Mayer
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Patent number: 6877897Abstract: The temperature of a semiconductor component is determined by way of a memory cell that includes a transistor and a capacitor. To that end, a signal is determined in dependence on a threshold voltage of the transistor and a value for the temperature of the transistor is determined in dependence on the signal.Type: GrantFiled: January 30, 2002Date of Patent: April 12, 2005Assignee: Infineon Technologies AGInventors: Jens Braun, Detlev Richter, Wolfgang Spirkl
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Patent number: 6871119Abstract: Machine-readable media, methods, and apparatus are described to throttle interfaces and/or logic based upon a temperature estimate. Some embodiments may provide thermal effects associated with throttled and non-throttled interfaces to a filter. The filter may update a temperature estimate based upon the provided thermal effects and one or more thermal time constants. Control logic may determine whether to throttle one or more interface based upon the temperature estimate of the filter.Type: GrantFiled: April 22, 2003Date of Patent: March 22, 2005Assignee: Intel CorporationInventors: Eric C. Samson, Aditya Navale, David M. Puffer
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Patent number: 6850448Abstract: A circuit for generating a refresh signal for a memory cell, includes a temperature-independent current source, a temperature-independent voltage source, and a temperature-dependent reference voltage source. A capacitor's first and second terminals are connected respectively to the temperature-independent current source, and the temperature-independent voltage source. The capacitor's first terminal is connected to a first input terminal of a comparator. The comparator's second input is connected to the temperature-dependent reference voltage source. The comparator is configured to output a refresh signal in response to a difference between voltages present at the first and second inputs thereof.Type: GrantFiled: March 11, 2003Date of Patent: February 1, 2005Assignee: Infineon Technologies AGInventors: Joachim Schnabel, Michael Sommer
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Patent number: 6809978Abstract: A method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a voltage of a network of the integrated circuit and regulating a voltage of an internal voltage generator of the integrated circuit based on the comparing.Type: GrantFiled: May 13, 2002Date of Patent: October 26, 2004Assignee: Infineon Technologies AGInventors: George William Alexander, Steven Michael Baker
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Patent number: 6778453Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.Type: GrantFiled: February 24, 2003Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventors: Christopher B. Cooper, Ming-Bo Liu, Chris G. Martin, Troy A. Manning, Stephen L. Casper, Charles H. Dennison, Brian M. Shirley, Brian L. Brown, Shubneesh Batra
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Patent number: 6775196Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory includes a magnetic memory cell, a conductor which crosses the magnetic memory cell and a circuit coupled to the conductor configured to apply a modified magnetic field to the magnetic memory cell in response to temperature variations in the magnetic memory cell.Type: GrantFiled: July 12, 2002Date of Patent: August 10, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Frederick A. Perner, Manoj Bhattacharyya
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Patent number: 6765836Abstract: In order to achieve an optimally stable synchronization of clock signals, a temperature-controlled delay device with which it is possible to generate a signal delay that is dependent on operating temperature is provided in a synchronization device for a semiconductor memory device. In this manner, the clock signal can be time-tuned in a particular reliable fashion.Type: GrantFiled: September 10, 2003Date of Patent: July 20, 2004Assignee: Infineon Technologies AGInventor: Ullrich Menczigar
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Publication number: 20040066691Abstract: Systems and methods for reading from or writing to memory blocks, are provided. An embodiment of the system comprises a plurality of memory blocks; a plurality of repeaters; and a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks. One embodiment of the method comprises coupling the memory blocks to repeaters; and reading from the memory blocks.Type: ApplicationFiled: September 30, 2003Publication date: April 8, 2004Inventor: Frederick A. Perner
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Publication number: 20040042307Abstract: In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas.Type: ApplicationFiled: June 27, 2003Publication date: March 4, 2004Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Masaki Hirayama, Yasuyuki Shirai
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Publication number: 20040042308Abstract: A disk drive determines whether or not a currently loaded disk is a gravity center deviated disk based on a tracking error signal detected at different disk rotation speeds.Type: ApplicationFiled: August 25, 2003Publication date: March 4, 2004Applicant: MITSUMI ELECTRIC CO., LTD.Inventor: Fumiya Igarashi
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Patent number: 6645822Abstract: To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells includes the step of structuring each of the memory elements simultaneously with the structuring of the first and second conductor elements.Type: GrantFiled: January 31, 2002Date of Patent: November 11, 2003Assignee: Infineon Technologies AGInventor: Till Schlösser
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Patent number: 6608791Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.Type: GrantFiled: March 25, 2002Date of Patent: August 19, 2003Assignee: Hitachi, Ltd.Inventors: Takao Watanabe, Ryoichi Hori, Goro Kitsukawa, Yoshiki Kawajiri, Takayuki Kawahara, Kiyoo Itoh
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Patent number: 6608790Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.Type: GrantFiled: December 3, 2001Date of Patent: August 19, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Lung T. Tran, Manoj K. Bhattacharyya
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Patent number: 6603678Abstract: A magnetic memory element is written to by heating the memory element and applying at least one magnetic field to the memory element. The memory element is heated via heating lines which can be formed in a single path or plurality of paths. Each path has one end tied to a reference potential, and the other end coupled to a current source via a transistor.Type: GrantFiled: January 11, 2001Date of Patent: August 5, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Janice H. Nickel, Lung T. Tran
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Patent number: 6577549Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.Type: GrantFiled: September 25, 2002Date of Patent: June 10, 2003Assignee: Hewlett-Packard Company, L.P.Inventors: Lung T. Tran, Manoj K. Bhattacharyya
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Patent number: 6557072Abstract: A mobile electronic device is disclosed. The mobile electronic device includes a housing, a processor supported by the housing, and a memory device coupled to the processor, the memory device including an adjustable self-refresh rate setting configured to determine the self-refresh rate of the memory device. The mobile electronic device also includes a temperature sensor supported by the housing, the temperature sensor is coupled to the processor and configured to measure a temperature. The mobile electronic device also includes computer program logic running on the processor, and the computer program logic is configured to predict a future temperature and change the adjustable self-refresh rate setting based on the predicted future temperature.Type: GrantFiled: May 10, 2001Date of Patent: April 29, 2003Assignee: Palm, Inc.Inventor: Neal A. Osborn
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Patent number: 6552945Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.Type: GrantFiled: January 23, 2001Date of Patent: April 22, 2003Assignee: Micron Technology, Inc.Inventors: Christopher B. Cooper, Ming-Bo Liu, Chris G. Martin, Troy A. Manning, Stephen L. Casper, Charles H. Dennison, Brian M. Shirley, Brian L. Brown, Shubneesh Batra
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Patent number: 6549486Abstract: A circuit for generating a constant pulse signal from an enabling ATD input signal may include a latch structure connected between first and second circuit nodes, with each node being coupled to a corresponding charge and discharge capacitance and being also connected to respective inputs of a logic gate. The circuit may also include a memory element coupled to the circuit nodes for filtering the enabling ATD signal and avoiding a partial discharge of one of the capacitances. An output of the logic gate is provided for generating the pulse signal independent of voltage and/or temperature variations affecting the enabling ATD signal.Type: GrantFiled: October 31, 2001Date of Patent: April 15, 2003Assignee: STMicroelectronics S.r.l.Inventors: Massimo Scardaci, Ignazio Martines
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Patent number: 6484232Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to control logic in a memory controller that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices. In addition, the memory controller also monitors the expected remaining life of the memory devices, and the number of errors occurring in the memory devices, and based on these parameters, may change the frequency of the calibration cycles.Type: GrantFiled: November 30, 2000Date of Patent: November 19, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Sompong P. Olarig, John E. Jenne
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Patent number: 6453218Abstract: A method and apparatus for the thermal sensing and regulating of a RAM device using temperature sensing circuitry, embedded directly in the device, is presented. A predetermined voltage is passed through a temperature sensitive diode to create an analog signal. The analog signal is converted into digital temperature data by a A/D converter. The digital temperature data is then transmitted to a controlling host, without interfering with the normal operation of the device, by either transmitting the data in an out-of-band signal or during the clock refresh cycle. The controlling host, upon receipt of the temperature data, checks to see if the temperature level of the device has exceeded a threshold value.Type: GrantFiled: March 29, 1999Date of Patent: September 17, 2002Assignee: Intel CorporationInventor: George Vergis