Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.

Abstract: The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.

Abstract: The invention provides for a content addressable memory (CAM). The CAM includes an input port and a plurality of locations to store page addresses for comparing to an address received from the input port. Each location includes a plurality of lower cells and at least one page size mask cell to send signals to an associated one of the lower cells. The associated one of the lower cells produces a match signal in response to either the page size cell sending a mask signal or to the portion page address stored therein matching a corresponding portion of the address received from the input port. Each location produces a match signal in response to each cell therein producing a match signal. The invention provides for a method of translating logical to physical addresses.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: An integrated circuit formed on a semiconductor substrate having multiple input/output signal paths such that the semiconductor substrate can be mounted to more than one package type. The integrated circuit formed on the semiconductor substrate has at least three pluralities of input output connector pads. The first plurality of input/output connector pads is placed on the semiconductor substrate and is attached to a first functional circuit of the integrated circuit. The second and third pluralities of input/output connector pads are placed on the semiconductor substrate and are attached to a second functional circuit of the integrated circuit. The third plurality of input/output connector pads is placed in an area separated from the first and second pluralities of input/output connector pads.

Abstract: Each global data bus is selectively connected via a connection circuit to any of local data buses associated with subarrays arranged on either side of the global data bus. Between row blocks is arranged a connection controlling circuit outputting a control signal which controls connection of the connection circuit. In each connection controlling circuit, a fuse corresponding to a location of a subarray including a defective memory cell is cut to provide column substitution without changing an order of global data buses.

Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory device coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature of the memory device. Based on the operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

Abstract: A semiconductor device having an EEPROM array includes resistive elements capable of elevating the temperature of the EEPROM array during programming and erasing operations. The resistive elements are located in close proximity to individual EEPROM cells within an EEPROM array. By elevating the temperature of the EEPROM cell during programming and erasing operations, data errors associated with shifting threshold voltages of floating-gate devices within the EEPROM is reduced. An operating method for improving the long term reliability of an EEPROM device includes the step of providing thermal energy during programming and erasing sufficient to raise the temperature of the EEPROM device to at least about 70.degree. C.

Abstract: An integrated circuit is described which includes a temperature detection circuit. The detection circuit produces an output which indicates a temperature range of the integrate circuit. The output of the detection circuit is used to adjust the operation of the integrated circuit. The integrated circuit is described as a flash memory device which can include a controller to monitor the output of the detection circuit, or provide the output to an external controller. The controller uses the detection circuit output to adjust memory operation, such as operating frequency.

Abstract: A semiconductor integrated circuit having a DRAM, or the like, includes a memory cell block containing a plurality of memory cells, and a core circuit portion for selecting and activating a specified memory cell inside the memory cell block, and is constituted so that a step-up voltage is applied to the core circuit portion at the time of an activated state. The semiconductor integrated circuit further includes a step-up voltage lowering unit for lowering the step-up voltage by a predetermined value and a unit for selectively supplying the step-up voltage and an output voltage of the step-up voltage lowering unit to the core circuit portion.

Abstract: A system of semiconductor devices is formed by staggering like devices on opposite sides of a board, such that common leads on the opposed devices are aligned. The common leads are connected directly through the board. The staggered arrangement provides additional room for conductive lines on the board. In addition, it improves performance by reducing signal delays. The invention is applicable to a dual in-line memory module and other products formed of semiconductor devices.

Abstract: An integrated circuit is described which has circuitry to detect environmental conditions such as temperature and supply voltage and adjust the operation of the circuit accordingly. A flash memory system is described which includes a temperature detector and a supply voltage detector. The memory monitors temperature and voltage and adjusts an oscillator circuit to maintain an ideal operating frequency. The oscillator includes adjustable delay stages which can be selectively fed back to adjust operating frequency. To save power, unused delay stages of the oscillator can be disabled. Oscillator calibration circuitry, a temperature detector, and a voltage detector are described.

Abstract: An integrated circuit is described which includes a temperature detection circuit. The detection circuit produces an output which indicates a temperature range of the integrate circuit. The output of the detection circuit is used to adjust the operation of the integrated circuit. The integrated circuit is described as a flash memory device which can include a controller to monitor the output of the detection circuit, or provide the output to an external controller. The controller uses the detection circuit output to adjust memory operation, such as operating frequency.

Abstract: An electrically erasable programmable read only memory (EEPROM) capable of reducing the margin of threshold voltage is disclosed which contributes to the achievement of low-voltage driving and/or multiple-value data storage architectures. The EEPROM includes an array of memory cells that are changeable in threshold voltage for data storage of different logic levels, wherein data may be read out of any specified one of the memory cells. A read voltage applied to the memory cell is designed to have a temperature dependence substantially identical to that of the memory-cell threshold voltage. A write-verify voltage may also be designed to have the same temperature dependence as that of the memory cell. Thus, the inter-threshold margin and the read margins of the memory cell can be reduced.

Abstract: An address transition detector receives one or more address signals. The address transition detector provides a transition detection signal in response to a transition of at least one of the address signals. A pulse generator is coupled to receive the transition detection signal and an environmental input. The pulse generator provides a control signal having a delay based upon an environmental input. The environmental control input may be based upon variables such as temperature, supply voltage, or process skew.

Abstract: A non-volatile memory module includes a charging circuit, a battery couple to the charging circuit, a volatile memory and an electronic switch coupled between the volatile memory and the battery.

Abstract: A memory device includes a plurality of PMOS transistors and a voltage regulator circuit. Each transistor has a gate, a source region, a drain region, and a well containing the source and drain regions. Each transistor is characterized by a threshold voltage which is dependent on temperature and on a body-source bias voltage. Each transistor is also characterized by a sub-threshold current which is dependent on the transistor's threshold voltage. The voltage regulator circuit is operatively coupled to each well to provide the body-source bias voltage to each well. The voltage regulator circuit temperature-compensates the body-source bias voltage to maintain the threshold voltage of each transistor approximately constant despite changes in temperature. The memory device thus advantageously has a relatively constant stand-by current despite temperature variations.

Abstract: In a matrix array of memory cells, each memory cell includes a control gate, and first and second terminals for defining a channel therebetween, with the second terminals of the memory cells being connected to a common circuit node. During a write modes a row of memory cells and a column of memory cells are selected, and a first voltage is supplied to the control gates of the memory cells of the selected row and a second voltage which varies positively as a function of temperature is supplied to the first terminals of the memory cells of the selected column for trapping electrons in at least one of the memory cells. During an erase mode, ground potential is supplied to the control gates of all memory cells and a third voltage which varies negatively as a function of temperature is supplied to the common circuit node to remove the trapped electrons from the memory cells.

Abstract: A digital value on a plurality of control input terminals of a PCMCIA power multiplexer integrated circuit determines which one if any of a plurality of power input terminals (for example, 12 volts, 5 volts, and 3 volts) is coupled through the integrated circuit to a power output terminal. A decoder which decodes the digital value prevents any two of the power input terminals from being coupled to the power output terminal at the same time. The decoder is programmable so that a single power multiplexer integrated circuit die layout can support a variety of PCMCIA controllers outputting different digital values. The integrated circuit has current limit, controlled power turn on times, and overtemperature protection. A signal indicative of a fault condition (for example, an overtemperature or a current limit condition) is output onto a fault output terminal of the integrated circuit.

Abstract: A memory device includes a plurality of PMOS transistors and a voltage regulator circuit. Each transistor has a gate, a source region, a drain region, and a well containing the source and drain regions. Each transistor is characterized by a threshold voltage which is dependent on temperature and on a body-source bias voltage. Each transistor is also characterized by a sub-threshold current which is dependent on the transistor's threshold voltage. The voltage regulator circuit is operatively coupled to each well to provide the body-source bias voltage to each well. The voltage regulator circuit temperature-compensates the body-source bias voltage to maintain the threshold voltage of each transistor approximately constant despite changes in temperature. The memory device thus advantageously has a relatively constant stand-by current despite temperature variations.

Abstract: A semiconductor memory device has a dynamic memory element constructed of a capacitor and a transistor; and a refresh timer circuit for automatically recharging the dynamic memory element at periodic time intervals corresponding to an electric charge holding time of the dynamic memory element which changes in accordance with an ambient temperature. Since the refresh timer circuit includes a current bias circuit for varying an electric current in accordance with the ambient temperature and an oscillation circuit for oscillating at a frequency corresponding to the electric current of the current bias circuit, the refresh cycle time changes in response to ambient temperature changes, thus reducing the requisite current capacity of the memory device power supply.

Abstract: A system and method for isolating one or more causes of wafer misprocessing. A list of interesting queries (10) is generated. During wafer processing (15), processing parameters are measured (20) and a wafer tracking database (25) is created. The list of queries (10) may be filtered (30) before the queries are tested for interestingness. Interestingness is determined by outlier calculation (35) and trend analysis (40) on data stored in the wafer tracking database (25). Queries found to be interesting are displayed (50).

Abstract: A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.

Abstract: The specification describes an integrated circuit device that selects its own supply voltage by controlling a programmable power supply. The programmable power supply provides a supply voltage in response to one or more voltage control signals generated by the integrated circuit device. The integrated circuit device includes a voltage control circuit for generating the voltage control signals according to one or more predetermined operational voltages programmed into the integrated circuit device such that the supply voltage is substantially equal to a selected one of the predetermined operational voltages. The integrated circuit device may include a temperature sensor to allow selection of the predetermined operational voltage according to device temperature to avoid speed-limiting voltage and temperature combinations.

Abstract: Semiconductor circuit provides an EEPROM programming charge pump (18), and includes a leakage current measuring device (12), a plurality of interconnected current mirrors, and a current controlled oscillator (16) for providing programming power to such EEPROM. The leakage current sensor (12) generates current nonlinearly related to device ambient temperature of the semiconductor circuit, the current mirrors combining and scaling the leakage current (14) with a constant current to provide a composite current altering frequency of the oscillator (16).

Abstract: Delay circuit 11 is composed of eight-stage NOT circuits. Polysilicon resistors RPS11 and RPS12 are connected to the sources of P channel type MOS transistor Qp12 and N channel type MOS transistor Qn12 in the second stage NOT circuit. These polysilicon resistors exhibit a smaller temperature dependency, as shown by dot lines in FIG. 2. The delay time of the eight-stage NOT circuits as a whole shows a smaller temperature dependency. Delay circuit 12 in FIG. 1 is composed of three-stage NOT circuit, followed by three-stage NOT circuit or one-stage NOT circuit. With such arrangement, a temperature detection circuit with no or less manufacturing deviations is completed.

Abstract: A semiconductor device is provided with an automatic voltage switching circuit which applies an internal, reduced power voltage to an internal other than when a burn-in test is performed. The semiconductor device comprises a temperature detection circuit for detecting a predetermined temperature used for the burn-in test and a switch circuit for applying the external power voltage to the internal circuit when the predetermined temperature is detected.

Abstract: An electrically programmable read only memory (EPROM) source bias circuit provides a bias voltage at the source of an EPROM transistor which may vary with EPROM processing characteristics. The source bias circuit includes a reference voltage generator which generates a reference voltage which varies with EPROM transistor cell conductivity, and a source bias element which sets the voltage on the source node of the EPROM transistor during programming. The circuit functions to provide a greater amount of source bias to a higher-conductivity EPROM cell during programming, and to apply a lower source bias voltage to low conductivity EPROM cells. Programming efficiency of the EPROM transistor is improved, and yield of EPROM devices employing the circuit is enhanced.

Abstract: A memory unit includes an array of memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A decoder receives an address signal at a timing which follows an occurrence of a clock signal by a given time t1. The address signal is in synchronism with the clock signal. The clock signal has a preset period t0. The decoder decodes the address signal into a word signal and outputs the word signal at a timing which follows the reception of the address signal by a given time t2. A delay device delays the clock signal by a preset time "t" and thereby converts the clock signal into a control signal. An access to a word of the memory cells is performed via one of the word lines in accordance with the word signal at a timing determined by the control signal. The bit lines are precharged at a timing determined by the control signal. The preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0.

Abstract: An MOS temperature sensing circuit formed on a silicon substrate which may be used for disabling portions of output drivers in EPROM at high temperatures. The circuit uses a first and second diode, one of which has substantially larger area than the other. The diodes are reverse biased through field-effect transistors. The leakage from the smaller diode is used to cancel the effects process variations on the leakage current of the larger diode, thereby providing a circuit with an output substantially dependent only on temperature.

Abstract: An adjustable sense amplifier circuit for read/write control of solid state memory devices is described. In a write mode the circuit includes a write select path, coupled to a current source and coupled to a differential pair of data select transistors, wherein the input data state sets each of two differential pairs formed by the memory element cross-coupled latch, such that the memory element stores selected data. In a sense mode, a second current path is selected wherein an adjustable sense level is provided to each of two differential pairs formed by the memory element. The current source is coupled to a reference voltage source which is independent of the supply voltage. The reference voltage source tracks changes in temperature and also provides low beta compensation for current loss due to the low beta value of transistors in the write and sense paths.

Abstract: A semiconductor memory device with an internal refresh circuit is disclosed. The internal refresh circuit includes a timer circuit which generates a refresh request signal in a shorter cycle at a high temperature and in a longer cycle at a low temperature. The cycle of a self-refresh mode can be thereby lengthened in a low temperature to reduce a power consumption in the self-refresh mode.

Abstract: Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized.

Abstract: An oscillator of a pulse generator for use in a system for refreshing a dynamic memory comprises an operational amplifier having first and second input terminals and an output terminal, a thermistor connected between the first input terminal and the output terminal, a capacitor connected between the first input terminal and a ground, and four resistors. A first resistor is connected between the second input terminal and the output terminal. A second resistor is connected between the second input terminal and the ground. A third resistor is connected between the second input terminal and a power supply. A fourth resistor is connected between the output terminal and power supply.

Abstract: A two phase charge coupled device memory array wherein the storage capacity is increased by using multiple levels of charge storage within a given cell. A voltage waveform generator capable of producing one of four different voltages is utilized to input and output charge in the multiple level charge method. In determining the level of charge stored within a given cell in the array, the voltage difference between a reference cell and an adjacent addressing cell is used. By determining the voltage level of the addressing cell at which charge overflows the reference cell and counting the number of times it overflows as the voltage generator is successively stepped through its four voltage levels, the level of the original charge input to a given cell can be determined. To make the multiple level scheme independent of process parameters and temperature, the same two cells are utilized for both input and output functions. Various other cells are provided to block and route charge with respect to the array.