Abstract: A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.

Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Abstract: A memory apparatus includes a memory cell array including a plurality of memory cells, a temperature sensor, a temperature compensated self refresh (TCSR) block, and a command controller. The temperature sensor is configured to generate temperature information by measuring internal temperature of the memory apparatus. The TCSR block is configured to vary and output, in a test mode of the memory apparatus, period information for adjusting a refresh period for the memory cell array according to the temperature information. The command controller is configured to adjust, in response to the period information, the refresh period for the memory cell array by controlling an external command.

Abstract: A device includes a plurality of memory cells, an error detection circuit configured to detect at least one memory cell storing error data and a refresh control circuit including a register configured to store an error address corresponding to the at least one memory cell storing error data. The refresh control circuit is configured to control a refresh cycle of the error address.

Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.

Abstract: A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.

Abstract: Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.

Abstract: A semiconductor device in which a plurality of chips each including a memory circuit is stacked, the semiconductor device includes a transmission path including a plurality of microbumps formed in the plurality of chips, measurement circuitry that detects a reflected waveform when a signal is transmitted in the transmission path and measures propagation delay time for a certain part on the transmission path from the reflected waveform that has been detected, determination circuitry that calculates temperature of each memory area that corresponds to the certain part from the propagation delay time that has been measured by the measurement circuitry, and control circuitry that sets a refresh interval of each memory area, based on the temperature of each memory area, which has been calculated by the determination circuitry, and executes a refresh operation of the memory circuit in each memory area at the refresh interval that has been set.

Abstract: A memory circuit, comprises a first set of memory cells configured to operate in a direct access mode or in a refresh mode and a second set of memory cells configured to operate in the direct access mode and in the refresh mode. The memory circuit further comprises a controller configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.

Abstract: A semiconductor device according to an aspect of die present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to, the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: A memory system includes a memory in which stored data is periodically rewritten by a refresh command, and a memory controller. The memory has an input/output (“I/O”) terminal, and the memory controller is communicatively coupled by a channel to the I/O terminal. The memory transmits a plurality of commands over the channel to the memory. The memory controller estimates a first total energy consumed based on the plurality of commands during a first sampling period, determines a temperature of the memory based on the first total energy consumed in the first sampling period, determines a first refresh cycle rate corresponding to the first temperature of the memory and transmits a refresh command to the memory based on the first refresh cycle rate.

Abstract: A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts.

Abstract: A semiconductor device according to an embodiment includes a plurality of memory regions suitable for performing a refresh operation based on a row address signal; an initialization circuit suitable for generating an initialization pulse signal for each refresh period during which a refresh pulse signal toggles as many times as the number of the memory regions; a control circuit suitable for activating a control pulse signal based on the refresh pulse signal and a plurality of memory address signals corresponding to the memory regions, and deactivating the control pulse signal based on the initialization pulse signal; and a row address generation circuit suitable for sequentially generating the row address signal based on the control pulse signal.

Abstract: A method, system and memory controller are provided for implementing refresh power optimization during long idle mode in a memory subsystem utilizing Dynamic Random Access Memory (DRAM). The DRAM includes DRAM cells requiring periodic refresh. A DRAM activity monitoring mechanism monitors an instruction queue and asserts a predefined mode register bit when the instruction queue is empty. Responsive to the asserted predefined mode register bit, a refresh rate is increased and a low power mode is established by reducing DRAM core power level for optimizing refresh power during the long idle mode to provide enhanced system performance.

Abstract: A memory device may be provided. The memory device may include a test data output circuit configured to compare lower data output from a lower data storage region with upper data output from an upper data storage region and make a decision. The memory device may include a data transmitter configured to output the lower data by inverting or noninverting the lower data according to the decision. The memory device may include a test control circuit generates a test control signal according to a test read signal and an address signal.

Abstract: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.

Abstract: A memory device includes: a memory region including a plurality of word lines; and a refresh control block configured to: sequentially refresh the plurality of word lines in a manner such that two or more word lines are simultaneously refreshed during a first refresh operation, simultaneously refresh two or more first critical word lines corresponding to a first critical address generated by up-counting a target address during a second refresh operation, and simultaneously refresh two or more second critical word lines corresponding to a second critical address generated by down-counting the target address.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

Abstract: A resistance change memory including a memory cell having a resistance change element; a reference voltage generating circuit which generates a reference adjustment voltage; a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor. The reference voltage generating circuit includes a second transistor having a gate coupled to a gate of the first transistor, the reference adjustment voltage changing in accordance with a temperature, and the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in a current value in accordance with the reference adjustment voltage.

Abstract: Method and apparatus for allowing visually impaired users to easily interact with GUI applications is provided. The method and apparatus may utilize a directed graph of the GUI and a language model to describe the GUI in a brief but concise and descriptive manner.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

Abstract: In one embodiment, a semiconductor device (20) includes a semiconductor chip (200) in which functional blocks (201, 202, 203 etc.) and a temperature sensor (208) are integrated. In this embodiment, in response to a change in an operation state of the semiconductor device (20), the on-chip temperature sensor (208) operates to switch from a continuous operation in which it continuously measures a chip temperature to an intermittent operation in which it intermittently measures the chip temperature, or to change a time interval between intermittent measurements of the chip temperature.

Abstract: A semiconductor device in which a plurality of chips each including a memory circuit are stacked, the semiconductor device includes measurement circuitry each of which is disposed in each of a plurality of memory areas of the plurality of chips and each of which measures a temperature, calculation circuitry that calculates a temperature of each of the memory areas based on the temperature measured by the measurement circuitry and a temperature obtained from a thermal resistance model of the semiconductor device, and control circuitry that sets a refresh interval of each of the memory areas based on the temperature of each of the memory areas, which has been calculated by the calculation circuitry, and performs a refresh operation of the memory circuit of each of the memory areas at the set refresh interval.

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.

Abstract: A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.

Abstract: According to one embodiment, a memory system is provided with a memory cell array, a first command issuing circuit and a controller. The memory cell array includes a plurality of data areas and a plurality of first parity areas. The data areas are arranged in a plurality of banks or in a plurality of chips, and individually store a plurality of data portions constituting access-unit data. The first parity areas are adjacent to the data areas and individually store a plurality of first parity portions constituting the first parity corresponding to the data. The first command issuing circuit issues a first command for the data areas and the first parity areas. The controller accesses the data areas and the first parity areas in response to the first command.

Abstract: A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.

Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

Abstract: Techniques and mechanisms for configuring an integrated circuit to couple to, and exchange data with, a hardware interface. In an embodiment, the integrated circuit comprises a data channel including a plurality of bits, configuration logic, and a plurality of contacts including a first contact group and a second contact group. In response to a signal indicating connectivity of the integrated circuit to the interface, a mode of the configuration logic is selected to couple the plurality of bits to one of the first contact group and the second contact group.

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Abstract: A refresh control device for reducing power consumption during a target row refresh operation is disclosed. The refresh control device includes a refresh address generator configured to generate a refresh address by selecting any one of a target row refresh address and a normal refresh address according to a target row refresh flag signal, an address control signal generator configured to generate a multiple address control signal in response to the target row refresh flag signal and a multiple refresh signal, and a final refresh address generator configured to generate a plurality of final refresh addresses from the refresh address in response to the multiple address control signal.

Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.

Abstract: A semiconductor device includes a first control block suitable for selectively blocking a refresh command signal based on a period signal having a predetermined activating pattern and a predetermined mode signal activated in a predetermined mode to generate a refresh group signal; and a second control block suitable for controlling a refresh operation based on the refresh group signal.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command.

Abstract: There is disclosed herein multiplexer circuitry. In particular, there is disclosed a latch circuit for use as a multiplexer to multiplex information carried by respective pairs of input information signals onto an output information signal, each pair of input information signals comprising a first input information signal and a second input information signal, and each pair of input information signals carrying information values based on signal values of those input information signals and interleaved with information values carried by the other pair or pairs of input information signals.

Abstract: A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories, a non-volatile memory, and a controller suitable for backing up data of the ranks into the non-volatile memory by using the emergency power supplier during a power failure, wherein the ranks are sequentially backed up, and while one rank is backed up among the ranks, the other ranks are controlled in a self-refresh mode.

Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit and an accessing device. The refresh unit includes a target row on which a read/write (R/W) operation is requested to be performed. The accessing device is configured to perform the R/W operation on the target row while the refresh unit is being refreshed.

Abstract: A semiconductor device includes a substrate, a circuit having a transistor formed on the substrate, an oscillation circuit generating a frequency signal, a substrate voltage generation circuit generating a substrate voltage in accordance with the frequency signal from the oscillation circuit, and a control circuit varying a frequency of the frequency signal from the oscillation circuit during a stand-by period of the circuit.

Abstract: A semiconductor memory device includes: a plurality of memory cell arrays each memory cell array including a first region, a second region, and a third region in the second region; and a repair controller suitable for storing a first repair address information, generating a first mode enable signal for accessing the third region by comparing the first repair address information with a row address during a first mode for a repair operation, and disabling the first mode enable signal in response to a refresh command regardless of a result of the comparing the first repair address information with the row address.

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.

Abstract: Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.