Abstract: The present disclosure relates to systems and methods for information security, specifically for automatically detecting theft of personal data. In one implementation, a computer-implemented method for automatically detecting theft of personal data on the Internet may include at least one processor configured to execute instructions, the instructions including receiving from a user, an electronic communication containing a first search term, extracting via pattern recognition one or more patterns corresponding with the first search term, and comparing the one or more patterns with a subset of data scraped from the Internet, with the subset of data scraped from the Internet being indexed by pattern for the first search term. The instructions may also include flagging matches of the one or more patterns with the subset of data based on the comparison and transmitting information associated with the matches in a report that indicates a possible theft of personal data.

Abstract: Examples disclosed herein relate, in one aspect, to an electronic device including a processor, a lookup engine, and a content addressable memory (CAM) including a plurality of data tables. The lookup engine may obtain from the processor a search word and a table identifier identifying a selected data table from the plurality of data tables, and using a lookup table, determine table parameters associated with the selected data table. The lookup engine may also generate search parameters based on the search word and the table parameters and provide the search parameters to the CAM. The search parameters may cause the CAM to determine whether the selected data table comprises a word corresponding to the search word, and if the selected data table comprises the word, to output an entry address of an entry of the CAM that comprises the word.

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

Abstract: A method for efficient name coding in a storage system is provided. The method includes identifying common prefixes, common suffixes, and midsections of a plurality of strings in the storage system, and writing the common prefixes, midsections and common suffixes to a string table in the storage system. The method includes encoding each string of the plurality of strings as to position in the string table of prefix, midsection and suffix of the string, and writing the encoding of each string to memory in the storage system for the plurality of strings, in the storage system.

Abstract: A method for write aggregation using a host memory buffer includes fetching write commands and data specified by the write commands from a host over a bus to a non-volatile memory system coupled to the host. Writing the data specified by the write commands from the non-volatile memory system over the bus to the host. The method further includes aggregating the data specified by the write commands in a host memory buffer maintained in memory of the host. The method further includes determining whether the data in the host memory buffer has aggregated to a threshold amount. The method further includes, in response to determining that the data has aggregated to the threshold amount, reading the data from the host memory buffer to the non-volatile memory system and writing the data to non-volatile memory in the non-volatile memory system.

Abstract: To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

Abstract: Systems and methods are provided for updating expansion read-only memory (ROM) code to execute for device-specific initialization. An exemplary method comprises first accessing one or more copies of a ROM code in at least one of a plurality of repositories. The ROM code can be configured to execute an initialization process for a specific device in the computer system. The method can then select one of the one or more copies of the ROM code based on a selection criterion to yield a selected ROM code. The method can then copy the selected ROM code to a system memory of the computer system. The method can then execute the selected ROM code in the system memory to initialize the specific device.

Abstract: An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.

Abstract: A method comprising receiving, by a network element, a data packet, searching, by the network element, the received data packet at a first hierarchical level to determine whether a substring of a string of a regular expression exists in the received data packet, searching, by the network element when the search of the received data packet at the first hierarchical level finds a match, the received data packet at a second hierarchical level to determine whether the string of the regular expression exists in the received data packet, and transmitting, by the network element, the received data packet to a next network element along an original path of the received data packet without searching the received data packet at a third hierarchical level when the search of the received data packet at the first or second hierarchical level does not find a match.

Abstract: A method for determining a type of a device connected to an inter-integrated circuit (I2C) includes steps of: a) transmitting requests to bus addresses of the I2C, respectively; b) upon receipt of a response message transmitted by a device in response to receipt of one of the requests from one of the bus addresses, determining that the device is connected to said one of the bus addresses; and c) according to a lookup table that includes plural of entries, each of which has a corresponding device type and respective address set consisting of at least one reference address conforming with one of the bus addresses, determining a type of the device as one of the device types in the lookup table with reference to said one of the bus addresses.

Abstract: The disclosed apparatus may include a processing unit that (1) identifies an initial forwarding key that corresponds to a forwarding feature of a network device, (2) identifies an initial hash value that represents the initial forwarding key and is derived from the initial forwarding key, (3) identifies an additional forwarding key that corresponds to the forwarding feature of the network device, (4) determines that the initial forwarding key and the additional forwarding key exceed a threshold level of similarity relative to one another, (5) derives an additional hash value that represents the additional forwarding key by applying the initial forwarding key and the initial hash value as inputs to a hash function, and then (6) implements the additional hash value in connection with the forwarding feature of the network device and the forwarding information stored in the storage device. Various other apparatuses, systems, and methods are also disclosed.

Abstract: In one embodiment, a content-addressable memory has multiple blocks of content-addressable memory entries, including different first and second sets of content-addressable memory blocks. One embodiment determines the first set of content-addressable memory blocks based on a content-addressable memory profile identifier and a search key and then performs a first content-addressable memory lookup operation in each of the first set of content-addressable memory blocks, but not in the second set of content-addressable memory blocks, based on the search key. If at least one entry is match, a corresponding result is identified. Otherwise, in one embodiment, the second set of content-addressable memory blocks is determined based on the content-addressable memory profile identifier but not based on the search key, and a search is made therein to identify a matching result or that no match was determined. In one embodiment, a matching result determines how a packet is processed.

Abstract: A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the method, the method includes selecting a row of a memristor array associated with a desired cell, measuring the value of the selected memristor row, and selecting a column of a memristor array associated with the desired cell. The selection of the column and selection of the row selects the desired cell. The method also includes measuring the value of the memristor selected row with the selected desired cell and determining the value of the desired cell based on the value of the selected memristor row and the value of the selected memristor row with the selected desired cell.

Abstract: A method of searching for data stored in a memory, the method including receiving a regex search request, generating a parse tree including fundamental regex operations corresponding to the regex search request, individually analyzing each of the fundamental regex operations of the generated parse tree in a respective time-step, determining a memory address location of data corresponding to the analyzed fundamental regex operations by using a translation table to determine whether the data exists, and using a reverse translation table to determine the memory address location of the data, and outputting data matching the regex search request after analyzing all of the fundamental regex operations of the generated parse tree.

Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.

Abstract: A semiconductor device that includes a memory system is configured to accept input of search data and to search in parallel respective rows of a memory cell array such as a CAM and so forth for data held in a memory. The memory system detects whether an inflow amount of the search data that is input is at least a fixed amount by monitoring a packing ratio of an FIFO buffer that a search command is held. The memory system controls a speed of search processing by dividing the memory cell array into blocks and setting each block as a search processing object in accordance with a result of detection.

Abstract: Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes a SIMD instruction for vector packed tuple cross-comparison in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.

Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.

Abstract: One aspect of the invention relates to a network node for connecting to a Local Interconnect Network (LIN). In accordance with one example of the present invention, the network node includes a bus terminal which is operably coupled to a data line for receiving a data signal, which represents serial data, via that data line. The data signal is a binary signal having high and low signal levels. The network node further includes a receiver circuit which employs a comparator to compare the data signal with a reference signal. The comparator generates a binary output signal representing the result of the comparison. The network node also includes a measurement circuit that receives the data signal and provides a first voltage signal such that it represents the high signal level of the data signal.

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

Abstract: Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.

Abstract: Techniques for improving translation lookaside buffer (TLB) operation are disclosed. A particular entry of the TLB is to be updated with data associated with a large page size. The TLB updates replacement policy data for that TLB entry for that large page size to indicate that the TLB entry is not the least-recently-used. To prevent smaller pages from evicting the TLB entry for the large page size, the TLB also updates replacement policy data for that TLB entry for the smaller page size to indicate that the TLB entry is not the least-recently-used.

Abstract: A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

Abstract: The presented connection processes a stream data by a computer. The data is split into blocks called packets and the task is to search for a match of the data in packets with specified patterns—regular expressions, useful in the field of telecommunication technology and services. The connection may be formed within a semiconductor circuit, which serves for receiving, processing, and sending packets. This semiconductor circuit may be implemented by an FPGA-type circuit. In this way, instead of one circuit implementing the automaton with a total data width Sc, a set of simultaneously operating circuits is implemented forming several identical automata at a smaller data width Sn. This eliminates the exponential rise in the number of symbols in the automaton and at the same time it allows achieving a high throughput of the entire connection.

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache line write back instruction is to indicate a source packed memory indices operand that is to include a plurality of memory indices. The processor also includes a cache coherency system coupled with the packed data registers and the decode unit. The cache coherency system, in response to the vector cache line write back instruction, to cause, any dirty cache lines, in any caches in a coherency domain, which are to have stored therein data for any of a plurality of memory addresses that are to be indicated by any of the memory indices of the source packed memory indices operand, to be written back toward one or more memories. Other processors, methods, and systems are also disclosed.

Abstract: Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.

Abstract: The present disclosure illustrates a ternary content addressable memory (TCAM) device for software defined networking and method thereof. In the TCAM device, M bits of each forwarding rule is stored as a first part into a NAND-Type TCAM, and N bits of the same forwarding rule is stored as a second part into a NOR-Type TCAM. M bits of searching data is compared with the first part to generate a first matching result, N bits of the searching data is compared with the second part to generate a second matching result when the first matching result indicates match, and comparing process for the second part is disabled when the first matching result indicates mismatch. The mechanism is help to improve flexibility of the TCAM in words length and to reduce power consumption.

Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.

Abstract: Aspects of the disclosure provide a circuit that includes a plurality of memory access circuits configured to access a memory to read or write data of a first width. The memory includes a plurality of memory banks that are organized in hierarchy. Further, the circuit includes a plurality of interface circuits respectively associated with the plurality of memory access circuits. Each interface circuit is configured to receive memory access requests to first level memory banks from an associated memory access circuit, segment the memory access requests into sub-requests to corresponding second level memory banks, buffer the sub-requests into buffers associated with the second level memory banks. In addition, the circuit includes arbitration circuitry configured to control multiplexing paths from the buffers to the second level memory banks to enable, in a same memory access clock, memory accesses by the memory access circuits.

Abstract: Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin are disclosed. By the NV-CAM cells employing MTJ differential sensing, differential cell voltages can be generated for match and mismatch conditions in response to search operations. The differential cell voltages are amplified to provide a larger match line voltage differential for match and mismatch conditions, thus providing a larger sense margin between match and mismatch conditions. For example, a cross-coupled transistor sense amplifier employing positive feedback may be employed to amplify the differential cell voltages to provide a larger match line voltage differential for match and mismatch conditions. Providing NV-CAM cells that have a larger sense margin can mitigate sensing issues for increased search operation reliability.

Abstract: A ternary content addressable memory (TCAM) cell may include a first resistive memory element, a second resistive memory element, a third resistive memory element, and a first switching element. The first resistive memory element may be disposed between a true data bit line node and a common node. The second resistive memory element may be disposed between a complement data bit line node and the common node. The third resistive element may be coupled to the common node and a word line node. The first switching element may have a control terminal coupled to the common node.

Abstract: A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.

Abstract: A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells.

Abstract: A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided.

Abstract: A ternary content addressable memory (TCAM) cell is coupled to a first word line and a first match line and includes a first data storage portion coupled to a first search line, a second data storage portion coupled to a complement of the first search line, and a resistor divider portion including two resistive elements coupled in series with the first and second data storage portions of the first TCAM cell. The first and second data storage portions of the first TCAM cell are coupled to a first supply voltage and include two resistive elements coupled in parallel.

Abstract: Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored in a data row of the memory array to generate true and complement sense amplifier inputs. The true and complement sense amplifier inputs are amplified in the sense amplifier to generate a single-ended match signal. The single-ended match signal can be aggregated with other single-ended match signals in the data row to determine whether there is a hit or miss for a compare operation on the entire data row.

Abstract: Aspects of the disclosure provide a circuit that includes a content addressable memory (CAM) array, a first mask circuit and a first encoder. The CAM array has CAM entry lines to be compared with a search key. The CAM array is configured to output a match result indicative entry lines that match the search key. The first mask circuit is configured to selectively mask first one or more portions of the match result to generate a first masked match result indicative first entry lines among the entry lines that match the search key. The first encoder is configured to encode the first masked match result to identify a matching entry line in the first entry lines as a first search result.

Abstract: A content addressable memory device includes a first memory cell having three programmable resistive elements coupled in parallel. The first terminals of the first, second, and third programmable resistive elements are coupled to a first node, the second terminal of the first programmable resistive element coupled to a first source line voltage, the second terminal of the second programmable resistive element coupled to a second source line voltage, and the second terminal of the third programmable resistive element coupled to a first supply voltage. A first access transistor includes a first current electrode coupled to a bit line; a second current electrode coupled to the first node, and a control electrode coupled to a word line. A match line transistor includes a first current electrode coupled to a match line; a second current electrode coupled to a second supply voltage and a control electrode coupled to the first node.

Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

Abstract: Described is a system for detecting and encoding indirect associations in associative memory. The system receives a data storage input in a content-addressable memory (CAM), the data storage input comprising an association between a first data pattern A and a second data pattern B. At least one indirect association related to the data storage input is identified with an inductive logic unit (ILU) interfaced with the CAM, and the indirect association is stored for later recall. A query is generated from the ILU to the CAM to determine whether either of the first data pattern A or the second data pattern B is stored as part of an existing association in the CAM. If either the first data pattern A or the second data pattern B are known, then a new indirect association for the known data pattern is stored.

Abstract: Approaches for an integrated circuit ternary content addressable memory (TCAM) are provided. A system includes an array of XY TCAM cells and respective translation circuits connected to respective pairs of the XY TCAM cells. The system also includes a memory controller structured to provide control signals to the respective translation circuits. The memory controller and respective translation circuits are structured to control the array of XY TCAM cells to perform single cycle update and single cycle search operations.

Abstract: A power train battery assembly of an electric, fuel-cell or hybrid vehicle, said assembly having a plurality of battery cells (16), each encased in an individual and externally-closed cell housing (18), that are combined into a cell stack and moreover having at least one pipe (36) conducting cooling fluid for the removal of heat energy from the battery cells (16). At least one heat-conducting fin (42) that originates from the pipe (36) flatly abuts, at least in sections, at least one cell housing (18).

Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

Abstract: A semiconductor memory device includes a column address generation circuit suitable for generating contents addressable memory (CAM) column addresses for duplicated CAM data, a column selection circuit suitable for allocating columns to the duplicated CAM data according to the CAM column addresses, and a plurality of page buffer units, each unit being coupled to a corresponding memory group through the allocated columns, and suitable for storing the duplicated CAM data in the memory groups through the allocated columns. The allocated columns are of arranged sequentially within each memory group in a circular order, and a part of the CAM column addresses represent columns which are physically apart by a predetermined number of columns within a memory group.

Abstract: Techniques to avoid polarization in a communication network include a network switch or device having a first interface to receive a data unit or packet, and a second interface via which the packet is transmitted from the network device. The network device includes a hash value generator configured to generate, using a depolarizer, a depolarized key from an initial key (where the initial key is based on contents of the packet and the depolarizer is unique to the network device), and to generate a hash value based on the depolarized key and the packet by using a hash function that is common to all network devices in the network. The hash value may be optionally modified to load balance egress traffic of the network device. The network device selects an egress link or port, such as by determining an index into an egress table based on the (modified) hash value.

Abstract: A ternary content addressable memory (TCAM) cell is coupled to a first word line and a first match line and includes a first data storage portion coupled to a first search line, a second data storage portion coupled to a complement of the first search line, and a resistor divider portion including two resistive elements coupled in series with the first and second data storage portions of the first TCAM cell. The first and second data storage portions of the first TCAM cell are coupled to a first supply voltage and include two resistive elements coupled in parallel.

Abstract: An MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.