Abstract: Example memory controllers are disclosed. An example memory controller may include a PHY module including a first PHY terminal connected to a plurality of pins of a device connector, a MAC module including a first MAC terminal that is enabled to form a first lane with the first PHY terminal, and a second MAC terminal that is disabled without being connected to the first PHY terminal, a switch controller configured to receive a signal of a host connector connected to the device connector from at least one of the plurality of pins and output a switch signal in response to the signal of the host connector, and a switch configured to disable the second MAC terminal and form the first lane by connecting the first PHY terminal to the first MAC terminal in response to the switch signal.

Abstract: A target voltage circuit for fast voltage switching is provided. The target voltage circuit is configured to generate a time-variant target voltage(s) to thereby cause a power management circuit to generate a time-variant voltage(s) for a power amplifier circuit. In embodiments disclosed herein, the target voltage circuit receives a number of data signals (e.g., from a transceiver circuit via a parallel bus) that collectively represent a digital target voltage word and maps the digital target voltage word to a target voltage(s). By receiving the digital target voltage word corresponding to the target voltage(s) via the parallel bus, as opposed to directly receiving the target voltage(s) via a serial bus, it is possible to reduce transmission delay. As a result, the power management circuit will be able to switch the time-variant voltage(s) from one voltage level to another based on the target voltage(s) within a defined temporal limit.

Abstract: This disclosure provides methods, devices and systems for reducing PAPR in wireless communications. Some implementations more specifically relate to suppressing the amplitudes of a data signal that exceed a threshold amplitude level. In some implementations, a transmitting device may detect one or more peaks associated with a data signal to be transmitted to a receiving device. A peak may be any sample of a data signal having an amplitude that exceeds a threshold amplitude level. The transmitting device generates peak suppression information indicating the amplitude, a phase and a position of each of the samples associated with the detected peaks. The transmitting device adjusts the data signal by reducing the amplitudes associated with the detected peaks and transmits the adjusted data signal, with the peak suppression information, to the receiving device. In some implementations, the transmitting device may compress the peak suppression information to reduce the overhead of the transmission.

Abstract: A configuration interface bus may be coupled to components of a physical layer (PHY) device. A configuration controller may be coupled with the configuration interface bus and may receive an input signal representing a power state of the PHY device. The configuration controller may further identify a set of instructions that correspond to the input signal and may transmit configuration data via the configuration interface bus to one or more of the components of the PHY device in response to an execution of the set of instructions. The operation of the one or more components of the PHY device may be based on the configuration data.

Abstract: An apparatus and method that captures a complete history of serial network Link Training negotiations by continuously monitoring multiple analog signals representing both sides of full duplex lanes in real-time by pattern matching the Link Training Frame Marker and the subsequent negotiation request/response data values. The apparatus and method compare the digitized version of the incoming signal against a nominal pattern at the start to find the Frame Markers and Control Channel data, storing only those Control Channel data values that do not match the current compare pattern, and further by updating the current compare pattern to the new pattern just received, so that only the transitions in the data values are stored, thereby vastly reducing the amount of data presented to the user, but nonetheless retaining the complete substantive history of the Link Training negotiations.

Abstract: An encoding and transmitting system for a digital isolator system includes a transmitter for transmitting combined edge indicator signals through an isolation barrier, an encoder for generating the combined edge indicator signals based on first and second signals, a refresh clock generator for generating a refresh clock signal based on the first signal, and a refresh edge generator for masking at least a portion of the refresh clock signal, such that the portion of the refresh clock signal is not reflected in the second signal. The isolation barrier of the digital isolator system may be a capacitive isolation barrier for galvanically isolating a receiver from the transmitter. If desired, the refresh edge generator may include a refresh mask generator, one or more logic gates, and a glitch filter. A method of operating a digital isolator system is also described.

Abstract: The disclosure relates to an electronic device and a wireless communication method in a wireless communication system. According to the disclosure, the electronic device comprises one or more processing circuits. The processing circuit is configured to execute the following operation: configure timing mapping information between a downlink subframe carrying uplink scheduling grant signaling and an uplink subframe carrying uplink transmission, comprising physical uplink shared channel PUSCH transmission, scheduled by the uplink scheduling grant signaling, and performed on an unlicensed channel by user equipment in the wireless communication system. By means of the electronic device and the wireless communication method in the disclosure, a timing mapping relationship between a downlink subframe carrying uplink scheduling grant signaling and an uplink subframe carrying uplink transmission comprising PUSCH transmission can be determined, thereby realizing effective utilization of an unlicensed channel.

Abstract: The embodiments of the invention relate to a line switching component separable from a line card of a network node. The line switching component contains at least one input port for receiving an optical input signal from an optical transport network and at least one output port for transmitting an optical output signal to the optical transport network. The line switching component further contains at least one further output port configured to be connected to an input port of at least one optical interface of the line card and at least one further input port configured to be connected to an output port of the at least one further optical interface of the line card. The line switching component further contains a switchable optical path system configured to operate the line switching component in a first operation mode and to operate the line switching component in a second operation mode.

Abstract: A method is provided for identifying a lethargic drive. The method includes identifying a timing bucket unique to a drive located in a redundant array of independent disks (RAID) configuration, computing a delta-count for the timing bucket at a predetermined time, including determining a difference between a counter for the timing bucket at the predetermined time and the counter for the timing bucket at a time when the drive was replaced within the RAID configuration, comparing the delta-count for the timing bucket to a predetermined threshold, and determining whether the drive is lethargic, based on the comparing.

Abstract: According to one embodiment, a transmission system may include a plurality of signal processing apparatuses. The signal processing apparatus are connected in series. The signal processing apparatus includes a plurality of signal processors, and a switcher. The signal processors generate an output signal by performing signal processing of an input signal from an earlier-stage signal processing apparatus. The signal processors supply the output signal into which is included an abnormality signal if the input signal does not include the abnormality signal and also the output signal does not satisfy the criteria. The switcher receives a plurality of output signals output from the plurality of signal processors. The switcher supplies an output signal of the plurality of output signals.

Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

Abstract: Systems, methods, and apparatus for data communication are provided. An apparatus maybe configured to generate a mask field in a packet to be transmitted through an interface to a slave device, the mask field having a first number of bits, provide a control-bit field in the packet, the control-bit field having a second number of bits, where the second number of bits is less than the first number of bits, and transmit the packet through the interface. The packet may be addressed to a control register of the slave device. The control register may have the first number of bits. Each bit in the control-bit field may correspond to a bit of the control register that is identified by the mask field.

Abstract: Example embodiments of the present invention relate to an optical node comprising of at least two degrees, a plurality of directionless add/drop ports, a plurality of primary WDM transmitters and receivers, and at least one protection WDM transmitter and receiver, wherein the at least one protection WDM transmitter and receiver can transmit and receive in place of any of the plurality of primary WDM transmitters and receivers.

Abstract: A system and methods are provided for conveying connection-oriented communications (e.g., textual messages among multiple users) via a protocol such as HTTP (Hypertext Transfer Protocol). When a device operating a communication application that features a custom application layer protocol for formatting messages for transmission cannot connect to the system hosting the application using a default protocol stack that include the custom application layer protocol, it instead connects using HTTP's chunked mode of transfer encoding. Each outgoing communication is encapsulated in a separate HTTP chunk, and communications to multiple different users may be conveyed via the one connection. Incoming communications (e.g., from the multiple users) are received as separate chunks and are unwrapped or de-encapsulated to retrieve the communication for presentation to a user.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to determine when a peripheral is connected to the electronic device, determine a peripheral identification for the peripheral, and monitor the data going to and from the peripheral. Based on the monitored data, a type for the peripheral can be determine. The peripheral identification can be compared with the determined type for the peripheral and if they do not match, then communication to and from the peripheral can be blocked.

Abstract: Data unit identification for compressed video streams is described. In one or more implementations, a compressed video stream is received at a computing device and a determination is made as to whether prior knowledge is available that relates to the compressed video stream. Responsive to the determination that prior knowledge is available that relates to the compressed video stream, the prior knowledge is employed by the computing device to perform data unit identification for the compressed video stream. In one or more implementations, SIMD instructions are utilized to perform pattern (0x00 00) search in a batch mode. Then a byte-by-byte search is performed to confirm whether the pattern, 0x00 00, found is part of a start code, 0x00 00 01, or not.

Abstract: There are disclosed traffic generators, methods, and computer readable media to generate packets for testing a network under test. A first parameter memory bank may be active when a first bank select data has a first value and inactive when the first bank select data has a second value. A second parameter memory bank may be inactive when the first bank select data has the first value and active when the first bank select data has the second value. One or more engines may generate packets based on parameters stored in the active one of the first and second parameter memory banks. A processor coupled to the first and second parameter memory banks may write parameter data into the inactive one of the first and second parameter memory banks.

Abstract: In one embodiment, a network device, such as a router, receives a frame containing a message from a first terminal unit. The network device modifies the received frame by replacing an original value of an originator identifier field in the frame with a new value that is locally unique on a particular data link. The network device than forwards the modified frame to a selected second terminal unit selected from a plurality of terminal units.

Abstract: There are provided a communication apparatus capable of performing voice communication via an IP network, and performing FAX communication using a deemed voice, and a method of controlling the same. At the time of reception of an incoming call, the apparatus determines whether an incoming voice communication call or digital data has been received. If it is determined that the incoming voice communication call has been received and there is an already connected voice communication section, the SLIC superimposes a tone of a notification of the incoming call during voice communication on a voice during voice communication. When the telephone instructs to switch to the incoming call, the apparatus establishes a new session for the incoming call, and controls the selector to connect the already connected voice communication session to the digital modem to send a holding tone.

Abstract: A method and a target node for preventing collisions between networks communicating based on a carrier sense multiple access/collision avoidance (CSMA/CA) scheme, are provided. The method includes synchronizing an object network with a neighboring network. The method further includes allocating, to the object network, a slot index based on a number of the networks, and a contention window (CW) size. The method further includes setting, for the object network, a back-off counter value based on the CW size. The method further includes reducing the back-off counter value based on a channel state of the object network, and the slot index. The method further includes transmitting data related to the neighboring network based on the back-off counter value.

Abstract: Broadband access networks are driving the upgrade of DWDM networks from 10 Gb/s per channel to more spectrally-efficient 40 Gb/s or 100 Gb/s. Signal quality degradation due to linear and non-linear impairments are significant and error control coding and signal processing solutions play increasingly key roles in meeting increasing demand, providing improved quality of service, and reduced cost. It would be beneficial to reduce the power consumption of optical receivers for optical links exploiting for example LPDC encoding. Accordingly, the inventors have established a low complexity soft-decision front-end compatible with deployable LDPC codes in next-generation optical transmission systems. Beneficially the optical receiver design can be retro-fitted into deployed hard-decision based optical systems and replaces the 3-to-2 encoder of the prior art in the electrical portion of the receiver with a single gate design. Further, the design may act as a 2-bit Flash ADC in multimode fiber based optical receivers.

Abstract: A time division multiplexing intra-chip communication system comprising at least one communication link. Such communication link comprises serialization and transmission circuitry, reception and deserialization circuitry, and at least one coaxial or wafer-level package transmission line interconnect therebetween. Such coaxial or wafer-level package transmission line interconnect may carry signals from such transmit circuitry to such receive circuitry. Such intra-chip communication links may achieve single-cycle operation or multi-cycle operation. Single single-cycle operation may be conducive to synchronous FSM design methodologies while multi-cycle operation may be conducive to data transfers to and from memory.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: An electronic communication system including at least one first communication unit and one second communication unit which are connected to one another by means of at least one first data line. The communication system has a data transmission protocol according to which, in at least one first data transmission mode for synchronized data transmission, the first communication unit transmits a data request signal or a clock signal to the second communication unit via the first data line at least once and the second communication unit transmits a data signal to the first communication unit via the first data line in response to the data request signal or the clock signal.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: Disclosed is the radio (wireless) communication system providing a radio communication service and the terminal, and more particularly, a method of handling time alignment command during a random access procedure in an Evolved Universal Mobile Telecommunications System (E-UMTS) evolved from the Universal Mobile Telecommunications System (UMTS) or a Long Term Evolution (LTE) system is provided.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: A network device including a physical layer device and a media access controller. The physical layer device includes a first interface, and is configured to receive packets including a first packet and a second packet. The media access controller includes a second interface connected to the first interface of the physical layer device. The physical layer device is configured to: in response to the first packet, generate a power signal; transition at least one of the first interface and the second interface from being powered OFF to being powered ON; and output the power signal to the media access controller. The media access controller is configured to: receive the power signal; in response to the power signal, transition from being powered OFF to being powered ON; and subsequent to being powered ON, receive the second packet from the physical layer device via the first interface and the second interface.

Abstract: A serializer and deserializer utilize upsampling and downsampling to operate over a broad range of frequencies. The serializer includes a bit repeater and a high-speed serializer. The bit repeater receives data to be serialized, upsamples the received data, and supplies the upsampled data to the high-speed serializer. The deserializer includes a high-speed deserializer and a downsampler. The high-speed deserializer supplies parallelized data to the downsampler. The downsampler decimates the parallelized data and supplies the decimated data to an output of the deserializer.

Abstract: Method embodiments are provided to improve efficiency of systems operating on internet protocol (IP) over Infiniband (IB) networks. In an embodiment, by way of example only, a method is provided for implementing redundancy for IB networks. The method includes detecting a failure at a first source port of a source node having a plurality of source ports, selecting a new source port, sending an address resolution protocol (ARP) message to one or more other nodes in communication with the source node including an IP address of the source node and IB address of the new source port of the source node, and re-balancing host traffic.

Abstract: A first multiplexer, at each given cycle, outputs a second input data signal, after outputting a first input data signal. A second multiplexer, at each given cycle, outputs a fourth input data signal, after outputting a third input data signal. The second multiplexer outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer. At each given cycle, a third multiplexer, after outputting the first input data signal and the second input data signal output from the first multiplexer, outputs the third input data signal and the fourth input data signal output from the second multiplexer.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: A connector assembly includes a first connector, a second connector, a first controller, an inter-integrated circuit (I2C), and a second controller. The first connector is electrically connected between a first element and the first controller. The second connector is electrically connected between a second element and the second controller. The I2C is electrically connected between the first controller and the second controller. The first connector receives and outputs a number of parallel signals from the first element. The first controller converts the parallel signals into two serial signals. The I2C transmits the two serial signals to the second controller. The second controller converts the two serial signals into a number of parallel signals.

Abstract: A data division unit of a serial transmission device divides transfer data to generate a plurality of divided data, a plurality of parallel-to-serial conversion units converts the divided data into serial data according to timing control provided by a transmission control unit to transmit the serial data to a plurality of data signal lines connected to the plurality of parallel-to-serial conversion units, a plurality of serial-to-parallel conversion units of a serial reception device receives the serial data from the data signal lines connected thereto to convert the serial data into parallel data, and a data restoration unit combines the parallel data, which are converted by the plurality of serial-to-parallel conversion units, to restore the transfer data in an order of completion of the conversion.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: A crossbar may be coupled between a plurality of PHY devices configured to provide physical layer functions according to an Open Systems Interconnection, OSI, model and a plurality of MAC devices configured to provide data link layer functions according to the OSI model. First data couplings may be provided through the crossbar between the plurality of PHY devices and the plurality of MAC devices during a first time period. Second data couplings may be provided through the crossbar between the plurality of PHY devices and the plurality of MAC devices during a second time period, with the first and second data couplings being different. Related network elements, interfaces, and networks are also discussed.

Abstract: A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.

Abstract: The present invention discloses a method of detecting and correcting skew across a plurality of transmitting lanes. Through the use of an N framer system, including a frame start signal and a frame synchronization signal, skew can be detected and corrected by writing data from a plurality of framers into offsetting bit locations of a plurality of buffers. The present invention also provides a method of transmitting data in a multiple lane distribution (MLD) transmission system.

Abstract: A gateway apparatus 110 includes: a communication unit 111 communicating a frame signal conforming to an IuUP (Iu User Plane) protocol with a wireless base station controller connected to a circuit switching network 101; a determination unit 112 for determining whether the frame signal received by the communication unit indicates a time alignment request for a sound signal to a circuit switching network or not; a conversion unit 113, converting information included in the frame signal to information to be set in a call control signal of an IMS (IP Multimedia Subsystem) when the frame signal indicates a time alignment request; and a call control signal transmission unit 114 transmitting the call control signal including the converted information to a communication apparatus in the IMS 102.

Abstract: An information processing apparatus is provided which includes a signal multiplexing unit for multiplexing a plurality of transmission signals, each in a different frequency band and not containing a DC component, and a power signal supplied from a DC power supply and generating a multiplexed signal, a single signal cable through which the multiplexed signal generated by the signal multiplexing unit is transmitted, and a signal separating unit for separating the multiplexed signal transmitted through the signal cable into signals, each in a frequency band of one of the plurality of transmission signals, and a signal in a frequency band of the power signal.

Abstract: A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.

Abstract: A system and a method for transmitting serial data, and a recording medium thereof are provided, in which a host is connected to a portable device through network, and the portable device is connected to a serial device. The host includes a host control module, a data convert module, and a first communication module. The host control module generates and receives serial data. The data convert module is connected between the first communication module and the host control module to convert formats of serial data and network packet data. The first communication module performs communication of network packet data between the data convert module and the portable device. The portable device is configured between the host and the serial device, and converts formats of the serial data and the network packet data by using a bridge module, so as to establish connection between the host and the serial device.

Abstract: A method, system, and computer program product for routing data in a network. The data is routed from a source in the network to a destination in the network along a path from the source to the destination through a plurality of nodes in the network using state information. The plurality of nodes forms the network and comprises static nodes and mobile nodes. In response to a loss of a route at a node in the mobile nodes, the node sends the data is sent to all other nodes in the plurality of nodes. Responses are received at the node from the destination through a number of paths from the destination to the node. Updated state information for the node is identified using the responses. The data is sent from the node to the destination along a selected route for the node using the updated state information.

Abstract: A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol.

Abstract: An IS-OFDM system for ultra-wideband (UWB) wireless communications that suppresses narrow-band interference, comprising an in-premises base station (IBS) is described. The IBS further comprises an IS-OFDM transceiver for communicating with a plurality of in-premises terminals (ITs) without creating interference outside an in-premises perimeter. Further, a method for operating an IS-OFDM system for ultra-wideband (UWB) wireless communications that suppresses narrow-band interference and provides local area networking services, in-premises distribution of broadcast cable channels and in-premises wireless access and routing to external networks is described, without creating interference outside an in-premises perimeter.

Abstract: A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: A request to receive multicast data, associated with a multicast group, may be transmitted. The request may be transmitted via a tunnel. Group keys may be received in response to the request. The group keys may be based on the multicast group. An encapsulated packet may be received via another tunnel. The encapsulated packet may be processed, using the group keys, to obtain a multicast packet associated with the multicast data. The multicast packet may be forwarded to at least one multicast recipient.

Abstract: A method for transferring plural pieces of packet data from a plurality of terminal devices to a host device with an IEEE 1394 serial bus. The method includes transferring the plural pieces of packet data from the terminal devices to a transfer controller, storing the plural pieces of packet data in a buffer memory of the transfer controller, and sequentially transferring the packet data stored in the buffer memory to the host device. This method substantially increases data transfer speed without increasing the transfer speed at nodes and cables when transferring data with the IEEE 1394 serial bus.