Abstract: A method for controlling a multi-port Network Interface Card (NIC) is provided. In a computer using the multi-port NIC with a plurality of NIC ports, a plurality of control options is set into a Basic Input/Output System (BIOS) setup menu, so that a user individually controls the NIC ports. Furthermore, due to the characteristic that after a reference code process in the BIOS restarts a system, the set of hardware becomes effective, an action of controlling the NIC ports is set before a reference code process restarts the system.

Abstract: A space switch includes a buffer having a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, a plurality n of buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-nth that of the input data and a switch fabric connected to the buffers for matching buffer data throughput with switch data throughput. Preferably the buffer is a bifurcate buffer. This space switch described ensures matching of buffer and switch fabric throughput.

Abstract: Disclosed are a Time Division Multiplexing (TDM) communication system with a parallel structure and a method for the same. A transmission apparatus of the TDM communication system with the parallel structure includes a Time Division Demultiplexer (TDDM) to perform time division demultiplexing of inputted first serial signals to thereby output the demultiplexed serial signals as a plurality of parallel signals, a plurality of modulators to respectively modulate the outputted parallel signals; a Time Division Multiplexer (TDM) to adjust a multiplexing ratio according to channel-related information, and to perform time division multiplexing of each of the modulated parallel signals in the adjusted multiplexing ratio to thereby output the multiplexed parallel signals as second serial signals, and a transmission antenna to transmit the outputted second serial signals.

Abstract: The present invention discloses a method of detecting and correcting skew across a plurality of transmitting lanes. Through the use of an N framer system, including a frame start signal and a frame synchronization signal, skew can be detected and corrected by writing data from a plurality of framers into offsetting bit locations of a plurality of buffers. The present invention also provides a method of transmitting data in a multiple lane distribution (MLD) transmission system.

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: An imaging apparatus includes an imaging element, an image signal transmitter, an image signal receiver, a signal processor and a control unit. The imaging element includes pixels arranged in two-dimensional array. The pixels output an imaging signal in synchronization with a first synchronizing signal. The image signal transmitter superimposes a second synchronizing signal on the imaging signal and transmits an image signal. The second synchronizing signal indicates a start position in vertical and horizontal directions in the two-dimensional array and is different from the first synchronizing signal. The image signal receiver receives the image signal from the image signal transmitter, and separates the received image signal into the imaging signal and second synchronizing signal. The signal processor processes the separated imaging signal based on the separated second synchronizing signal.

Abstract: Apparatus having corresponding methods comprise: a physical-layer input circuit to receive first signals representing first data; a first serializer to transmit a serial stream of the first data; and a magic packet circuit to generate a magic packet signal when the first data includes a magic packet.

Abstract: A system and method are provided for programming the parallel path width in a serial-to-parallel path transceiver. Initially, the transceiver is programmed to select a link layer (layer 1) protocol, such as Gigabit Ethernet (GBE) or SONET. The method accepts serial digital data in the selected protocol at a serial interface, and differentiates the serial data into units of i bits per unit. Another programmed selection is made between n number of unique data interfaces, where each interface includes a plurality of parallel paths. The serial digital data is assigned to z selected data interfaces and transmitted. In one aspect, the serial data is assigned to m number of parallel path channels, where m is less than, or equal to z, and less than i. In another aspect, the frequency at which each data interface parallel path transmits data is selected.

Abstract: Certain embodiments of the present disclosure relate to methods for peak-to-average power ratio (PAPR) reduction of a transmission signal in a single carrier frequency division multiple access (SC-FDMA) system. The proposed methods and systems are based on manipulations of an SC-FDMA transmission signal in a time- and/or a frequency-domain.

Abstract: A signal transmitting device includes: a synchronous-data detecting unit that detects, from parallel data specified by a predetermined format and including video data and audio data, synchronous data for controlling synchronization of the parallel data; an audio extracting unit that stores the audio data in an audio memory; a clock extracting unit that extracts a reference clock from the parallel data; a multiplexing unit that multiplexes the audio data and the synchronous data in a horizontal auxiliary data space of the video data; a control unit that controls, on the basis of the synchronous data and the reference clock, timing of the multiplexing unit for multiplexing the audio data with the video data; and a parallel serial converting unit that converts the video data multiplexed with the audio data by the multiplexing unit into a transmission stream specified by a Level A of a 3G-SDI format.

Abstract: An interface device includes a parallel-to-serial converting unit, a driver, a receiver, and a serial-to-parallel converting unit. The parallel-to-serial converting unit converts parallel signals into a single-ended signal. The driver converts the single-ended signal from the parallel-to-serial converting unit into a differential signal and transmits the differential signal to an external device via signal lines. The receiver converts a differential signal received via the signal lines from an external device into a single-ended signal. The serial-to-parallel converting unit converts the single-ended signal from the receiver into parallel signals. A direction in which the differential signal is to be transmitted is determined based on a control signal.

Abstract: The present invention discloses a method of detecting and correcting skew across a plurality of transmitting lanes. Through the use of an N framer system, including a frame start signal and a frame synchronization signal, skew can be detected and corrected by writing data from a plurality of framers into offsetting bit locations of a plurality of buffers. The present invention also provides a method of transmitting data in a multiple lane distribution (MLD) transmission system.

Abstract: A method for serially transmitting data from a system including a serializer for converting a parallel data signal into a serial data signal and a parallelizer for converting the serial data signal into the parallel data signal includes storing a value of the parallel data signal in a register in the parallelizer, generating a serial clock signal independent from a clock signal of the parallel data signal using an external clock source, and recovering the parallel data signal by using the value of the parallel data signal stored in the register.

Abstract: A network system, having an array of processing engines (“PEs”) and a delay line, improves packet processing performance for time division multiplexing (“TDM”) sequencing of PEs. The system includes an ingress circuit, a delay line, a demultiplexer, a tag memory, and a multiplexer. After the ingress circuit receives a packet from an input port, the delay line stores the packet together with a unique tag value. The delay line, in one embodiment, provides a predefined time delay for the packet. Once the demultiplexer forwards the packet to an array of PEs for packet processing, a tag memory stores the tag value indexed by PE number. The PE number identifies a PE in the array, which was assigned to process the packet. The multiplexer is capable of multiplex packets from PE array and replacing the packet with the processed packet in the delay line in response to the tag value.

Abstract: Method and system for serially sending data signals captured from multiple sources through a single unidirectional isolation component. Data signals from respective multiple sources are captured in parallel. Such captured data signals are stored in respective storages. The stored data signals are transferred, in serial, from the storages to a single unidirectional isolation component. Multiple concurrent processes for parallel data signal capture and serial data signal transfer via a single unidirectional isolation component are implemented so that the sampling effect on a first of the multiple processes is minimized.

Abstract: A scaling device or striper improves the lane efficiency of switch fabric. The striper controls or adjusts transfer modes and payload sizes of a large variety of devices operating with different protocols. The striper interfaces between network devices and the switch fabric, and the resulting switching system is configurable by a single controller. A source device sends a data packet to its corresponding striper for transmission across the switch fabric to a destination device. The corresponding striper parses the packet to determine its type and payload length, and divides the packet into numerous smaller segments when the payload length exceeds a predetermined length. The segments may be stored in the striper to adapt to the available bandwidth of the switch. The segments are sent across the switch fabric and reassembled at a destination striper. The packet as reassembled is forwarded to the destination device.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: A system receives serial messages from a device under test. The system includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) data bits based on the data frames. A plurality of virtual JTAG test access ports are configured to i) receive the JTAG data bits and ii) shift the JTAG data bits between the plurality of virtual JTAG test access ports.

Abstract: A scheduling algorithm is disclosed that allows mobile units, participating in an ongoing communications session, to temporary perform channel-demanding communications operations without ending the session and that is useful in the case of no free radio channels. The algorithm is based on selecting a radio channel for transmitting a radio block based on information of a previous radio channel, no which a previous radio block has been transmitted. The radio block and the previous radio block are based on common information. A mobile unit participating in the communications session selects whether to perform any channel-demanding communications operations on the selected radio channel. By limiting any such other channel-demanding operations to only the selected radio channel, the probability of loss of useful data for the mobile unit during the communications session is minimized.

Abstract: An IS-OFDM system for ultra-wideband (UWB) wireless communications that suppresses narrow-band interference, comprising an in-premises base station (IBS) is described. The IBS further comprises an IS-OFDM transceiver for communicating with a plurality of in-premises terminals (ITs) without creating interference outside an in-premises perimeter. Further, a method for operating an IS-OFDM system for ultra-wideband (UWB) wireless communications that suppresses narrow-band interference and provides local area networking services, in-premises distribution of broadcast cable channels and in-premises wireless access and routing to external networks is described, without creating interference outside an in-premises perimeter.

Abstract: Secure tunneled multicast transmission and reception through a network is provided. A join request may be received from a second tunnel endpoint, the join request indicating a multicast group to be joined. Group keys may be transmitted to the second tunnel endpoint, where the group keys are based at least on the multicast group. A packet received at the first tunnel endpoint may be cryptographically processed to generate an encapsulated payload. A header may be appended to the encapsulated payload to form an encapsulated packet, wherein the header includes information associated with the second tunnel endpoint. A tunnel may be established between the first tunnel endpoint and the second tunnel endpoint based on the appended header. The encapsulated packet may be transmitted through the tunnel to the second tunnel endpoint. The second tunnel endpoint may receive the encapsulated packet. Cryptographic processing of the encapsulated packet may reveal the packet having a second header.

Abstract: A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue during a first system clock cycle, where Q<P, and sends, during the first system clock cycle, the Q data units to a processing device configured to process a maximum of Q data units per system clock cycle.

Abstract: An interface module comprises a serial signal transceiver to be connected to an external transmission path and an interface processing unit connected to the transceiver. The interface processing unit comprises a serializer/deserializer circuit, an encoder/decoder, a protocol processing unit having at least two kinds of selectable protocol processing functions, and a communicate mode switch circuit for changing reference clock to be supplied to the serializer/deserializer circuit in conjunction with switching of the protocol processing function from one to another.

Abstract: An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator performs a test on the integrated circuit. The embedded in-circuit emulator generates a testing result based on the test on the integrated circuit. Trace logic to generate trace data based on the testing result, the trace data being in a parallel format. A serializer is located on the integrated circuit. The serializer converts the parallel format of the trace data into a serial format. The serializer serially outputs the trace data in the serial format from the integrated circuit.

Abstract: The present invention provides an architecture for a platform, which includes (1) gates located in a central area of a die for supporting an application layer; (2) a SerDes region located at one side of the die for holding at least one SerDes device; (3) a Link Layer Controller region, located adjacent the SerDes region and between the SerDes region and the gates, for supporting the at least one SerDes device; and (4) at least one RAM array for supporting the at least one SerDes device, the at least one RAM array being located at least one of adjacent the gates or between the gates and the Link Layer Controller region.

Abstract: Devices, softwares and methods enable SIP devices to operate in H.323 networks, and devices, softwares and methods enable H.323 devices to operate in SIP networks. Messages that initiate communication from a first protocol are translated into the appropriate messages of the second, responded to, and the replies are translated back into the first. Routing by the legacy network is thus seamlessly exploited.

Abstract: The number of channels is changed in accordance with an operation mode in an image pickup apparatus. An image-pickup control unit 240 determines the number of operation channels W in accordance with an operation mode. A sensor unit 210 outputs an image pickup signal corresponding to each pixel in accordance with the number of operation channels W. A data sending unit 220 performs serial conversion on image pickup signals, and transfers them to the image processing unit 300 using a high-speed interface (a signal line 229) such as an LVDS in accordance with the number of operation channels W. A data receiving unit 311 performs parallel conversion on the transferred serial signal for each of the channels in units of M bits. A data reconstruction unit 500 detects a synchronization code embedded in the parallel signals, extracts data windows, and supplies, to a signal line 319, image pickup signals of bit length n which are reconstructed from the data windows.

Abstract: In a mobile terminal in which a communication service is being executed, communication networks can be switched without causing a loss of communication data while maintaining the execution of the communication service. In a server which provides a communication service via communication networks provided in parallel and a mobile terminal which obtains the communication service using one of the communication networks, the mobile terminal activates another communication network in parallel while maintaining execution of the communication service to thereby transmit pieces of information having the same content, generated by copying, through the respective communication networks, and switches the one communication network being used to the other communication network.

Abstract: A network device includes a multi-port media access controller (MAC) device that comprises a plurality of MAC devices. Some of the MAC devices output respective data streams at different speeds. A plurality of speed translators translates the speeds of the respective data streams to be greater than or equal to a highest output speed of the plurality of MAC devices and generates parallel speed translated data streams. A multiplexer multiplexes the parallel speed translated data streams to generate a multiplexed data stream corresponding to one of the plurality of MAC devices with the highest output speed defined by the parallel speed translated data streams. A first serializer and deserializer receives the multiplexed data stream that is encoded at a physical coding sublayer and serially transmits the multiplexed data stream to a multi-port physical layer device.

Abstract: A synchronization scheme is provided that includes querying a managed device to obtain an initial device state, synchronizing the device state in a plurality of management processes, detecting a change in the initial device state, and maintaining a synchronized current device state between the managed device and the plurality of management processes.

Abstract: A data transfer apparatus includes a clock generation unit to generate a clock signal, a control unit to output parallel data and a reset signal, and a plurality of transmission units. Each of the plurality of transmission units uses continuous rising edges of a bit clock to sample the reset signal multiple times so that a phase shift of the reset signal between the transmission units is reduced, and the phase of the frequency dividing clock is aligned in each transmission unit.

Abstract: A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link having a width of N or multiple sublinks having a width less than N based on a respective value of the respective signal on the one or more control lines.

Abstract: This invention relates to a data transmitting apparatus and a data receiving apparatus, which multiplexes and transmits HD-SDI signals, and which receives the multiplexed and transmitted HD-SDI signals. The data transmitting apparatus is characterized by being equipped with a parallel data forming section which forms word string data De based on HD-SDI signals DHS of n channels, a data multiplexing section which obtains multiplex word string data Dm based on De, a multiple channel data forming section which forms bit string data DSX of m channels from Dm, a data multiplexing and P/S converting section which forms bit string data DTG based on DSX and in which a bit rate is set to 10 Gb/s or more, and an electric photo converting section which sends away DTG.

Abstract: A communications module including an electrical interface for operatively connecting the communications module to an electric device is disclosed. The electric interface enables data communication between the communications module and the electric device in either a serial mode or parallel mode. The communications module includes: one or more electrical connectors arranged in the electric interface, a Dual Port RAM is connected to the electrical interface for providing parallel transfer of data through the electrical interface, and a control unit connected to at least one of the one or more electrical connectors, wherein the control unit is adapted to determine the value of one or more signals applied on the at least one of the one or more electrical connectors and enable either serial or parallel data communication through the electrical interface depending on the value of the one or more signals.

Abstract: The present invention discloses a method of displaying a sequence for sharing digital data items with a set of recipients using a terminal capable of using at least two communication modes for communicating with the recipients. The method comprises the steps of obtaining a first list of recipients communicating with the terminal according to a first communication mode, obtaining at least one second list of recipients communicating with the terminal according to a second communication mode, displaying on the mobile terminal a representation of each recipient in the lists thus obtained, selecting at least one representation, determining the communication mode to be used according to the representation selected and sending data item to the recipient whose representation was selected according to the determined communication mode. The invention also describes a sharing device adapted to implement the method, in particular a digital camera.

Abstract: Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.

Abstract: A communication apparatus includes at least one input port, multiple output ports, at least one Serial-to-Parallel (S/P) converter and at least one Parallel-to-Serial (P/S) converter. The S/P converter is operative to receive from the input port an input data stream that is to be cross-connected to a destination output port, and to separate the input data stream into multiple sub-streams. Each of the switching planes includes at least one input for receiving a respective sub-stream from the S/P converter; multiple outputs, each output associated with a respective one of the output ports; and switching circuitry, which is configured to switch the respective sub-stream to the output that is associated with the destination output port. The P/S converter is coupled to the outputs of the switching planes so as to combine the multiple sub-streams switched by the switching circuitry into a combined output data stream at the destination output port.

Abstract: In accordance with the invention, time slot interchange switches (“TSIS”) with bit error rate testing are described. The bit error rate testing includes creating a channel of data appropriate for bit error rate testing and monitoring the bit error rate testing on that channel.

Abstract: A system for receiving serial messages from a device under test includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) data bits based on the data frames. A plurality of virtual JTAG test access ports are configured to i) receive the JTAG data bits and ii) shift the JTAG data bits between the plurality of virtual JTAG test access ports.

Abstract: The present invention relates to an expandable structure for peripheral storage devices. The expandable structure includes an interface controller having a plurality of connecting ports for serial data transmission; and a Port Multiplier electrically connected to one of the connecting ports of the interface controller for serial data transmission, and the Port Multiplier having a plurality of expanded connecting ports, wherein each of the expanded connecting ports is capable of connecting to a peripheral storage device with a parallel data transmission mode or a peripheral storage device with a serial data transmission mode.

Abstract: A method of and system for transferring overhead data from a sender to a receiver over a serial interface is provided. The overhead data is transferred over one or more data lines of the interface during one or more time periods in which excess bandwidth is available on the one or more data lines or while the transfer of the overhead data does not substantially impede the throughput of the payload transfer.

Abstract: A serial interface circuit includes a plurality of serial transmitters for a plurality of channels, respectively; and a plurality of serial receivers provided for said plurality of channels and connected with said plurality of serial transmitters, respectively. Each of said plurality of serial transmitters transmits a serial signal. Each of said plurality of serial receivers includes a receiver circuit configured to convert the serial signal into a data sequence; n (n is an integer more than 1) register groups configured to shift the data sequence; a data processing circuit configured to perform a data process on said data sequence based on n outputs of said n register groups and a detection result; and a header detecting circuit configured to detect a header of the data sequence when said b register groups from a first register group to a bth register group among said n register groups shift the data sequence, and to output the detecting result to said data processing circuit.

Abstract: A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.

Abstract: Synchronization management is provided for a continuous serial data streaming application wherein the serial data stream includes a plurality of consecutive, identical-length segments of consecutive serial data bits. Synchronization management bits are provided in each segment. The synchronization management bits are programmed such that the synchronization management bits contained in first and second adjacent segments of the serial data stream will bear a predetermined relationship to one another. At the receiving end, the synchronization management bits are examined from segment to segment. In this manner, synchronization can be monitored, synchronization loss can be detected, and synchronization recovery can be achieved.

Abstract: A method, mobile electronic device and system for synchronizing hand-off of a voice media session between a WAN/cellular network and a WLAN network. When a hand-off occurs, the connection with both networks is temporarily maintained and the voice data on both connections compared to determine differences in the delays experienced over both connections. The timing of one or both voice streams is adjusted to synchronize the voice streams, and then the handoff is completed.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Disclosed are an apparatus and method for removing noise contained within a usable frequency band of a mobile communication terminal. The apparatus includes a multiplier for multiplying a main clock of the mobile communication terminal by a predetermined integer to generate a reference signal; a multiplexer for multiplexing parallel signals, the parallel signals being transmitted to a peripheral device inside the mobile communication terminal, using the reference signal, and converting the parallel signals into serial signals; a demultiplexer for demultiplexing the serial signals to convert the serial signals into parallel signals; and a frequency divider for recovering the reference signal of the serial signals transmitted from the demultiplexer into the main clock.

Abstract: A digital signal receiver for a high-bitrate digital signal has a serial signal input (20, 20?) and a number of N parallel digital signal outputs (26) with N>1. The receiver contains at least N+1 digital sampling channels (31-35), a Q-monitor (37, 38) for comparing the output signal of at least two of the sampling channels (31-35), and a switch fabric (36) for controllably connecting N of the sampling channels (31-35) to the outputs (26) and at least two of the sampling channels (31-35) to the Q-monitor (37, 38). This allows to use N of the sampling channels to provide the N output signals while at the same time, the at least one remaining sampling channel can be used by the Q-monitor to scan an eye diagram.

Abstract: Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

Abstract: A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.