Abstract: An optical packet exchange apparatus and an optical switch in which search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit devoid of a packet to be received is reduced to enable fast switch control even in cases wherein the number of channels of the exchange apparatus is increased or network speed is higher. A plurality of input units, a plurality of output units and an optical switch are provided. Each input unit includes an input buffer unit, a parallel/serial conversion unit, an electrical/optical conversion unit, and a dummy packet insertion unit for sending a dummy packet if there is no packet to be transmitted. Each output unit includes an exchange counterpart contention resolution unit for controlling the exchange counterpart, an optical/electrical conversion unit, a serial/parallel conversion unit, and a packet eliminating unit. The exchange counterpart contention resolution unit controls the packet eliminating unit to eliminate a dummy packet.

Abstract: An apparatus for enabling transmission of parallel data from a first parallel bus to a second parallel bus via a serial data channel includes a first logic element that generates a synchronization character used in a serial data transmission protocol upon detection of a parallel synchronization packet. A serializer converts data from the first logic element into a serial data stream. A de-serializer converts the serial data stream into a plurality of parallel data packets. A second logic element detects the synchronization character and converts the synchronization character into a parallel synchronization packet.

Abstract: To provide a video signal transmission apparatus capable of correctly transmitting a digital video signal. A PLL circuit 5 has a first cutoff frequency lower than the frequency of a horizontal synchronization signal contained in a digital video signal S9. has the characteristics of causing attenuation of a signal of the frequency higher than the first cutoff frequency, performs PLL processing for a dot clock signal S14 for identifying one pixel's worth of data of the digital video signal S9, and generates a transmission clock signal 55 of the frequency N (integer of 2 or more) times the first dot clock signal S14. The PLLL circuit 6 has a second cutoff frequency higher than the frequency of the horizontal synchronization signal, tracks a signal of a frequency lower than the related second cutoff frequency, performs the PLL processing on the serial signal S2 input via the transmission cable 4, and generates a transmission clock signal S6.

Abstract: A multiplexer circuit, converting parallel data into serial data and synchronized with a clock signal, has a plurality of multiplexer cells that receive the parallel data. Each of the multiplexer cells has a first load, a plurality of first conductivity type transistors, and a level-changing circuit. The first conductivity type transistors are connected in series between a first power source line and a second power source line, and the level-changing circuit changes a connection node of adjacent first conductivity type transistors to a level of the first power source line.

Abstract: The present invention increases the communication path switching control speed. A demultiplexing circuit 2a is provided at an input side of a time division switch 1 and converts a serial signal of an input high 20a of multiplexed 32 Kbps sub rate channels into serial signals of the input highway 21a and 22a of multiplexed 64 Kbps full rate channels. A multiplexing circuit 2b is provided at an output side of the time division switch and converts serial signals of the output highways 21b and 22b of multiplexed 64 Kbps full rate channels into a serial signal of the output highway 20b of multiplexed 32 Kbps sub rate channels.

Abstract: An apparatus comprising a first circuit, a deserializer circuit and a framer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may comprise (a) a parallel register bank configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals and (b) a state machine configured to generate the one or more select signals in response to one or more control signals. The framer circuit may be configured to generate the one or more control signals in response to (i) one or more input control signals and (ii) the output signal.

Abstract: A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit.

Abstract: Frame-oriented serial data, such as PCM data, are switched. Switching information is generated with the aid of a switching algorithm. The switching information is referred bit by bit to the data and it includes addresses of output lines of an interface of the apparatus. Because of the bit by bit switching, data from channels with a largely arbitrary bandwidth can be switched without passing multiple times through the switching apparatus. A bypass data path renders it readily possible to switch the last bit of an arriving PCM frame to the first bit of the next PCM frame. Thus each arbitrary bit of an input frame can be switched with a fixed delay of one PCM frame. The apparatus is advantageously embodied as an applications-specific circuit.

Abstract: The invention is a receiver and a method of receiving data having a preferred application in a satellite. A receiver in accordance with the invention includes at least one memory (118, 120), each memory including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal and outputs the stored data samples from a plurality of channels in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and an outer decoder (102), responsive to data blocks with each data block containing at least one data group, which decodes the data blocks and outputs decoded data blocks.

Abstract: The invention relates to a method, a device and software for digital inverse multiplexing digital data, wherein a packet of digital data is split into:

Abstract: A data transmission system efficiently transmits data of high quality by accurately restoring the sequence of the transmitted data at a receiving circuit. The data transmission system includes a periodic data generating unit for generating periodic data, a parallel/serial converting unit for multiplexing parallel transmission data and the periodic data and converting multiplexed data into serial data, a serial data sending unit for sending the serial data, a serial data receiving unit for receiving the serial data, a serial/parallel converting unit for converting the serial data into parallel data, a periodic data string detecting unit for detecting a periodic data string from strings of the parallel data, and a transmission data restoring unit for restoring the transmission data based on the detected periodic data string.

Abstract: A circuit for detecting whether an intermittent clock waveform signal of 50 MHz is received or not includes an offset receiver, a charge pump, a capacitor and a hysteresis comparator. A circuit for detecting whether a random data waveform signal of 500 MHz is received or not includes an offset-less receiver, a transition counter, a delay circuit and an AND circuit. An OR circuit outputs as a signal detection signal a signal indicating the OR operation result of respective outputs of the hysteresis comparator and the AND circuit.

Abstract: In a multiplexer, flip-flops for timing control are interposed between a control signal generating circuit and a four-to-one selector, and a flip-flop is interposed between a quarter divider and flip-flops provided for data input. A sum of delay times of the quarter divider and the control signal generating circuit and a setup time of the flip-flops for timing control is merely required to fall within one clock cycle, and therefore an operation speed can be high.

Abstract: A serial communication circuit sends or receives a large amount of data speedily. A buffer 2a is connected to a serial interface circuit 1a, and a buffer 2b is connected to a serial interface circuit 1b. One end of a switch 4 is connected to the serial interface circuit 1a or the serial interface circuit 1b, and another end to a serial port 3. Switching the switch 4 sequentially to the serial interface circuit 1a and to the serial interface circuit 1b makes it possible to use the two buffers for sending data to, or receiving data from, one serial port 3.

Abstract: An optical packet exchange apparatus and an optical switch in which search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit devoid of a packet to be received is reduced to enable fast switch control even in cases wherein the number of channels of the exchange apparatus is increased or network speed is higher. A plurality of input units, a plurality of output units and an optical switch are provided. Each input unit includes an input buffer unit, a parallel/serial conversion unit, an electrical/optical conversion unit, and a dummy packet insertion unit for sending a dummy packet if there is no packet to be transmitted. Each output unit includes an exchange counterpart contention resolution unit for controlling the exchange counterpart, an optical/electrical conversion unit, a serial/parallel conversion unit, and a packet eliminating unit. The exchange counterpart contention resolution unit controls the packet eliminating unit to eliminate a dummy packet.

Abstract: Different frames received on a first port are processed by different processing channels in parallel. The processed frames are transmitted to a second port in the same order in which they were received on the first port. The ordering is maintained using a FIFO that receives the number of a processing channel whenever a frame is dispatched to the processing channel. The processing channels are selected to provide frames to the second port in the order of the channel numbers in the ordering FIFO.

Abstract: A serial/parallel converter 101 converts a single stream of transmit data to a plurality of streams of transmit data, outputs first-stream transmit data and fourth-stream transmit data to error correction coding sections 102 and 103, respectively, and outputs second-stream transmit data and third-stream transmit data to an IFFT section 106. The IFFT section 106 generates an OFDM signal using the second-stream transmit data and third-stream transmit data, together with first-stream and fourth-stream transmit data that has undergone error correction coding processing. A peak detector 107 detects peak power of the generated OFDM signal. If the detected peak power exceeds a threshold value, the IFFT section 106 re-generates an OFDM signal using a peak suppression signal from a peak suppression signal generator 108 instead of first-stream and fourth-stream transmit data.

Abstract: The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A matrix switch comprises a matrix switch main body (2), a preprocessing block (1) provided on an input side of the matrix switch main body (2), and a postprocessing block (3) provided on an output side of the matrix switch main body (2), wherein each of the preprocessing block (1), the matrix switch main body (2) and the postprocessing block (3) comprises a circuit, which parallel-converts a line input with each setting bit width, performs a bit stream operation in the setting bit width, serially converts it, and performs line output, respectively, and the matrix switch main body (2) is divided into the setting bit width parallel-converted with the preprocessing block (1) and switching-control is performed.

Abstract: A transmission interface compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals are single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals are also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus.

Abstract: Packets are accumulated in a packet transmission memory, and the data bits stored in each packets are serially output from the packet transmission memory, wherein an internal bit address signal is sequentially changed in the packet transmission memory so as to store the serial data bits in an addressable data storage region without any serial-to-parallel data conversion, and the data bits are serially output from a built-in parallel-to-serial data converter connected to the data storage regions, thereby making the circuit arrangement simple.

Abstract: A highly flexible and scalable architecture implements TDM bridge and related functions for network to telecom interface applications like voice over Internet. A very small packet size minimizes packetization delay so that VOIP can be realized without expensive echo cancellation. High density enables processing 4K simultaneous voice channels in real time on a single, compact circuit board.

Abstract: The invention provides a single-chip method. The method includes a memory shared among packet buffers for receiving packets, packet buffers for transmitting packets, and packet header buffers for packet forwarding lookup. Accesses to that shared memory are multiplexed and prioritized. Packet reception is performed with relatively high priority, packet transmission is performed with medium priority, and packet forwarding lookup is performed with relatively low priority. The single-chip method includes circuits for serially receiving packet header information, converting that information into a parallel format for transmission to an SRAM for lookup, and queuing input packets for later forwarding at an output port. Similarly, the single-chip method includes circuits for queuing output packets for transmission at an output port, receiving packet forwarding information from the SRAM in a parallel format, and converting packet header information from output packets into a serial format for transmission.

Abstract: A data processor 1 converts serial data in an STM-16 to parallel data that is based on eight bytes (64 bits) . A transparent information detector 10 detects the position of the data (transparent data) as a candidate for transparent processing in the parallel data and transparent processors 30a through 30e serially connected in five stages converts the transparent data and rearranges the processed data based on the detected information. Thus, the data processor 1 can perform transparent processing easily via a relatively low-speed general-purpose device, by converting high-speed serial data in the STM-16 to every 8-byte parallel data for further processing.

Abstract: The present invention relates to a method of assigning data from time slots on an input bus to time slots on an output bus comprised of determining the order of time slots of data in a frame, determining whether each time slot of data in an input frame is to be located in the same or later time slot in an output frame, or whether it is to be located in an earlier time slot in an output frame, in the event each time slot of data of the input frame is to be located in the same or later time slot in an output frame, applying each time slot of data of the input frame to the same or a later time slot in the output frame, in the event a time slot of data of the input frame is to be located in an earlier time slot in an output frame, delaying for one time slot internal and then applying each time slot of data of the input frame to the same or a later time slot in the output frame, whereby the order of time slots in a stream of output data is always from an earlier time slot to a later time slot.

Abstract: In order to enable high speed, high bandwidth data transfer between two ASIC devices, for example in a backplane, a wide parallel input data word is divided into a smaller number of words, and each smaller word is converted to serial form and then transmitted over a respective sub-link at a high clock rate relative to the system clock. At the receiving side, the clock is recovered from the serial words, and the serial words are converted back to parallel form. An alignment process is then carried out, firstly involving detecting the positions of the bits of the words and then storing the words in a buffer FIFO register. The words are clocked out of the FIFO register in synchronism under control of the system clock once it is detected that valid words are received in the FIFO registers.

Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.

Abstract: Systems and methods for time division multiplexing are described. A time division multiplexer-demultiplexer system includes I) a signal transmitting system for transmittal of a serialized signal including A) latency free continuous data and B) at least one member selected from the group consisting of bursty data and packetized data, the signal transmitting system including a multiplexer and a timing control block; and II) a signal receiving system for reception of the signal without disrupting the laminarity of the latency free continuous data, the signal receiving system including a demultiplexer and a sequence detector. The systems and methods provide advantages in that continuous data can be simultaneously transmitted with bursty data and/or packetized data on the same tie line without disrupting the laminarity of the continuous data.

Abstract: Receive and transmit blocks for asynchronous transfer mode (ATM) cell delineation are disclosed. The receive block has a plurality of cell delineation blocks, a memory controller, a memory and a bus controller. The transmit block has a bus controller, a plurality of queue selection devices, a plurality of memory queues and a plurality of cell delineation blocks. According to one implementation, the bus controllers receive address mode/select signals and operate to respond to one of a plurality of subsets of port addresses on the ATM physical layer responsive to the address mode/select signals.

Abstract: An apparatus and method for enabling the combination of multiple streams of data cells into a single thread. By enabling plural input ports of an intermediate device to access a single parallel output port of the device, plural network switch elements share a single thread through a switch fabric. For instance, the method and apparatus permit interleaving the relatively low bandwidth cell outputs of two ATM network switch central control processors onto a single thread routed through an interconnected switch fabric. Certain of these cells are received from the switch fabric at a parallel input of the intermediate device, then routed to one of plural serial output ports. Pacing of cells provided to the plural serial input ports prevents exceeding the shared thread bandwidth.

Abstract: The present invention is directed to an apparatus and method for efficiently transferring asynchronous transfer mode (ATM) cells across a backplane in a network switch. The present invention is realized through an electrical apparatus that converts parallel data that is received on parallel data input ports to serial data that is transmitted on serial data output ports. The parallel data that is received on each parallel data input port is divided and transmitted from a corresponding pair of serial data output ports. The electrical apparatus also converts serial data that is received on serial data input ports to parallel data that is transmitted on parallel data output ports. The serial data that is received on a corresponding pair of serial data input ports is combined and transmitted from a parallel data output port.

Abstract: A plurality of transmitters are multiplexed to a hub through clocked serial links. Timing problems that may arise when switching between links are eliminated with a system including a group serial receiver for each link for performing serial to parallel conversion of data sent over the serial link, outputing a group clock signal based on the serial clock signal, outputing parallel data clocked by the group clock signal, and determining a data enable signal from the serial link. A select signal for determining the serial link being read by the hub selects the corresponding group clock, parallel data, and data enable. A load control clocks the selected parallel data into a first-in, first-out buffer using the selected group clock when the selected data enable is asserted. When the selected data enable is not asserted, the load control is held in reset and, hence, is insensitive to irregularities in the selected clock signal due to switching between links. Data is clocked from the buffer by a local clock.

Abstract: This invention relates to a cross connection element which comprises at least one input, output and branching means for forwarding through predetermined outputs at least some signal components of a first serial data signal received through the input. To provide such a cross connection element that considerably facilitates the management of the data transmission network, the branching means comprise means for transparently forwarding single signal components of a serial data signal received through said input, as serial data signals through the output indicated by the routing data stored in the memory means of the cross connection element. In addition, the cross connection element comprises at least one output for transparently forwarding a single signal component of a first serial data signal indicated by the routing data stored in the memory means.

Abstract: A computer system employs a hierarchical ring structure for communication. Computer system elements are configured into modules with ring interface hardware, and the modules are coupled to one or more rings. Bridge modules may be included for transmitting between rings in the hierarchy. The rings are time division multiplexed, and each time slot on a ring carries a frame. According to an address carried within the frame, bridge modules determine whether or not to transmit a frame circulating on a source ring onto a target ring. If the address of the frame indicates a module upon the source ring, the bridge module retransmits the frame on the source ring. Otherwise, the bridge module transmits the frame on the target ring. The bridge module operates in this fashion at any level of the hierarchy. The owner of a time slot on a ring is permitted to release the time slot for use by other modules. To reclaim a time slot, the owner marks the time slot owned.

Abstract: A method and apparatus for accessing data of a telecommunications interface control RAM to meet the two different requirements of the two types of devices accessing the control RAM. Data for output ports are typically aligned such that time-slot 0 for each port leaves the network at the same time. The hardware therefore requests that the control RAM be organized such that the first N locations correspond to time-slot 0 of all output ports, the next N locations to time-slot 1 of all ports, and so on with the final N locations corresponding to the last time-slot of all ports. The software addressing under processor control, on the other hand, uses data structure groups which are a function of the communication ports.

Abstract: A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit.

Abstract: An asynchronous transfer mode switching system including a core switch section (CS102) in an output buffer-type configuration which has an ATM switching function between high-rate input and output ports, an input buffer module section (IXB20) which multiplexes plural low-rate input line to the high-rate input port of the core switch section, and an output buffer module section (OXB30) which separates the output of a high-rate output port of the CS into plural low-rate output lines. The IBX enables queuing for each output line and each service class. The OXB enables queuing for output line and service class accommodated by itself. When the buffer occupancy exceeds a threshold value, the OXB originates a cell inhibiting signal to the CS. When the queue length for each output port exceeds a threshold value, the CS originates the cell inhibiting signal to all IXBs. The IXB controls to stop a cell transmission according to the cell inhibiting signal.

Abstract: An apparatus and a method are provided for switching an information signal from a selected input to a selected output of a telecommunications switch. The method includes the steps of digitally sampling the information signal at the selected input of the telecommunication switch and writing the sampled information signal into a predetermined location of a data frame within a circulating data loop at a first station of the circulating data loop. The method further includes the steps of capturing the sampled information signal at a second station of the circulating data loop and transferring the captured information signal to the selected output of the telecommunications switch.

Abstract: A plurality of transmitters are multiplexed to a hub through clocked serial links. Timing problems that may arise when switching between links are eliminated with a system including a group serial receiver for each link for performing serial to parallel conversion of data sent over the serial link, outputing a group clock signal based on the serial clock signal, outputing parallel data clocked by the group clock signal, and determining a data enable signal from the serial link. A select signal for determining the serial link being read by the hub selects the corresponding group clock, parallel data, and data enable. A load control clocks the selected parallel data into a first-in, first-out buffer using the selected group clock when the selected data enable is asserted. When the selected data enable is not asserted, the load control is held in reset and, hence, is insensitive to irregularities in the selected clock signal due to switching between links. Data is clocked from the buffer by a local clock.

Abstract: A data bus controller is provided. The data bus controller comprises an ingress interface that receives single data streams of encoded data. A multiplexer is connected to the ingress interface and combines the single data streams into a broadcast data stream of encoded data. An egress interface connected to the multiplexer transmits the broadcast data stream. An arbiter is connected to the multiplexer. The arbiter generates control data for controlling the multiplexing of the single data streams and transmits control data to the multiplexer.

Abstract: A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Abstract: A data transmission system etc. which can transmit and receive a signal of a serial data interface (SDI) system and a signal of a serial digital data interface (SDDI) system mixed on the same transmission path. A serial to parallel conversion circuit receives a transmission signal and converts the same to a reception signal of a 10-bit parallel format. A packet classification data detection circuit detects the transmission packet from the reception signal and detects the content of the positions of separation codes SAV and EAV of the transmission packet. An FIFO performs buffering so that the beginning of the transmission packet will not be cut off. A selector circuit separates the SDI data and the SDDI data under the control of a control circuit in accordance with the contents of the SAV and EAV of the transmission packet and outputs the same.

Abstract: In a multipoint video conference controlling system which is supplied with video packets and audio packets from conference terminals, multiplexes the video packets to produce a composite video packet, and mixes the audio packets to produce a mixed audio packet, a sequence number collating device collates the sequence numbers of the video packets and the audio packets to produce a coincidence signal when the sequence numbers of the video packets and the audio packets coincide with each other. Video and audio transmitting devices transmit synchronously the composite video packet and the mixed audio packet in response to the coincidence signal. The multipoint video conference controlling system may comprise video and audio sequence number processing devices which add one of sequence numbers to the composite packet and the mixed audio packet when the video packets and the audio packets have the sequence numbers.

Abstract: A method for interfacing a media independent interface with a DVB compliant modulator includes the step of receiving nibbles of data from a media independent interface in accordance with a transmit clock signal and a holdoff signal during assertion of a transmit enable signal, wherein the nibbles of data are a portion of a variable sized packet. The nibbles of data are stored into a first buffer. The transmit clock signal is disabled. The nibbles of data are shifted out of the first buffer in accordance with a serial clock signal to provide a first bitstream. The first bitstream is framed into a predetermined packet size. The holdoff signal is asserted to halt the first bitstream. A synchronization indicator is serially inserted into the first bitstream in accordance with the serial clock signal to form a second bitstream. The second bitstream is parallelized to form parallelized data.

Abstract: A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link. The serial-to-parallel converters are staggered length shift registers. The output side of the switching matrix can be similarly configured.

Abstract: There is provided a switching system that includes a plurality of input lines for transmitting time division multiplexed data signals, and a conversion means for receiving and converting the respective data signals into a non-time division multiplexed, parallel format, group of N data signals. The system also includes a crosspoint switch having a group of N/K outputs, a first group of N inputs connected to the respective outputs of the conversion means, and a second group of N/K select or control inputs. In addition, a control means includes connection memory that constitutes a means for addressing the crosspoint switch at the select inputs, and the outputs of a group of N/K multiplexers are connected to the select inputs and the inputs of the group of N/K multiplexers are connected to the control means.

Abstract: A multi-media-access-controller (henceforth "multi-MAC") in accordance with this invention includes a plurality of transmit data path circuits and a plurality of receive data path circuits that respectively transmit and receive data serially on a corresponding plurality of network buses, a single transmit data path controller and a single receive data path controller that monitor status of and control operation of the respective transmit and receive data path circuits. Use of only two data path controllers eliminates the plurality of MACs used in prior art devices and therefore results in significant savings in die area. Use of a single CRC calculator also results in savings in die area.

Abstract: A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes is the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to the parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations.

Abstract: A demultiplexer (10) includes an input stage (12) that receives a serial data stream having a plurality of m-bit sections at a first clock rate. The input stage converts successive n-bit portions of each m-bit section into a first n-bit parallel output at a second clock rate. An intermediary stage (14) receives the first n-bit parallel output and generates a second n-bit parallel output at the second clock rate. The first n-bit parallel output corresponds to a different portion of an m-bit section than the second n-bit parallel output. An output stage (16) receives the first n-bit parallel output from the input stage (12) and the second n-bit parallel output from the intermediary stage (14). The output stage (10) places the first n-bit parallel output onto an output bus (36) having a width of m-bitlines at an earlier instance in time than the placement of the second n-bit parallel output.