Abstract: A method and system including apparatus for detecting and blocking an invalid request to a target wherein fiber channels interconnect the data processing configuration. A request made from a hub such as a fabric switch to an internal fiber channel arbitrated loop is blocked by substituting IDLE characters for the frames of data included with the request. The substitution of IDLE signals can also occur within an internal fiber channel arbitrated loop system where access is blocked to a confidential data storage system. If the request is legitimate, the data frames are passed to the target and the requested data is transmitted back to the requester. If the request is refused as being an unauthorized request, the data frames are replaced with IDLE characters and no transfer of confidential data occurs.

Abstract: A switch for a network. The switch comprises a memory mechanism in which portions of packets are stored. The switch comprises a mechanism for instituting changes to the memory mechanism while the memory mechanism continuously operating on packets. A method for switching packets. The method comprises the steps of receiving changes for a memory mechanism of a switch at a buffer of the switch. Then there is the step of implementing the changes to the memory mechanism when the memory mechanism receives an implementation signal while the memory mechanism continuously operates on packets.

Abstract: In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.

Abstract: A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

Abstract: The present invention includes a design for a 20-gigabit per second two to one multiplexor, that uses: first and second input amplifiers that respectively provide output signals by respectively receiving and amplifying first and second ten-gigabit per second input signals; first and second power dividers that each produce two output data streams by respectively splitting the output signals of the first and second input amplifiers; first and second mixers that produce output signals by respectively mixing output signals of the first and second power dividers with a 10 GHz local oscillator signal; a second means for combining signals that produces an output signal by combining the output signal of the second mixer with an output data stream of the second power divider; a T/2 delay line that produces an output signal by delaying the output signal of the second combining means; and an output combiner means that outputs a 20-gigabit per second data stream by combining the output signal of the T/2 delay line with t

Abstract: Network data is received in a first format. The data is converted to a synchronous optical network (SONET) format. Switching functions are performed on the SONET formatted data. The SONET formatted data is converted to a second format. In one embodiment, the switching functions on the SONET formatted data contains performing time switching and space switching.

Abstract: A highly flexible and scalable architecture implements TDM bridge and related functions for network to telecom interface applications like voice over Internet. A very small packet size minimizes packetization delay so that VOIP can be realized without expensive echo cancellation. High density enables processing 4K simultaneous voice channels in real time on a single, compact circuit board.

Abstract: According to one embodiment, an integrated circuit (100) includes a programmable portion (102) and a communication portion (104). A programmable portion (102) may include logic circuits that are configurable by a user. A communication portion (104) may include one or more circuit blocks designed to perform predetermined serial data communication functions. According to one embodiment, a communication portion (104) may include a block converter (218) that can encode/decode input data words into output data words, and a scrambler circuit (220) for scrambling/de-scrambling data according to a predetermined scrambling polynomial value. Different scrambling polynomial values may be selected from an operation control store (206) to provide a variety of different scrambling/de-scrambling functions.

Abstract: Converters and a corresponding method for converting serial data to parallel format and vice versa, particularly for use in switches for telecommunications applications. The converters comprise a storage element associated with each serial channel and comprising two arrays of storage elements. At any one time, the storage elements are accessed sequentially while those of the other array are accessed in parallel. A data bus, divided into portions by buffers, connects the by buffers, connects the serial channel to all storage cells in an associated storage element. For serial to parallel conversion, the buffers latch data from one bus portion to the next in accordance with a write cycle during which one storage element is written. Writing commences from the bus portion furthest from the incoming serial channel and storage elements on either side of a buffer are written simultaneously. The resulting delay between writing arrays words allows checking of the data such as synchronization.

Abstract: A LAN interface using an Ethernet protocol is disclosed. The interface includes an Ethernet controller, which performs a control operation for LAN interfacing, a codec, which codes and decodes transmission/reception data, and a transceiver, which detects LAN collisions while data is being transmitted/received. It further includes a retransmission control circuit, which is coupled between the Ethernet controller and the codec and outputs the n-th data in accordance with a back-off algorithm after delaying a certain time when the n?1 data collisions occur on the same frame.

Abstract: An integrated circuit comprising a plurality of link layer controllers. The plurality of link layer controllers may be configured to operate independently in a first mode and cooperatively in a second mode.

Abstract: A multiplexer circuit converts parallel data into serial data synchronized with an internal clock signal, and the multiplexer circuit has a logic circuit, a load circuit, and a plurality of switching elements. The logic circuit processes the internal clock signal and the parallel data. The load circuit and the plurality of switching elements are connected in series between a first power source line and a second power source line. Each of the switching elements is controlled in accordance with an output of the logic circuit.

Abstract: An optical packet exchange apparatus and an optical switch in which search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit devoid of a packet to be received is reduced to enable fast switch control even in cases wherein the number of channels of the exchange apparatus is increased or network speed is higher. A plurality of input units, a plurality of output units and an optical switch are provided. Each input unit includes an input buffer unit, a parallel/serial conversion unit, an electrical/optical conversion unit, and a dummy packet insertion unit for sending a dummy packet if there is no packet to be transmitted. Each output unit includes an exchange counterpart contention resolution unit for controlling the exchange counterpart, an optical/electrical conversion unit, a serial/parallel conversion unit, and a packet eliminating unit. The exchange counterpart contention resolution unit controls the packet eliminating unit to eliminate a dummy packet.

Abstract: A method for communicating data is provided that includes communicating a first set of data from a first channel to a first serial-to-parallel converter and communicating a second set of data from a second channel to a second serial-to-parallel converter, the data sets are then converted to a parallel format. The converters are monitored to determine when one or more words of the respective data sets have accumulated in each of the converters. One or more of the words that have accumulated in each of the converters are then written to a selected one of first and second memory banks. A single scheduler monitors the memory banks to determine when the words that were written to each of the memory banks have formed one or more cells such that they may be read out of a selected one of the memory banks to be communicated to an output communications link.

Abstract: A network switch having an internet port interface controller, includes a high performance interface for communicating with other switches and components through the transfer of data packets contained in memory. The high performance interface includes a data connection bus, where data is transferred on both a rising edge and a falling edge of a clock signal, and the data connection bus has output drivers and a multiplexing circuit connected to the output drivers. The multiplexing circuit is constructed through two levels of glitchless multiplexors, to serialize said data transmitted over said high performance interface. Because two levels of glitchless multiplexors are employed, function hazards that occur in the glitchless multiplexors when more than one input thereto change simultaneously can be masked, and do not create noise that can be propagated to an output driver.

Abstract: A built-in self test system for testing a clock and data recovery circuit. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Abstract: A communication system includes a link module having a first serial interface for interfacing to a serial link. The link module also including a second serial interface. The system also includes a Media Access Control (MAC) module including a parallel interface. The system also includes a converter module, coupled between the parallel interface and the second serial interface, configured to convert symbols, transferred between the parallel interface and the second serial interface, between a parallel format at the parallel interface and a serial format at the serial interface.

Abstract: The present disclosure relates to an apparatus for use with a probe station in the testing of semiconductor wafers. In one embodiment, an apparatus for testing semiconductor devices includes a first plate and a second plate. The first plate is configured to be mounted to and completely removable from the head stage of a probe station. The second plate is configured to be removably coupled to the first plate and has a major aperture for receiving a probe-card assembly. Docking equipment desirably is mounted to a major surface of the second plate to facilitate docking of a tester to the probe station.

Abstract: A scheme is described for distributing data operations on an irregular data stream over multiple stages of a data aligner to generate a regular data stream having continuous filled byte positions. In one particular embodiment, the number of unaligned data scenarios may be reduced through the use of data stream element mapping. A complex data stream may be mapped onto a simple data stream with only the addition of multiplexers and simple logic to the data aligner. The implementation in network protocol related hardware, where a data stream is encoded and decoded for error detection and correction, may lead to a faster and more efficient pipelined design of checkers and generators, thereby, making them more desirable for higher frequency and higher bandwidth designs.

Abstract: A latch device is provided having a latch mode and a transparent mode. In the latch mode, the latch device synchronizes a data signal to a clock signal. In the transparent mode, the data signal drives the output without clock synchronization, such that the clock input signal is unused. The latch device can be employed in an optical driver for optical network laser diodes.

Abstract: A digital switching system capable of changing switching capacity without any recourse of increasing or decreasing the quantities of line terminals or cross-point switches. The digital switching system comprises line terminals which send and receive data as serial data to and from the user, a switching arrangement which switches, based on destination information, the parallel data converted from the serial data, and data converters capable of converting between the serial data and the parallel data at a specified conversion ratio. The serial/parallel converter circuit of a serial/parallel converter in a digital switching system comprises a 1:4 transceiver, four variable converters, and 16 selector circuits The 1:4 transceiver converts serial data into 4-bit wide parallel data and sends the parallel data to the variable converters. If mode selection information specifies a conversion ratio of 1:4, only a tristate buffer is enabled and 4-bit wide parallel data is output.

Abstract: This invention adds one extra bit which can be viewed as a shadow of most significant bit of the serial register. This extra register bit is referred as buffer_flop. When the receive data is coming in, the data bits keep shifting into the serial register of the serializer block bit by bit. The first bits enters into the most significant bit of the serial register and is shifted towards the least significant bit of the serial register. When a whole block of bits (32 bits) are received, the serializer is full and is read into the VBUS clock domain. The first bit of next block of bits is stored in the buffer flop. The second bit is stored in the most significant bit of the serializer and the buffer flop bit is copied into the second most significant bit of the serializer. Subsequent bits are received and right shifted by one.

Abstract: A secure communication circuit for use with a data communication interconnect adapter and method of operation thereof. The secure communication circuit includes a first data buffer coupled to a data input terminal, an encoder/decoder coupled to the first data buffer, a second data buffer coupled to the encoder/decoder and a switching device coupled to a data output terminal. The switching device is couplable to either the first or second data buffers. A controller, coupled to the (switching device, selectively connects the switching device to the first or second data buffers. In a related embodiment, the secure communication circuit further includes a first serializer/deserializer (SERDES) coupled to the data input and a second SERDES coupled to the switching device.

Abstract: The present invention relates to a method of assigning data from time slots on an input bus to time slots on an output bus comprised of determining the order of time slots of data in a frame, determining whether each time slot of data in an input frame is to be located in the same or later time slot in an output frame, or whether it is to be located in an earlier time slot in an output frame, in the event each time slot of data of the input frame is to be located in the same or later time slot in an output frame, applying each time slot of data of the input frame to the same or a later time slot in the output frame, the event a time slot of data of the input frame is to be located in an earlier time slot in an output frame, delaying for one time slot interval and then applying each time slot fo data of the input frame to the same or a later time slot in the output frame, whereby the order of time slots in a stream of output data is always from an earlier time slot to a later time slot.

Abstract: A device and a method for equalizing data delays in a multiplicity of serial input data streams switched by a switching network in a telecommunication switching system, wherein the multiplicity of data word synchronization units are used for synchronizing a multiplicity of input data streams at a data word level into a multiplicity of synchronized parallel input data streams.

Abstract: A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A transponder may include a transmitter and a receiver. A serializer may include (i) a serdes framer interface (SFI) circuit for receiving data channels and a reference channel from a framer and realigning the data channels, (ii) a clock multiplier unit (CMU) for receiving a clock frequency and translating the clock frequency to a higher-clock frequency, (iii) a multiplexing circuit for merging data channels into one data channel, (iv) an output driver stage, (v) a reference selection circuit for selecting a reference clock, filtering the reference clock, and providing to the CMU one of the selected reference clock or a filtered reference clock.

Abstract: A serial bus communication system for communication across the backplane of a node includes a control unit having a serial bus controller operable to convert between parallel signals and serialized signals. A plurality of service units each include a serial bus terminator. A serial bus includes a discrete serial channel for each service unit. The serial channel connects the serial bus terminator to the serial bus controller. The serial bus controller is operable to direct a message for a service unit on the serial bus to only the serial channel of the service unit.

Abstract: There is disclosed, for use in a communication device, such as an access concentrator, that performs high-speed data transfers between a group of M data drivers and a group of N data receivers, a space and time division multiplexing (STDM) bus interface in which each bus line is a single source/multidrop line that connects the output of only one driver to multiple receivers (i.e., a 1:N configuration). The disclosed invention minimizes the number of data reflections on each bus line by eliminating all but one of the stubs associated with the bus drivers. The disclosed device also eliminates a single point or failure situation. The bus interface also provides additional robustness by means of a “back-up” bus line that is coupled to alternate outputs on all data drivers and to inputs on all receivers (i.e., multisource/multidrop or M:N configuration).

Abstract: Clock provisioning techniques that may save chipset space, power, and manufacturing expense.

Abstract: A bit line selector switch is serially connected with a data sink for detecting high speed data transmissions, typically in the gigabit-per-second range, and a backplane having a plurality of data lines. The selector switch incorporates a selector circuit that operates in one of two modes, a first “selected”, or ON, mode and a second “not selected”, or OFF, mode. The selector circuit includes one, preferably differential, input. In one embodiment, a selector switch has a plurality of selector circuits thus allowing the switch to operate in both modes simultaneously. Data coupled to a differential input of the selector circuit will, when operating in the “selected” or ON mode, transmit the data to the data sink which be, for example, a memory device, processor, or the like. In the “not selected” or OFF mode, the selector circuit will pass any data received to a positive supply rail.

Abstract: A communication node to be implemented within an optical fiber communication system is described that consists of a number of individual cards inserted within a node shelf. Each card is a transponder that comprises a Short-Range (SR) transceiver, a Dense Wavelength Division Multiplexed (DWDM) transceiver, and a local switch coupled to both transceivers. The local switches of the cards are coupled together and each selectively couple the transceivers within their respective cards to the local switches of other cards so that the transceivers can be further coupled to transceivers of other cards. This allows failure and congestion protection systems to be implemented within the node while not requiring the use of a central cross-connect switch.

Abstract: A multiplexer circuit converts parallel data into serial data synchronized with an internal clock signal, and the multiplexer circuit has a logic circuit, a load circuit, and a plurality of switching elements. The logic circuit processes the internal clock signal and the parallel data. The load circuit and the plurality of switching elements are connected in series between a first power source line and a second power source line. Each of the switching elements is controlled in accordance with an output of the logic circuit.

Abstract: A method and apparatus of communicating data packets across the midplane of an electronic system in which the packets are partitioned into segments of a predetermined size and then serialized to a predetermined width. The serialized packets are transmitted, in phase staggered segments, across the midplane on a respective channel, received into receiving end and the serialized segments that have traversed the midplane, are deserialized and reassembled into the original data packet.

Abstract: A system of expanding addressing in an addressing constrained environment. A bus that defines a limited number of addresses couples together a master and a plurality of slaves. When each slave has multiple possible target ports, a maximum granularity provided by the addressing may be exceeded. By using a portion of a transmission header as an internal address, the maximum addressing may be expanded to greater granularity. The internal address is then translated in the slave to recover the external address in the header.

Abstract: A serial link circuit includes a transmitter which multiplexes the circuit's input signals together and uses a single processing circuit to generate a multiplexed output to be transmitted. The multiplexing is done with a limited voltage swing prior to preamplification. In this way, clock loading (and hence clock buffer area), power and jitter are significantly reduced. The complementary link receiver includes a demultiplexer implemented with sense amplifiers that are digitally unbalanced using trimmer capacitors to cancel the receiver's offset voltage. This allows the receiver to be implemented using very small elements to save power, and enables the link to operate reliably with a very low signal swing.

Abstract: A synchronous signal/active signal restoring apparatus and method are disclosed in which a display device receives a digital image signal transmitted in an optical signal form from a source device through an optical cable, a physical medium which can not transmit a clock signal, and restores a horizontal/vertical synchronous signal and a horizontal/vertical active signal.

Abstract: Systems and methods for efficiently conveying one or more communication channels over a transmission medium. Communication is effected by transforming an incoming digital bit stream into a Hermite-Gaussian information stream that includes a plurality of Hermite-Gaussian packets. This transformation is accomplished through the use of a plurality of Hermite-Gaussian basis functions. The Hermite-Gaussian information stream is then transmitted over the transmission medium. More particularly, digital bit streams carried on one or more incoming channels may be in the form of binary “on” and “off” bits. These digital bits are converted into a plurality of Hermite-Gaussian waveform components which together comprise a Hermite-Gaussian packet. The conversion process maps each of respective incoming digital bits to a corresponding one of a group of Hermite-Gaussian functions.

Abstract: A signal transmission system has a master node and plural slave nodes performing data transmission with the master node. The master node has a serial-to-parallel converter for converting a serial data signal from each slave node into a parallel data signal. Each slave node has a transmission aligner for performing word alignment processing upon a parallel data signals, and a parallel-to-serial converter for converting the parallel data signal subjected to the word alignment processing by the transmission aligner into a serial data signal, and outputting the serial data signal to the master node.

Abstract: A supervisory parallel switching device is designed for use with a CIM system including a host computer unit connected via an extended computer integrated unit to at least one equipment unit through an SECS-compliant (Semiconductor Equipment Communication Standard) serial communication link, for the purpose of allowing the equipment unit to be continuously under computer control even in the event of an unanticipated shutdown to the extended computer integrated unit.

Abstract: A solution to the word alignment problem in a Serializer Deserializer (SERDES)/Media Access Controller environment is to have for each SERDES lane: a recovered clock, a Write Pointer counter and a FIFO. Misaligned words are simply stored in their FIFO's according to the respective recovered clocks and straightforward increments of the various Write Pointers WP_i. One of the lanes is selected as a reference, and the contents of the other FIFO's are inspected to determine the nature of their misalignment, if any. Then the values from the Read Pointer counters RP_i are individually offset by corresponding amounts to compensate for the misalignment, so that when data is read it is indeed aligned. These offsets by corresponding amounts are simply individual per lane adjustments to the various Read Pointers, and cooperate with the adjustments to those Read Pointer for rate matching.

Abstract: A system and method for the efficient transmission of information in a code division multiple access (CDMA) wireless telecommunication system. The rate of reliable transmission is increased by implementing an orthogonal frequency-division multiplexing (OFDM) scheme in, for example, a direct-spread CDMA network, resulting in a multi-carrier CDMA (MC-CDMA) system. Information (such as voice and data), is encoded, divided, and spread across the frequency domain, rather than in the time domain as in traditional CDMA; the allowable transmission bandwidth is divided into a number of carriers. Using this scheme, a number of loading parameters such as code rate, data rate, and the number of streams into which the encoded data is divided may be varied to increase the performance of the system. Application of the variable loading parameter may be a function of channel quality, such as the presence of noise or the channel fading state.

Abstract: A method and apparatus for transporting data over a plurality of serial channels. A plurality of parallel data word are generated from a parallel data word of greater width. The plurality of parallel data words are scrambled in a predetermined manner utilizing a side scrambler to generate a plurality of cipher data words. A first bit is generated for each channel as an exclusive OR function from the cipher data word in the respective channel. A second bit is generated for each channel as an exclusive or function of the respective cipher data word and certain control information. The first bit is appended to the cipher data word for the channel from which it was derived. The second bit is appended to the cipher data word for a channel other than the one from which it was derived. The cipher data word and the first and second bits comprise a parallel extended width information word.

Abstract: A digital multiplexer circuit includes an input transmission line structure receiving input signals, multiplexing blocks having input terminals that are successively coupled together by the input transmission line structure, and an output transmission line that successively couples output terminals of the multiplexing blocks and receives output signals from multiplexing blocks.

Abstract: A routing switch includes a first router module having N1 signal input terminals, M1 signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N1 signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the N1 signal output terminals. The router further includes a second router module having N2 signal input terminals, M2 signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N2 signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the M2 signal output terminals.

Abstract: A method of transferring a serial data stream to a data framer includes converting the serial data stream to parallel data streams. The parallel data streams are synchronized and formed into one or more groups of synchronized parallel data streams. The one or more groups of synchronized parallel data streams are then transferred to the data framer at a transfer rate determined by the forming of the one or more groups.

Abstract: A full service channel access protocol that supports the integrated transport of voice, video and data communications is provided by dividing a communication channel into a plurality of frames, dividing each of the frames into a plurality of slots, and dividing some of the plurality of slots into a plurality of mini-slots. The mini-slots are provided for use by the multiple communication sources to request the establishment of a new voice, data, or video transmission connection over the communication channel. Additionally, a second one of the plurality of slots is divided into a plurality of second mini-slots for use by the multiple communication sources to request the establishment of a new voice, data, or video transmission connection over the communication channel and for use by the multiple communication sources to augment an existing video connection over the communication channel.

Abstract: A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.

Abstract: In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.

Abstract: The invention relates to a device and a method for compensating data run times. The invention provides a plurality of series/parallel converters (2), a plurality of data word synchronisation units (3), a plurality of storage devices (4) and a plurality of parallel/series converters (5) for simultaneously reading out the data that is stored in the plurality of storage devices (4). Data run times are compensated, especially by inserting or rejecting at least one predetermined code word into/from the plurality of data streams.