Abstract: This invention discloses an interface card built in each single unit of a CTI system and connected to the Voice Processing Unit (VPU) of the single unit via local CT-BUS. On the transmitting side of an interface card, low-speed signals from the VPU in the single unit are multiplexed into a single high-speed signal and converted into LVDS signals. On the receiving side of the interface card, external high-speed LVDS signals are converted into low voltage TTL signals, demultiplexed into local CT-BUS compatible low-speed signals and sent to the VPU in the single unit. The invention also discloses a CTI system applying the interface card. The interface card and the CTI system applying the interface card feature low cost, simple and reliable connection, easy installation and operation, high reliability, large channel capacity and good expandability.

Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.

Abstract: In a communication system comprising a mapper or other type of physical layer device coupled to a link layer device, the physical layer device comprises payload extraction circuitry and payload insertion circuitry. The payload extraction circuitry is configured to extract a payload from an ingress synchronous transport signal received over an ingress link, and the payload insertion circuitry is configured to insert a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link. The payload extracted from the ingress synchronous transport signal is transmitted by the physical layer device to the link layer device over an output serial data line of a serial interface, and the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device over an input serial data line of the serial interface.

Abstract: A driving circuit of a display device includes a timing controller for combining p first digital data signals (p being a positive integer greater than 1) corresponding to colors for displaying images to generate q second digital data signals and for supplying the q second digital data signals to first to qth data transmission lines (q being a positive integer smaller than p), and a plurality of data driver integrated circuits for processing the q second digital data signals from the timing controller to restore the p first digital data signals, converting the p restored digital data signals into analog data signals, and supplying the analog data signals to a display panel.

Abstract: A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.

Abstract: In one embodiment, the invention relates to a serial line circuit that comprises a serial information (SI) bus and at most two isolators interposed between a pair of programmable devices. In the TRANSMIT direction, a first programmable device is configured to multiplex serial data received from a plurality of serial UARTs and to route such data to the second programmable device over the SI bus and through a first isolator. In the RECEIVE direction, the second programmable device is configured to sample data from a plurality of serial interconnects and to route the sampled data to the first programmable device. The sampled data is routed over the SI bus and through a second isolator. The data transmission over the SI bus is in accordance with a proprietary serial transmission protocol described below.

Abstract: A network device comprises a multi-port MAC device that includes N MAC devices and that outputs a port multiplexed and encoded parallel data stream. A first serializer/deserializer (SERDES) serializes the port multiplexed and encoded parallel data stream from the multi-port MAC device.

Abstract: A method and a TDM digital switch are provided for switching data at a variety of data rates. Input streams having a data rate less than the maximum data rate of the switch are grouped and multiplexed to form multiplexed streams carrying data at the maximum data rate. A switching state machine switches the data from each input stream to form grouped output streams comprising multiplexed output streams, each grouped output stream carrying data at the maximum data rate. The grouped output streams are demultiplexed, and the output streams transmitted through respective output shift registers. The method and TDM digital switch allow streams with programmable data rates to be switched while still maximizing use of resources, including memory, within the switch.

Abstract: Provided is an optical transponder that receives a tributary signal such as a SDH/SONET signal, a GbE (Gigibit Ethernet) signal, and a SAN (Storage Area Network) signal in a WDM (Wavelength Division Multiplexing) transmission system and a SDH (Synchronous Digital Hierarchy)/SONET (Synchronous Optical Network) system, and more particularly, to an optical transponder having a switching function. The optical transponder having a switching function includes: a switch changing a data path of an input tributary signal from a plurality of channels (ports); an STM-64/OC-192 mapper/demapper mapping the tributary signal switched to a different data path by the switch to an STM-64/OC-192 signal or demapping the STM-64/OC-192 signal to the tributary signal; and a transmission delay time compensator compensating for a differential delay caused by a transmission route difference on an optical fiber link when the STM-64/OC-192 signal is demapped to the tributary signal.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: Disclosed is a method for transmitting and receiving data according to a channel state in a wireless communication system, the method includes measuring a characteristic of transmission channels used for data transmission and transmitting channel state information of the measured channel characteristic; and selecting sub-channels for data transmission according to the channel state information, and transmitting data through the selected sub-channels.

Abstract: Secure tunneled multicast transmission and reception through a network is provided. A join request may be received from a second tunnel endpoint, the join request indicating a multicast group to be joined. Group keys may be transmitted to the second tunnel endpoint, where the group keys are based at least on the multicast group. A packet received at the first tunnel endpoint may be cryptographically processed to generate an encapsulated payload. A header may be appended to the encapsulated payload to form an encapsulated packet, wherein the header includes information associated with the second tunnel endpoint. A tunnel may be established between the first tunnel endpoint and the second tunnel endpoint based on the appended header. The encapsulated packet may be transmitted through the tunnel to the second tunnel endpoint. The second tunnel endpoint may receive the encapsulated packet. Cryptographic processing of the encapsulated packet may reveal the packet having a second header.

Abstract: A communication apparatus includes at least one input port, multiple output ports, at least one Serial-to-Parallel (S/P) converter and at least one Parallel-to-Serial (P/S) converter. The S/P converter is operative to receive from the input port an input data stream that is to be cross-connected to a destination output port, and to separate the input data stream into multiple sub-streams. Each of the switching planes includes at least one input for receiving a respective sub-stream from the S/P converter; multiple outputs, each output associated with a respective one of the output ports; and switching circuitry, which is configured to switch the respective sub-stream to the output that is associated with the destination output port. The P/S converter is coupled to the outputs of the switching planes so as to combine the multiple sub-streams switched by the switching circuitry into a combined output data stream at the destination output port.

Abstract: A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue during a first system clock cycle, where Q<P, and sends, during the first system clock cycle, the Q data units to a processing device configured to process a maximum of Q data units per system clock cycle.

Abstract: Provided is a method for reducing a PAPR (Peak-to-Average Power Ratio) of a transmit signal in a broadband wireless communication. The method includes the steps of: assigning information signals to remaining tones except L reserved tones that are previously appointed among N tones, and performing an IFFT operation on the tones; detecting peaks that are greater than a predefined reference value from the IFFT-ed signal; generating signals for removing the detected peaks using P-waveform having impulse characteristic, the P-waveform being produced using the L reserved tones; generating a clipping signal by accumulating the signals; and simultaneously removing the peaks by adding the IFFT-ed signal and the clipping signal.

Abstract: An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and debugging on the IC, and generates testing results based on the at least one of the testing and the debugging. A serializer located on the IC receives the testing results from at least one of the embedded ICE and the embedded processor, serializes the testing results, and serially outputs the testing results from the IC.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: A method and apparatus for managing paging related delays between a mobile station and a base station is provided, which includes the use of a fractional slot cycle index. A first value for the slot cycle index, which is equal to an integer value less than a desired fractional slot cycle index value, is selected for use during a period of time corresponding to a determined proportion of a reduced slot cycle period, and a second value for the slot cycle index, which is equal to an integer value greater than a desired fractional slot cycle index value, is selected for use during a period of time corresponding to a remaining portion of the reduced slot cycle period.

Abstract: A wireless communication apparatus includes a random number range holding unit configured to hold a random number range, a random time setting unit configured to set a random time based on the random number range, a random time counting unit configured to count the random time starting from a particular time only when the radio communication channel is not used, a transmitting unit configured to transmit data via the radio communication channel when counting of the random time was completed, a time counting unit configured to count a particular time, and a random number range control unit configured to control the random number range such that when data transmitted by the transmitting unit over the radio communication channel collides with another data, the random number range is expanded, while when the particular time has been counted by the time counting unit, the random number range is initialized.

Abstract: A system is provided that retrieves test information from a target integrated circuit. A serializer receives the test information in a first format and divides and reformats the test information into first and second serial messages. The serializer is located on the target integrated circuit and has a first serial output that sends the first serial message and a second serial output that sends the second serial message. A deserializer communicates with the first and second serial outputs and receives the first and second serial messages. The deserializer retrieves a first portion of the test information from the first serial message, a second portion of the test information from the second serial message, and reconstructs the test information from the first portion and the second portion.

Abstract: A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: The invention relates to an insulation displacement plug-in connector for telecommunications and data technology, comprising a housing (45) and a number of contact elements (43), wherein the contact elements (43) each comprise an insulation displacement contact (54) for connecting cores and a pin contact (53) for making contact with a printed circuit board, wherein at least one extension (55) is arranged between the insulation displacement contact (54) and the pin contact (53).

Abstract: An interface module comprises a serial signal transceiver to be connected to an external transmission path and an interface processing unit connected to the transceiver. The interface processing unit comprises a serializer/deserializer circuit, an encoder/decoder, a protocol processing unit having at least two kinds of selectable protocol processing functions, and a communicate mode switch circuit for changing reference clock to be supplied to the serializer/deserializer circuit in conjunction with switching of the protocol processing function from one to another.

Abstract: A network monitor that taps data from a network link has first and second interfaces that allow the network monitor to be connected in-line in the network link between two network devices. The monitor has first and second programmable logic devices. The programmable logic devices are arranged to receive parallel data output by the interfaces and to process said data for network analysis purposes. Each programmable logic device is controllable so as to selectively pass a copy of the received parallel data to the other programmable logic device so that the network monitor can operate in in-line mode and not to pass a copy of the received parallel data to the other programmable logic device so that the network monitor can operate in end station mode.

Abstract: This communication system performs serial data communication between a master apparatus and a plurality of the slave apparatus via a data transmission line. The master apparatus generates, by using a controller, a serial conversion order control signal for controlling serial conversion order for the data in the slave apparatus, and then transmits the signal to the slave apparatus. The slave apparatus sets up serial conversion order for system information data in accordance with the serial conversion order control signal, then performs serial conversion in accordance with the set-up order, and then transmits the serial conversion data to the master apparatus. The master apparatus can read the system information data in the slave apparatus in the order specified by the serial conversion order control signal.

Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

Abstract: There is provided a serial compressed bus interface having a reduced pin count. The interface includes a serial-to-parallel converter having a single serial data input line adapted to receive time-division multiplexed serial data from a plurality of data sources. Enable logic is adapted to input at least one data valid signal that identifies each of a plurality of data consumers for which the time-division multiplexed serial data is valid.

Abstract: A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.

Abstract: Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A method and apparatus of communicating data packets across the midplane of an electronic system in which the packets are partitioned into segments of a predetermined size and then serialized to a predetermined width. The serialized packets are transmitted, in phase staggered segments, across the midplane on a respective channel, received into receiving end and the serialized segments that have traversed the midplane, are deserialized and reassembled into the original data packet.

Abstract: A signal transmission system has a master node and plural slave nodes performing data transmission with the master node. The master node has a serial-to-parallel converter for converting a serial data signal from each slave node into a parallel data signal. Each slave node has a transmission aligner for performing word alignment processing upon a parallel data signals, and a parallel-to-serial converter for converting the parallel data signal subjected to the word alignment processing by the transmission aligner into a serial data signal, and outputting the serial data signal to the master node.

Abstract: The invention provides apparatuses and methods for quickly modifying state information. Preprocessing prepares the state information to be modified. A logic unit modifies the state information. Postprocessing then puts the modified state information in proper form for output.

Abstract: An optical transmission system accomplishes optical transmission over a long distance by combining a multiplexing line terminal with optical amplifiers, linear repeaters, and regenerators with optical amplifiers combined together. The system also accomplishes the optical transmission over a short distance by directly connecting the linear terminals therebetween, with an electric-to-optic converter replaced by an electric-to-optic converter having a semiconductor amplifier, with an optic-toelectric converter by an optic-to-electric converter having an avalanche photodiode as light receiver, and with no use of any optical booster amplifier and optical preamplifier in multiplexing line terminal. With these, the optical transmission system can be easily constructed depending on the transmission distance required.

Abstract: A method of communicating over a wideband communication channel divided into a plurality of sub-channels comprises dividing a single serial message intended for one of the plurality of communication devices into a plurality of parallel messages, encoding each of the plurality of parallel messages onto at least some of the plurality of sub-channels, and transmitting the encoded plurality of parallel messages to the communication device over the wideband communication channel.

Abstract: The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect.

Abstract: A high-speed router and method for operation of the core of such a router are disclosed. The disclosure describes switching packet data through a router core serving core ingress and egress ports. The router maintains at least one always-up ingress serial link from each core ingress port to the router core, and at least one always-up egress serial link from the router core to each core egress port. For each core ingress port, packet data is serialized prior to introduction to the router core and then transmitted to the core over that port's ingress serial link. Each core egress port receives a serialized data stream from the router core, which is then deserialized. Within the router core, the serialized data received on each ingress serial link is deserialized into a clocked digital data stream. The digital data streams are switched through a reconfigurable digital switch, reserialized, and transmitted over the egress serial links.

Abstract: Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

Abstract: An apparatus and method for transferring data bursts in an optical burst switching network are provided.

Abstract: A receiver for deserializing a stream of data bits, including a single clock which is adapted to generate a first plurality of clock phases, and a sample generator which is adapted to sample the stream so as to generate initial data values of each of the bits at times defined by the first plurality of clock phases. The receiver further includes digital circuitry which is adapted to group the initial values into a second plurality of sampling phase sets, according to the clock phases at which the values were sampled, and assign each of the phase sets a respective grade in response to at least some of the initial values. The circuitry selects a decoding phase set from the phase sets in response to the respective grades, and decodes the stream in response to initial values of the decoding phase set to generate decoded values of the consecutive bits.

Abstract: An apparatus and method for selecting and recording multi-directional communication packet traffic in a compact manner in realtime while maintaining relative time between the selected packets passing in one direction and the selected packets passing in another direction. The apparatus includes a protocol interface, a block datapath, a record resource, and a trace merge memory. The protocol interface receives X and Y channel packets with interspersed idle times, segments the packets into time-aligned X and Y blocks, and eliminates idle times. The block datapath merges the X and Y blocks, then filters unneeded X and Y channel packets by purging the X and Y blocks from those packets. The record resource compares patterns for identifying the unneeded packets and trigger events. The trace merge memory records the time-aligned filtered merged block stream in a compact form for later analysis.

Abstract: An SFP module provides either a 1000Base-X or SGMII interface protocol to a host and provides a 1000Base-T media dependent interface (MDI). If the SFP module is coupled a host that only implements the 1000Base-X protocol then the SFP module translates the 1000Base-X protocol to the 1000Base-T protocol so that the host MAC sees the 1000Base-T SFP module as if it were an optical transceiver. If the host implements SGMII then the SFP performs auto-negotiation of speed and communicates with the host implement data transfer at a selected rate, e.g., 10, 100, or 1000 Mbps.

Abstract: Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

Abstract: A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of weighted sums of the N digital data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective weighted sum of the N analog data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a second matrix.

Abstract: A method and apparatus for interfacing a parallel connection, the parallel connection transmitting high bit-rate signals for a short distance. The method comprises: receiving a synchronous N-bits input data flow at a first input frequency; inserting said input data flow into parallel packets having a given length; and outputting said packets having a given length at a second output frequency onto a M-wires parallel connection.

Abstract: A switching device comprises at least two base racks, each base rack including a switch card in communication with a line card across a backplane, the line card having at least an external port. The at least two base racks are coupled such that the switch cards of each are linked. A method for switching a packet comprises introducing the packet into an external port on a first base rack, transmitting the packet from a first cascade port on the first base rack to a second cascade port on a second base rack, and sending the packet out of the second base rack through a second external port.

Abstract: A packet processing system converts a wide bus carrying P packets to a narrower bus that can carry only Q packets, where Q<P. The packet processing system includes a first data path, a queue, a shift register and a control unit. The first data path receives up to P packets during a first processing cycle. The queue stores the P packets in a queue. The control unit shifts a first quantity of data of the P packets into the shift register from the queue and selectively retrieves data from the shift register until a first packet of the plurality of packets is retrieved. The control unit then sends the first packet on a second data path during the first processing cycle.

Abstract: Method and circuitry for performing a line loop back test includes a receiver, a deserializer, and a low speed parallel loop back data multiplexer selects either the low speed parallel data from the deserializer when in loop back mode or low speed parallel input data when in normal mode. The deserializer produces a low speed clock output signal that is fed to a low speed loop back reference clock multiplexer and also to a low speed loop back clock multiplexer. Both the loop back reference clock multiplexer and the loop back clock multiplexer select the low speed clock output signal from the deserializer when in line loop back mode. A clock multiplying unit converts the output of the low speed loop back reference clock multiplexer into a high speed clock signal. The serializer generates the high speed serial transmitter data in synchronization with the high speed clock signal received from a clock multiplying unit.

Abstract: A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. An efficient encoding scheme permits transmission of both isochronous and non-isochronous data over existing media, such as twisted pair, without degrading bandwidth previously achieved for non-isochronous data over the same media, such as using an ethernet system. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware. Preferably, the present invention can be implemented in a fashion that is transparent to already-installed media access controllers.