Abstract: First to fourth input buffers stores cells inputted from first to fourth input ports, respectively. Each input buffer is equipped with a main buffer section, a plurality of sub-buffer sections connected to the main buffer section in series and a buffer controller for controlling them. A collision judging section judges whether or not a collision occurs between the cells outputted from each sub-buffer section, and the judged result is sent to a cell converter. The cell converter returns a collision information to the buffer controller in accordance with the judged result, and further sends a cell, which has a victory information since it is judged as a victory over the collision, through a sorter to a self-routing section. The self-routing section outputs the received cell to an output port. This configuration enables a shuffle operation to be carried out in the sub-buffer section and the cell converter to thereby avoid the drop of the throughput.

Abstract: In a method and arrangement for controlling accesses of network terminal units to predetermined resources of a packet-oriented communication network, in the context of connection setups, partial communication network resources requested by network terminal units arranged in a packet-oriented communication network are assigned to these units by entering access authorizations into annularly chained memories. By sampling the memories, the access to the assigned partial communication network resources is granted to the network terminal units in a manner corresponding to the entered access authorizations. Advantageously, the communication network resources are distributed to arbitrarily many network terminal units.

Abstract: A prioritized buffer for the Medium Access Control (MAC) layer for multimedia applications, in particular wireless Asynchronous Transfer Mode (ATM) in which reservation based TDMA is performed on the basis of control data frames (CDFs), is formed by an addressable memory system which is divided into sequential equal-sized pages for storing respective data packets or ATM cells having the same number of bytes. The memory system includes a tag register for storing tags associated with the respective pages, each tag indicating whether the associated page is empty or full, a shadow register for storing conflict-free updates from the tag register, and a page register for storing pointers to the lowest free or unoccupied page.

Abstract: A multiport data communication system for switching data packets between ports having a memory storing received data packets and a plurality of ports for transmitting and receiving data packets. Each transmit port has a transmit queue storing data packets to be transmitted from the respective port. The system includes a plurality of output queues, each corresponding to a respective port and storing frame pointers that point to where the data packets are stored in the memory. A plurality of dequeuing logic circuitry is provided corresponding to the plurality of ports. Each dequeuing logic circuitry reads respective frame pointers from the plurality of queues, reads the respective data packets corresponding to the respective frame pointers from the memory, and writes each read data packet to the corresponding transmit queue. The operations of each dequeuing logic circuitry are carried out in a pipelined manner in order to fully utilize the bandwidth of the external memory and speed up the dequeuing process.

Abstract: A method and apparatus for determining a percent utilization of shared resource and fine resolution scaling of a threshold based on the utilization is described. In one embodiment, the method includes detecting a cell that belongs to a VC queue where the VC queue includes a cell count, a minimum threshold cell count, and a maximum threshold cell count. The cell count is compared with the minimum threshold cell count. If the cell count is greater than (or equal to) the minimum threshold cell count, the method further includes determining a ratio between the cell count and the maximum threshold cell count, selecting a scaling factor responsive to the ratio, scaling the cell count by the scaling factor to provide a scaled cell count, comparing the scaled cell count with a maximum threshold cell count, and discarding the cell if the scaled cell count is greater than the maximum threshold cell count.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: A switching system for switching data with rate conversion between a high speed bus and a low speed bus, comprising a double-buffered data memory having a read-only port and a write-only port, a plurality of registers and selectors for receiving and storing successive frames of data from one of either the high speed bus or low speed bus into the data memory via one of the write-only port or said read-only port, respectively; and a connection memory containing a plurality of entries each having a first bit indicating channel ON/OFF status, an additional plurality of bits identifying connection addresses for the received frames of data; and a further plurality of index bits for addressing and reading the data memory via the other one of the write-only port or read-only port in the event the first bit is set and thereafter outputting the data to the other one of the high speed bus or low speed bus.

Abstract: A method and apparatus are disclosed for reclaiming frame buffers used to store data frames received by a network switch. The apparatus includes a multicopy queue for queuing entries corresponding to received data frames which must be transmitted by multiple output ports of the network switch, a free buffer queue for queuing frame pointers that identify locations in an external memory where reclaimed frame buffers are located, and a multicopy circuit that retrieves entries from the multicopy queue and determines if all copies of a received data frame have been transmitted by the specified output ports. The multicopy circuit also reclaims one or more frame buffers, based on the size of the received data frame. The present invention allows efficient reclaiming of frame buffers regardless of whether the received data frame is stored in a single frame buffer or multiple frame buffers.

Abstract: A process for detecting upstream congestion within an ATM switch. The switch includes several junctions linked together by a cross-connector. In each input junction, the number of incoming cells bound for a same specified output port of a junction are counted. Results of the count supplied by the input junctions are transferred to the output port. Results of the counts in the output junction are aggregated and a congestion is declared in the output port if the aggregate number of cells is greater than a specified threshold value.

Abstract: A method of receiving a set of data packets which represent a contiguous data block sent over a bus between two nodes. A memory allocation unit allocates memory beginning at a known address to a local node. The local node divides the address into multiple segments that include predetermined transaction label overlay portions. Thereafter, the local node issues request packets which include transaction labels in a header of the request packet that correspond to the predetermined transaction label overlay portions. Subsequently, a remote node sends responses, and a header of the responses includes the transaction label that corresponds to the request. The local node routes response packets to a dedicated context. The dedicated context replaces the transaction label for the transaction label overlay portion to route the response packet to a proper memory location, regardless of the order in which the packet was received.

Abstract: Methods and systems for managing data packets in various communication networks are provided. The system includes a first memory for storing at least a free data pointer and a buffer descriptor. The free data pointer points to a data buffer allocated in a second memory. The buffer descriptor includes at least a data pointer pointing to a data buffer configured to store one or a portion of the communication packet. The first memory has a maximum threshold such that if the number of buffer descriptors stored in the first memory reaches the maximum threshold one or more buffer descriptors stored in the first memory are transferred to the second memory.

Abstract: A communication protocol stack apparatus and method determine the aggregate maximum header and trailer lengths(H, T) and a payload size(P) for each layer of the protocol stack and pre-allocate for each layer one or more buffers of a length equal to the sum of “H”, “T” and “P”. The layer copies receiving data into the pre-allocated buffer at a position determined by “H”, and copies its header and trailer immediately before and after the data in the buffer. The layer sets two references. The next lower layer copies its header and trailer into the buffer at the positions determined by the references and updates the references. The process is repeated until the lowest layer and data between the references is copied to a physical device for transmission.

Abstract: An apparatus for restoring the cell data storage regions of the common memory in an asynchronous transfer mode (ATM) switch system, comprises a first multiplexer for multiplexing the cell data with the header and content data separated, a second multiplexer for multiplexing the addresses generated from a plurality of FIFO registers, an address checker for checking the addresses from the second multiplexer to generate a first and second address signals if the addresses are checked normal, an address memory storing all addresses of the common memory in error state to selectively convert the addresses into normal state according to the second address signal from the address checker, a controller for checking the address memory at predetermined intervals to restore an address stored in error state to a normal state, and an address multiplexer for generating an idle address to an IAP according to the first address signal and address restored signal.

Abstract: A multiport data communication system for switching data packets between ports includes a plurality of receive ports for receiving data packets, a plurality of transmit ports for transmitting data packets, circuitry deciding whether each received data packet is one of high priority and low priority, and a memory for storing each received data packet. A memory location designator is provided for each data packet indicating where the corresponding data packet is stored in the memory and a plurality of queuing devices corresponding to the plurality of transmit ports queue the memory location designators. Each queuing device has a high priority queue queuing memory location designators corresponding to data packets of high priority to be retrieved from the memory an transmitted by the respective transmit port and a low priority queue queuing memory location designators corresponding to data packets of low priority to be retrieved from the memory and transmitted by the respective transmit port.

Abstract: A switch for switching fixed size ATM cells and variable length packets of a network. The switch includes an input port mechanism having a plurality of input ports each able to receive cells and packets from the network. The switch includes an output port mechanism having a plurality of output ports each able to send cells and packets to the network. The switch includes a switching fabric connected to the input port mechanism and the output port mechanism for switching either packets or cells from any input port to any output port. The switch includes a mechanism for converting packets to cells when the input port is a packet port and the output port is a cell port and cells to packets when the input port is a cell port and the output port is a packet port, respectively, or not converting cells or packets when the input port and the output port are both cell ports or both packet ports, respectively. The converting mechanism is connected to the output port mechanism and the switching fabric.

Abstract: Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: A communication control apparatus which effectively uses a memory and does not need complicated hardware is realized. Each area of a frame assembly memory 2 is set to the maximum frame length which is handled. When a cell of a new connection is inputted, a memory write control unit (1) allocates the connection to an empty area in the memory (2) and writes the cell therein. When the cell of the same connection as that already allocated to any area is inputted, it is written into the allocated area. If a plurality of cells of one frame have already been written in the area of the same connection, the connection is allocated to another new area and the cell is written therein. A memory read control unit (3) reads out the cells of one frame and outputs them as one completed-frame data.

Abstract: A cell re-sequencer for re-sequencing the cells switched by an ATM switching system, comprises a maximum delay register for setting the maximum delay value by initialization to output the maximum delay value according to internal clock pulses, a base address increment register for increasing the initial value of the initialization set as a base address one by one according to cell time clock pulses, a delay detector for detecting the real delay of a cell from its header, a cell storing address generator for adding the base address to the delay difference between the maximum delay and real delay to generate a cell storing address, a multiplexer for multiplexing the base address and cell storing address according to the cell time clock pulses, and a memory address register for temporarily storing the output of the multiplexer.

Abstract: A network cell is delayed by a predetermined time by injecting one or more delay cells ahead of the cell into a queue in a network (e.g., an ATM network). The queue may comprise a cell egress queue at a switch of the ATM network and the delay cells may be generated at the switch using a local processor. If required, additional cells may be generated by replicating the locally generated cells. The delay cells, including the replicated cells, may be stored together with the network cells in the queue; the number of delay cells so stored being controlled by configuring a threshold for the egress queue.

Abstract: The present invention provides an ATM switch which includes: memory for storing identification information which identifies user-network interfaces with terminals, analysis control data for analyzing a call control signal for each user-network interface, and editing control data for editing a call control signal for each user-network interface; analysis circuit for analyzing a first call control signal in accordance with the analysis control data corresponding to a first user-network interface identified on the basis of the identification information when the first call control signal is received from a first terminal for setup with a second terminal; call control circuit for performing call control based on the first call control signal analyzed by the analysis circuit; and editing circuit for editing the first call control signal to a second call control signal in accordance with the editing control data corresponding to a second user-network interface identified on the basis of the identification informati

Abstract: In an ATM communication apparatus, when a transmission schedule section determines a transmission virtual channel, payload data corresponding to a plurality of cells is read out from a host memory if no payload for the virtual channel is present in a transmission payload temporarily storing section. The payload corresponding to a first cell, a corresponding cell header, and a corresponding cell trailer are formed into a transmission cell. The cell is transmitted to a physical layer device. Payloads corresponding to the second and subsequent cells are temporarily stored in the transmission payload temporarily storing section. When the transmission schedule section determines the virtual channel as a transmission virtual channel afterward, a payload is read out from the transmission payload temporarily storing section if the payload is stored therein. The read payload, corresponding header information, and corresponding trailer information are formed into a transmission cell.

Abstract: An apparatus for serving ATM packets, each packet having cells. The apparatus includes a server which provides service to a cell. The apparatus includes a scheduler mechanism which determines which cell is to receive service from the server. The scheduler mechanism is connected to the server. The apparatus includes a shared memory mechanism having a first region for storing cells of a first packet of a first connection and at least a second region for storing cells of a second packet of a second connection. Each region has a dynamic size determined by demands of the corresponding connection. An apparatus for serving ATM packets, each packet having cells. The apparatus includes a server which provides service to a cell. The apparatus includes a scheduler mechanism which determines which cell is to receive service from the server. The scheduler is connected to the server.

Abstract: Port cards in an ATM switch store parameters for virtual channel connections (VCCs) and virtual path connections (VPCs) in separate areas of a virtual connection parameter table (VCPT), the areas being defined by a VCC pointer and a VPC pointer. Also, a number of “free lists” are used to identify unused single locations (for VPCs) or chunks of locations (for sets of VCCs) that are available for re-allocation. Different free lists are used for different-sized sets of VCCs, i.e., sets configured to use different maximum numbers of VCI bits. When a new VPC is created, a VCPT location identified by an entry in the VPC free list is allocated, if such an entry exists. Otherwise a VCPT location is allocated by advancing the VPC pointer. De-allocation of a VPC entry proceeds in reverse order, i.e., the VPC area is shrunk by backing up the VPC pointer if possible, and if not the de-allocated entry is placed on the VPC free list.

Abstract: Circuitry to free the core processor from performing the explicit read operation required to read data into the internal register set. The processor's register set is expanded and a “shadow register” set is provided. While the core processor is processing one event the “context” and “data” and other associated information for the next event is loaded into the shadow register set. When the core processor finishes processing an event, the core processor switches to the shadow register set and it can begin processing the next event immediately. With short service routines, there might not be time to fully pre-fetch the “context” and “data” associated with the next event before the current event ends. In this case, the core processor still starts processing the next event and the pre-fetch continues during the event processing.

Abstract: A two (2) dimensional shaper uses a hierarchical searching technique to find the first memory location of the calendar queue with a validity bit of “1” (that is, the lowest time stamp). The bit string at any level l (l≠0) can be stored in a RAM of size glMl−1. The string at the highest level in the hierarchy (l=0) can be stored in an M0 bit register.

Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.

Abstract: The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell.