Abstract: A method and apparatus for searching a forwarding table are provided.

Abstract: Streaming data is processed through one or more pipes of connected modules including mixers and/or splitters. The data is carried in composite physically allocated frames having virtual subframes associated with different ones of the splitters, mixers, and other transform modules. Nesting trees and pipe control tables represent the structure of the pipes. A frame allocator is assigned to a particular module in a pipe. Rather than issuing a control transaction to all modules when any one of them completes an operation upon its source data, a control manager requests a module to begin its operation only when all of its input subframes have become available. Frame control tables record when any module has completed an operation, and a pipe control table lists which modules provide data to which other modules.

Abstract: There are disclosed processes and apparatus reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.

Abstract: One (SC3) of the sockets (SC) is designated to be capable of receiving the data stream received by each socket associated with a selected process, Said socket thereby designated (SC3) further comprises an additional receive list (RXS) listing buffer memories containing the data stream received by all of the sockets involved in a selected process. The buffer memories (SKB) of each socket (SC1, SC2, SC3) simultaneously belong to both receive lists (RX, RXS), and each further comprise an additional “previous” pointer (PPS) indicating the buffer memory which precedes the current buffer memory in the additional receive list (RXS), and an additional “next” pointer (PSS) indicating the buffer memory which follows the current buffer memory in the additional receive list (RXS), which makes it possible to access the data stream received by the set of sockets involved in said process, in the order in which said received data stream arrived.

Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

Abstract: A device is coupled to a first network and a second network and comprises a first storage element and a second storage element. The device stores data packets originating from the first network in the first storage element and stores data packets destined for the second network in the second storage element. In particular, the device slaves the writing of a data packet intended for the second network into the second storage element to the reading of the data packet from the first storage element so that the transfer time inside the device is constant for all the data packets.

Abstract: A communications apparatus for directly transferring payload data included in a received packet to an application memory area. The communications apparatus comprises an error check unit for checking the payload data for an error, a write processing unit for performing write processing for writing the payload data into the application memory area, and a protocol processing unit for causing the write processing unit to start write processing to write the payload data into the application memory without waiting for the completion of the error check, and upon detection of an error, returning a valid section in the application area that has been overwritten by write processing to an invalid section which has not stored normal data.

Abstract: A method for forwarding service in the data communication device and the forwarding apparatus, said apparatus includes a memory unit and a forwarding unit, wherein storing the Route Prefix, the private data of the Route Prefix and the corresponding Next Hop Array; said forwarding unit forwards the service at the data communication device according to said private data and the Next Hop corresponding with the Route Prefix. Using the present invention, it can implement the corresponding different a process for the different Prefix while the data communication device is forwarding service. It also may constitute a new-style FIB using the present invention, accordingly not only improve the updating speed of FIB, save the internal memory of the data communication device, but also satisfy the requirement that the different Prefixes need to have the different private domains with some specific functions.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: Computing resources available on multiple computing devices are consolidated by an intermediate computing system and provided to other computing systems when those computing systems need additional bandwidth and processing power they cannot provide by themselves.

Abstract: A preferred embodiment comprising a data switch includes a first processor for routing data packets including a MAC address, using a MAC address table stored in a writable memory. The switch further includes a second processor for routing data packets including an IP address using an IP address look-up table stored in the writable memory. The writable memory consists of a single memory fabric that is allocated between the MAC address table and the look-up table by a memory control unit according to a setting stored in a non-erasable memory unit.

Abstract: Included are methods for facilitating routing of control data associated with a communication to a plurality of recorders. One such method, among others, includes receiving control data related to a communication and routing the received control data to at least one recorder via a layer 3 protocol.

Abstract: Mechanisms for programming and performing combined interface and non-interface specific associative memory lookup operations for processing of packets are disclosed. One system includes multiple interfaces, a content-addressable memory, multiple memory entries and a lookup mechanism. The content-addressable memory includes multiple interface independent entries, multiple first interface dependent entries corresponding to the first interface, and multiple second interface dependent entries corresponding to the second interface. The lookup mechanism is configured to initiate lookup operations in order to produce the interface independent and interface dependent results.

Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Abstract: A method and interface are provided for using a memory that distinguishes transmission data from reception data and performs a First-In-First-Out (FIFO) operation on the transmission and reception data in a communication system. In the method, a controller receives from a register a last transmission address provided for dividing one memory module having L addresses into a transmission area having M addresses according to application, where M is less than or equal to L, and a reception area having (L-M) addresses. A codec interface allocates a first address up to the last transmission address of the memory module for the transmission area. The codec interface allocates an address increased by 1 from the last transmission address up to the last address of the memory module for the reception area.

Abstract: A method and apparatus for receiving packets from a node within a first network in accordance with a first protocol. A descriptor associated with each received packet is read by a direct memory access (DMA) controller that stores the received packet. A value for a controllable parameter is selected to efficiently communicate the content of the received packet over a second network that operates in accordance with a second protocol. The information in the received packet is then organized into newly formed packets, the size of which makes them efficient for communication over the network in the second protocol. The newly formed packets are stored in a transmit line buffer and associated with a Protocol Descriptor. The Protocol Descriptor provides information to a transmit controller to allow the transmit controller to select and aggregate packets from the transmit line buffer in order to make efficient use of the second protocol.

Abstract: Reducing pool starvation in a switch is disclosed. The switch includes a plurality of egress ports, and a reserved pool of buffers in a shared memory. The reserved pool of buffers is one of a number of reserved pools of buffers, and the reserved pool of buffers is reserved for one of the egress ports. A shared pool of buffers and a multicast pool of buffers are in the shared memory. The shared pool of buffers is shared by the egress ports.

Abstract: Systems and methods for increasing the efficiency of communications between master devices and slave devices in a system. A master normally sends a command to a slave if a token from the slave is received. Determining whether a token is of the correct type requires multiple processing cycles. Alternatively, if all of the slaves have available buffer slots, an “all token available” signal is asserted. When the “all token available” signal is received, the master can send any command without having to decode any of the tokens.

Abstract: A prime number based pointer allocation technique. A packet-forwarding system incorporating the technique stores cells of a packet in packet memory, according to allocated pointers that have a fixed correspondence to locations in the packet memory. Each packet input interface of an ingress module has a memory parameter counter that is incremented by a different prime number each time a memory pointer is allocated to that input interface. The memory parameter counter includes a memory interface portion and a memory bank portion that correspond to the memory interfaces and memory banks of a packet memory with which the memory pointers are associated.

Abstract: A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to receive data from the at least one data port interface, determine if the data is to be stored in one of the first memory or the second memory, store the data in one of the first memory or the second memory as a linked list, retrieve the data from one of the first memory or the second memory, and forwards the data for egress.

Abstract: The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. According to another aspect of the present invention, a system for handling transmission of network packets which are assembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.

Abstract: A method for operating a node of a communication network including a plurality of peer-to-peer nodes, the node being linked with predetermined neighbour nodes among the plurality of peer-to-peer nodes, includes: a) storing, on a first storage area, node information indicative of predetermined data required by the node to become an information provider node; b) waiting to receive from at least one information provider node of the neighbour nodes describing information of data that can be provided by the information provider node; c) at the receipt of the describing information from the at least one information provider node, checking in the first storage area if the data that can be provided by the at least one information provider node match at least in part the predetermined data required by the node; d) in the affirmative, deleting in the first storage area the node information indicative of the matching data; and e) in the negative, forwarding the describing information received in c) to at least one of th

Abstract: A controller controls exchange of data between a plurality of storage units based on transfer rates of the storage units and a fixed rate. If at least one of the transfer rates of a transfer-source storage unit and a transfer-destination storage unit are different than the fixed rate, the controller accumulates a certain amount of data, and outputs accumulated data to the transfer-destination storage unit at the transfer rate of the transfer-destination storage unit so that data is transferred from the transfer-source storage unit to the transfer-destination storage unit at apparently at the fixed rate.

Abstract: In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeuing of the selected packet identifiers.

Abstract: In one embodiment, a method and apparatus for a mechanism for data and event management across networks is disclosed. The method includes creating one or more random connections to transmit event data between agents in a data management network, the agents to maintain the event data for the data management network without utilizing a central management system, randomly removing one of the random connections, and forming another random connection between the agents. Other embodiments are also disclosed.

Abstract: A method for communication includes inputting from a host processor to a network interface device a sequence of work requests indicative of operations to be carried out by the network interface device with respect to a plurality of the connections. The device looks ahead through the sequence in order to identify at least first and second operations that are to be carried out with respect to one of the connections in response to first and second work requests, respectively, wherein the second work request does not immediately follow the first work request in the sequence. The device loads the context data for the one of the connections from a host memory into a context cache, and performs at least the first and second operations sequentially while the context data are held in the cache.

Abstract: A shared memory system including: a shared memory includes a plurality of memory banks; a plurality of input ports; a plurality of input buffers; and a controller for controlling writing-into and reading out of the shared memory and for transferring data from each of the input buffers to the shared memory, wherein when one of the memory banks is cycled back next to the starting memory bank, another memory block is to be selected next for writing the remainder of a series of data, said controller controlling each of the input buffers to transfer a plurality of series of data to the shared memory successively with a time gap while switching to said another memory block, said controller offsetting a start memory bank in said another block for start writing the remainder of the series of data by an amount of memory banks corresponding to the time gap.

Abstract: The present disclosure provides a network data storage system and a network data access method. The disclosed network data storage system includes: a data node, used for storing a data unit; a metadata node, used for storing and managing routing information and providing the routing information according to a data processing request of a client; and a data management node, used for processing the requested data unit in the data node according to a data access request of the client. The disclosed system and method may improve access performance of network data, enhance expansibility of a system, and lower expansion cost.

Abstract: A method for overhead processing of optical network and device thereof are disclosed, the device includes: an overhead memory, an overhead processor, and an overhead processor control module. The overhead processor control module is used for controlling the operation of the overhead memory and the overhead processor. The method includes: a system chip inputs the time slots of all overhead bytes that will be processed and descrambled data, and corresponding virtual container numbers, the overhead processor encodes the byte and stores all overhead byte of the same channel in the address of the same overhead memory; at the same time it stores in turn the overhead byte of different channels in different address spaces based on the virtual container numbers, so that an overhead processing logic performs a polling process. The method and device only use a set of overhead processing logic for the overhead of large capacity chips, and save the area and power consumption greatly, thereby reduce the production cost.

Abstract: Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.

Abstract: A network system includes a first device and a second device separated by a network having asymmetric routes in which traffic forwarded in a first direction from the first device to the second device may travel a different route than traffic forwarded in a second direction from the second device to the first device. At least three intermediate processing devices are located between the first device and the second device, wherein at least two of the intermediate processing devices are located along different asymmetric routes. The intermediate processing devices intercept a communication flow between the first device and the second device, and encapsulate the communication flow within network tunnels so that communications associated with the communication flow in the first direction and the second direction are forwarded between a same set of at least two of the intermediate processing devices.

Abstract: Methods, systems and computer program products for an N-port network adaptor that is interchangeable between a network switch and a network adaptor. Embodiments of the invention include a method in a network device having a random access memory, a non-volatile random access memory and a flash memory, the method including operating in a network switch/router mode of operation, operating in a network adapter mode of operation and switching in between the network switch/router operation and the network adapter operation in response to receiving a device configuration signal.

Abstract: Presented is a device for processing packets of flows on a network link. The device includes a scheduling module for scheduling packets in a queue in accordance with a fair queuing with priority algorithm.

Abstract: A digital signal-processing device is described which comprises a recording controller for control of recording in the memories drives a trigger-switching element arranged in the trigger line downstream of the two parallel-operating signal-processing units in such a manner that essentially the same timing period is recorded in both memories during a post-triggering period after a trigger time.

Abstract: A packet counter/adder for use in a multiprocessor system. The packet counter stores a counter value of data packets processed by a plurality of processors in the multiprocessor system. The packet counter comprises a first register capable of storing the counter value, wherein the counter value in the first register is incremented by a write operation to a first address associated with the first register. The counter value in the first register may be set to a specified value by a write operation to a second address associated with the first register.

Abstract: A method for cache management includes assigning a respective cache line in a cache of a processing device to each of a plurality of processing flows in the processing device, and loading respective context data relating to each of the processing flows from a memory into the respective cache line that is assigned thereto. Respective activity levels of the processing flows are monitored. Responsively to detecting an absence of activity of a processing flow, and prior to receiving a request to overwrite the cache line, the context data are written back to the memory from the respective cache line that is assigned to the processing flow.

Abstract: An address learning method for a network device having a plurality of connection ports, at least one of which is electrically connected to a terminal device. The method includes a fetching process, a hashed-address generating process, a data registering process and an address registering process. The fetching process fetches an address data string from a first memory unit by a programmable logic device (PLD). The hashed-address generating process generates a hashed-address by the programmable logic device. The data registering process writes the address data string into an address data table. The address registering process writes the hashed-address into a hashed-address table. A network device for performing the address data learning method is also disclosed.

Abstract: A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network are provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally intermediate states are restored, processed, and saved when the service byte engine changes to process a different data stream or a different frame of data of a given service.

Abstract: Disclosed is an input port to one or more switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Abstract: To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnection, the data caching control units are divided into plural control clusters, each of the control clusters including at least two or more data caching control units, control of a cache memory is conducted independently for each of the control clusters, and one of the plural data caching control units manages, as a single system, protocol transformation units and the plural control clusters based on management information stored in a system management information memory unit.

Abstract: A system and method for facilitating packet transformation of multi-protocol, multi-flow, streaming data. Packet portions subject to change are temporarily stored, and acted upon through processing of protocol-dependent instructions, resulting in a protocol-dependent modification of the temporarily stored packet information. Validity tags are associated with different segments of the temporarily-stored packet, where the state of each tag determines whether its corresponding packet segment will form part of the resulting modified packet. Only those packet segments identified as being part of the resulting modified packet are reassembled prior to dispatch of the packet.

Abstract: An inter-networking system and method that provides for access control identifier (ACI) metadata utilization for the life of a session even on unknown networks being traversed, allowing for ACI metadata utilization, reutilization, and modification in both the send and receive paths (bi-directional), and allowing for metadata transport over network segments requiring that ACIs be embedded at different layers of the communications stack.

Abstract: Deadlock is avoided in a grid storage system having superior scalability. Provided is a storage subsystem connected to a host computer for receiving a write or read access from the host computer. This storage subsystem includes a plurality of modules respectively having a storage resource, a switch for connecting the plurality of modules, a controller for controlling the transfer of a packet based on the write or read access from the host computer to a target module among the plurality of modules via the switch, and a memory storing a transfer rule of the packet. The controller controls the transfer of the packet based on the transfer rule.

Abstract: Methods, apparatuses, and systems directed to efficient compression processing in system architectures including a control plane and a data plane. Particular implementations feature integration of compression operations and mode selection with a beltway mechanism that takes advantage of atomic locking mechanisms supported by certain classes of hardware processors to handle the tasks that require atomic access to data structures while also reducing the overhead associated with these atomic locking mechanisms.

Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

Abstract: A network device switches variable length data units from a source to a destination in a network. An input port receives the variable length data unit and a divider divides the variable length data unit into uniform length data units for temporary storage in the network device. A distributed memory includes a plurality of physically separated memory banks addressable using a single virtual address space and an input switch streams the uniform length data units across the memory banks based on the virtual address space. The network device further includes an output switch for extracting the uniform length data units from the distributed memory by using addresses of the uniform length data units within the virtual address space. The output switch reassembles the uniform length data units to reconstruct the variable length data unit. An output port receives the variable length data unit and transfers the variable length data unit to the destination.

Abstract: A decoder for decompressing real-time media data streams and a method for operating such a decoder is disclosed. The decoder may comprise a relatively larger first memory for storing compressed data and parameters, and a processor for executing a decompression algorithm, the processor having a relatively smaller second memory. The decompression algorithm may be executed on a periodic basis, and the parameters used to select the data to be decompressed may be moved from the second memory to the first memory each time the decompression algorithm executes. An embodiment of the present invention may use slower, less expensive memory to enable it to support a greater number of real-time media streams than prior art solutions. Another embodiment of the present invention may include machine-readable storage having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the foregoing.

Abstract: A reorder mechanism for use with a relaxed order interconnect device. The reorder mechanism includes a buffer module and a reorder module coupled to the buffer module is disclosed. The reorder module enables movement of multiple packets between a plurality of resources. The movement of multiple packets of information has a relaxed ordering of data transfers associated with multiple packets and also a relaxed ordering of data transfers associated with any single packet.

Abstract: A method of handling data in a memory of a network device is disclosed. The method includes the steps of storing portions of a datagram, being handled by a network device, in a memory, where the memory comprises two logic memory blocks, storing at least two pointers with the portions of the datagram in the memory, where one of the at least two pointers points to a next portion of the memory to be accessed, retrieving the portions of the datagram and the at least two pointers when the network device is ready to act on the datagram, polling a register to determine which of the at least two pointers actually points to the next portion, retrieving the next portion, when necessary and acting on the datagram based on the processing of the datagram by the network device.

Abstract: An Ethernet data switch maintains one or more queues for each of its ports in a shared memory. The memory is divided into data packets. When a data packet is received, the switch checks whether it can be stored efficiently in the packet buffers, and if the packet cannot be stored efficiently then a portion of the packet is stored in a separate memory and the remaining portion of the packet is stored in the packet buffers.