Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: Packets are accumulated in a packet transmission memory, and the data bits stored in each packets are serially output from the packet transmission memory, wherein an internal bit address signal is sequentially changed in the packet transmission memory so as to store the serial data bits in an addressable data storage region without any serial-to-parallel data conversion, and the data bits are serially output from a built-in parallel-to-serial data converter connected to the data storage regions, thereby making the circuit arrangement simple.

Abstract: A packet buffer management method and system are provided which enable maximum utilization of the hardware resources of the buffer memory, and which are optimum for the number of preset physical ports in use or for the number of service class (CoS) areas. In the buffer memory management method in a packet transmission/reception device, for storing a received packet in the buffer memory and controlling writing and reading of packets to and from the above buffer memory, the control methods are set in units of the service class contained in the header portion of received packets, and areas allocated to each service class in the buffer memory storing received packets are modified according to the set number of the above service classes.

Abstract: Multiple network switch modules have memory interfaces configured for transferring packet data to respective buffer memories. The memory interfaces are also configured for transfer among each other data units of data frames received from different network switch modules. A shared switching logic monitors (“snoops”) the data units as they are transferred between network switch modules, providing a centralized switching decision logic for multiple network switch modules. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads. A preferred embodiment includes a distributed memory interface in between the network switch modules and a shared memory system.

Abstract: An ATM interface device (SS) that is connected via a first data bus (SAR_DAT) to a first ATM device (SAR) controlling a data transfer and via a second data bus (ATM_TDAT, ATM_RDAT) to a second ATM device (MUX) [sic] controlled by a data transfer is provided for a data transmission. The ATM interface device (SS) comprises a control module (CC) and two FIFO memories (T_FIFO, R_FIFO) for intermediate storage of data to be communicated.

Abstract: An ATM interface device (SS) that is connected via a first data bus (SAR_DAT) to a first ATM device (SAR) implementing an access coordination of the first data bus (SAR_DAT) and that is connected via a second data bus (ATM_RDAT, ATM_TDAT) to a second ATM device (MUX) implementing an access coordination of the second data bus (ATM_RDAT, ATM_TDAT) is provided for a data transmission. The ATM interface device (SS) comprises a control module (CC) and two FIFO memories (R_FIFO, T_FIFO) for intermediate storage of data to be communicated.

Abstract: A diversity handover processing apparatus includes a shared buffer memory for storing signals input from a mobile station and converted into ATM cells, a combining/copy information table for storing connections necessary to one of a combining and a copy of the ATM cells received from the shared buffer memory, a combining/copy controller for reading information concerning connections in the combining/copy information table, a shared buffer memory handling section for designating addresses contained in the information read by the combining/copy controller, and a combining/copy processor for performing one of combining and copy of the ATM cells read out of the shared buffer memory in respect of the radio terminal.

Abstract: A system enables a cell of data to be transmitted one time over a high speed data bus to an Ethernet switch system where it is then distributed to each of the destinations for which it is intended. A first group of buffers is for temporarily storing data that is to be delivered to only one destination. A second group of buffers is for holding the cells that are to be transmitted to a plurality of devices. In the described embodiment of the invention, the unicast and multicast cells are transmitted over the same line or bus. The invention further includes a switch processor that is formed to detect congestion within the switch fabric and to transmit a congestion rating to each device coupled to transmit and receive data through the switch fabric.

Abstract: A queuing system (230) stores a package (246) derived from an ATM cell, the package including an internal interface header (IIH) and either an ATM cell payload or an AAL2 packet. The queuing system comprises a queue (312, 320) for storing the package, as well as a processor which executes plural functions. A time stamping function applies a time stamp upon storage of the package in the queue. The time stamping function can apply the time stamp to a package as replacement of the internal interface header. A time stamp checking function uses the time stamp to make a determination whether the tenure of the package in the queue is longer than permissible. The time stamp checking function can make the tenure determination in conjunction with a potential readout of the package from the queue. Alternatively, time stamp checking function can make the tenure determination when invoked by a queue monitoring function which monitors a fill level of the queue (e.g., when a queue fill level exceeds a threshold).

Abstract: To reduce the number of memory access cycles required to process each data element in a data networking device having one or more queues and a corresponding set of data link structures, the queue and data link structures are implemented on separate memories. Each queue is maintained using separate receive and transmit queue structures. Similarly, the data memory linked list is separated into a data queue link and a data stack link. Each of these four memories comprises its own address and data bus, and all four memories may be accessed simultaneously by a controller. In a general case, processing a complete data transmission event (i.e., a data element arrival and a data element departure) may be performed with a latency of at most three steps. In the first step, the transmit queue is read to obtain the old head pointer.

Abstract: A computer network switch includes a receiving module for receiving packets, a packet memory with a plurality of buffer cells with each of the buffer cells having a buffer descriptor. A descriptor free pool lists available buffer descriptors that can be used for new incoming packets. A plurality of transmit queues hold the buffer descriptors. Each of the transmit queues include an input queue, an expansion queue and an output queue. The switch also includes control logic for directing the removing of one of the available buffer descriptors from the free pool and directing one of the packets from the receiving module into one of the buff cells corresponding to the one available buffer descriptor. The control logic places the one buffer descriptor in the input queue of one of the transmit queues. The control logic also monitors a load status of the input and output queues.

Abstract: A switching system includes a multiport module having an address table for storing network addresses, and a host processor configured for selectively swapping the stored network addresses in the address table to an internal memory that serves as an overflow address table for the multiport switch module. The address table internal to the multiport module is configured for storing a prescribed number of network addresses for high-speed access, for example the most frequently-used network addresses. The host processor, configured for controlling the storage of network addresses between the address table and the external memory, uses the external memory as the overflow address table for storage of less frequently-used network addresses, for example addresses of network devices that transmit little more than periodic “keep-alive” frames. Hence, a large number of addresses may be managed by the switching system, without the necessity of an unusually large on-chip address table.

Abstract: According to some embodiments, configurable transmit and receive system interfaces are proved for a network device.

Abstract: By appropriate arrangement of two sets of tables chosen to be complementary, cells which are conveyed through a first multiplexor, n RAM storages and the second are subject to a cell rearrange-ment enabling introduction of at least one bitmap field, thereby producing the n Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage, one particular byte is stored into one RAM available for a Write operation by use of the first set of tables, thereby causing an alteration to the normal association between the n RAMs and the n Logical Units which is then re-established by the second set of tables.

Abstract: A compressed switch data storage for a network system is disclosed. The system includes a plurality of network channels to transfer data, and devices coupled to the plurality of network channels. The devices provide or receive data. The system also includes a switch. The switch has a memory for storing compress data, and a plurality of ports coupled to the plurality of network channels. The switch routes data from one port to another port according to a destination port address.

Abstract: UBR traffic control apparatus and methods can control UBR bandwidth according to cell traffic state and congestion occurrence at the switch terminal. Preferred embodiments can include an egress subscriber terminal that monitors congestion of cells at the switch terminal and traffic state to generate UBR bandwidth information, and an ingress subscriber terminal that outputs UBR cells to the switch terminal according to the generated UBR bandwidth information. Preferred embodiments can increase or maximize UBR traffic by flexibly increasing, decreasing or maintaining UBR bandwidth in consideration of the cells' congestion experience at the switch terminal, the egress subscriber terminal's buffer threshold value and traffic load. By managing cell traffic state for each transmitting subscriber board and by determining subscriber boards to be controlled in consideration of the traffic state at the time of UBR bandwidth's increase or decrease, the preferred embodiments may improve the quality of UBR service.

Abstract: Multi-level buffer system dynamically allocates storage for data units arriving at network gateway, and retrieves stored data units according to hierarchical schedule. Minimum and maximum thresholds associated with system resource and storage availability determine acceptance and storage of data units. Data units are accepted preferably if all threshold criteria are met. Threshold criteria may be determined from reserved minimum buffer length, calculated maximum buffer length, or random early discard-type algorithm applied separately to each buffer level. Optionally, buffer management applies to non-hierarchical storage systems.

Abstract: A method for reconstructing an aggregate stream of cells transmitted over communication links in an asynchronous transfer mode protocol includes determining a respective link delay for each of the communication links, including determining a fastest communication link. A common starting cell at which the cells from the communication links will correspond in time is determined based upon the fastest communication link. The method further includes filling a respective delay compensation buffer with corresponding cells for each of the communication links beginning with the common starting cell. The cells are read from the delay compensation buffers in a round-robin fashion to reconstruct the aggregate stream of cells.

Abstract: Memory interleaving is performed to increase bandwidth of a common memory in a non-blocking switch. The switch receives packets from a plurality of ingress ports, stores the packets in the common memory, and forwards the packets to a plurality of egress ports. The common memory is physically divided into two banks to provide two way interleaving. Two way interleaving is performed by reading a packet to be forwarded to an egress port from one bank concurrently with writing a packet received from an ingress port to the other bank. The common memory is physically divided into four banks to provide four way interleaving. Four way interleaving is performed by concurrently reading and writing two even banks or two odd banks. Bank balancing techniques are also provided to keep the banks of the common memory at the same level of occupancy.

Abstract: A network services processor receives, stores, and modifies incoming packets and transmits them to their intended destination. The network services processor stores packets as buffers in main and cache memory for manipulation and retrieval. A memory subsystem stores packets as linked lists of buffers. Each bank of memory includes a separate memory management controller for controlling accesses to the memory bank. The memory management controllers, a cache management unit, and free list manager shift the scheduling of read and write operations to maximize overall system throughput. For each packet, packet context registers are assigned, including a packet handle that points to the location in memory of the packet buffer. The contents of individual packets can be accessed through the use of encapsulation pointer registers that are directed towards particular offsets within a packet, such as the beginning of different protocol layers within the packet.

Abstract: A method and a transmission and reception device for data transmission in a distributed system is described, in which a central control unit transmits data simultaneously to all decentralized control units in a broadcast mode. The preferred field of application is a decentralized system for environment sensors in a motor vehicle.

Abstract: In general, in one aspect, the disclosure describes an apparatus capable of queuing and de-queuing data stored in a plurality of queues. The apparatus includes a status storage device to track status for each of the plurality of queues, a status cache to track status for a subset of the plurality of queues that are undergoing processing, and a queuing engine to queue incoming data and de-queue outgoing data. The queuing engine receives and updates the status for the subset of the plurality of queues from the status cache and receives and updates the status for remaining queues from the status storage device.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A direct memory access (DMA) circuit reduces the number of processor cycles involved in transmitting and receiving asynchronous transfer mode (ATM) cells. The circuit includes a read sequencer, a write sequencer, an ATM control block, a processor interface block, and a DMA arbitration and control block. The DMA arbitration and control block arbitrates between data transmissions on various subchannels. The ATM control block provides ATM functionality to the DMA circuit. The circuit may also respond to a trigger signal and may generate an interrupt signal. In this manner, the processing involved for DMA of ATM cells is improved.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: The present invention discloses a memory sharing mechanism based on priority elevation. In accordance with the present invention, there is provided an apparatus and method for transporting packets of data in a communication device, wherein each packet is assigned one of several priorities and received based on memory state information. The method comprises the steps of storing the received packets in a memory and modifying the assigned priority of any of the packets causing congestion within the memory.

Abstract: There is disclosed an QoS-oriented burstification method supporting various grades of burstification delay guarantee. For the arrival packets, the packets are sequentially inserted in a sequence of windows on weight basis, thereby forming a queue. The window size together with the weight of each flow determines a maximum number of packets of each flow in a window. For the departure packets, there is generated a burst consisting of a plurality of packets from the head of the queue when either a total number of packets reaches a maximum burst size or a burst assembly timer expires.

Abstract: Message cells that are allocated to virtual connections having different priorities are transmitted jointly over at least one transmission line of an ATM system working according to an asynchronous transfer mode. While being transmitted via the respective transmission lines, these message cells pass through a buffer memory individually allocated thereto. Given a buffer memory exhibiting a specific filling degree, one or more message cells from message cells of a selected virtual connection of low priority, which are, stored at the moment in the buffer memory, are discarded with the arrival of a message cell on the respective transmission line belonging to a virtual connection of relatively high priority, and dependent on the number of message cells stored for this virtual connection having low priority.

Abstract: The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. According to another aspect of the present invention, a system for handling transmission of network packets which are assembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.

Abstract: The present invention generally provides a memory device that is optimized for network packet switching. Multiple access ports permit multiple devices to concurrently access the memory in a non-blocking manner. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching. The memory system is expandable, with packet data being distributed across all memories in the system to prevent overloading of any one memory device. Further, the memory system includes input and output queue management functions using pointers that allow input data to be placed on output data queues without the data actually being copied into a new output queue.

Abstract: A method for monitoring traffic in a packet switched network. The packet switched network includes connections grouped in a single group; token buffers for respectively corresponding to the connections, and storing tokens generated at a predetermined token generation rate by the corresponding connection; a shared token pool for being shared among the connections, and storing the generated tokens therein when each token buffer of each connection is over a predetermined maximum size; and counters for respectively corresponding to the connections, and counting tokens stored in the shared token pool by a corresponding connection.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a plurality of ports. Each port is configured to compare a corresponding incoming data packet with at least one template. Each template has min terms specifying a corresponding prescribed value that is to be compared with a corresponding selected byte of the incoming data packet by the port. The network switch also includes a manager module configured to supply a next location field to the corresponding port. The corresponding port determines a next corresponding selected byte of the incoming data packet from the next location field for a next comparison with a next corresponding prescribed value in response to a next location field request.

Abstract: A termination device for connection to a group of TDM (time division multiplexed) trunks is capable of sending cells over one or more links either individually or as part of an inverse multiplexed group. The device includes a Utopia interface for receiving an incoming cell stream, a buffer for storing incoming cells at specific memory locations identified by pointers obtained from a queue of available pointers, a round robin scheduler for sequentially assigning cells to links forming an IMA group or individually in the UNI mode, and a pointer queue for each channel address, the pointer queue indicating the location of the next cell to be transmitted for each virtual channel. An adaptive shaper determines when a stuff cell is inserted and a per link output circuit places cells on the links, which can operate in CTC or ITC mode. The device can operate in mixed mode where up to four IMA and/or up to eight UNI channels can be supported concurrently. The links assigned to the IMA or UNI channels is programmable.

Abstract: A switching apparatus incorporated in a time division multiplying system has a read control memory for storing addresses indicative of parts of different messages to be transferred to different channels, and a read controller checks the read control memory so as to determine the memory areas of a message memory for selectively transferring the parts of different messages to the channels, thereby making the memory structure simple.

Abstract: A transmission system operable to store a plurality of transmission cells is disclosed. The transmission system comprises a first memory coupled to a plurality of signals and a first data bus. The transmission system also comprises a second memory coupled to the plurality of signals and a second data bus. The transmission system further comprises a controller coupled to the first memory device and the second memory device. The controller is operable to maintain a list comprising the available storage blocks in the first memory.

Abstract: The invention relates to a device for transferring data packets between two data networks comprising

Abstract: A packet buffer device and a packet assembling method in a packet transfer module to assemble logical channel-multiplexed asynchronous transfer mode (ATM) cells into packets and to store and output the cells in packet units. The packet buffer device includes a discrete buffer controller to generate a discrete buffer from a common buffer, a buffer type determination unit to determine a buffer type in which to store an ATM cell for each input ATM cell, and a packet buffer controller to assign the ATM cell to the common buffer or to the discrete buffer according to the buffer type. Thus, a common buffer and discrete buffers are dynamically constructed and buffers of respectively differing type can be used for packets of differing service mode. Further, optimal buffer resource usage can be achieved by using the buffer capacity of both a common buffer type and a discrete buffer type to store packets.

Abstract: The invention relates to a switching fabric arrangement for a packet-switched telecommunications network. Packets arriving at the switching fabric are assigned a time stamp depending on their time of arrival. Time stamp information relating to the packets to be transported is transmitted to at least some of the switching elements, and in at least some of the switching elements, the relative order of the packets to be sent is established on the basis of the received time stamp information in such a way that on each outgoing link (IL) from the switching element, the packets are in the sequence indicated by the time stamps.

Abstract: According to one embodiment, a system (900) includes a content addressable memory (CAM) address system (910) that receives voice packet data, and in response thereto, generates a channel number value (CHANNEL#). The CHANNEL# value can be used to generate a base address value for a voice packet buffer memory system (912). A base address value will correspond to a particular voice channel. The use of the CAM address system (910) can enable processing of voice data packets “on-the-fly,” allowing for rapid processing of voice data transmitted over a network structure and/or result in more efficient use of a buffer memory that stores voice data.

Abstract: A method and apparatus for synchronizing components operating isochronously that are coupled by independent links. The apparatus includes a synchronization circuit having a first and second buffer, each including an input port coupled to an external link, an output port, a read pointer and a write pointer. The read pointer indicates a next location in a respective buffer to be read in transferring data out on the output port. The write pointer indicates a next location in the respective buffer to be written when receiving data on the input port and is configured to automatically increment upon receipt of a first data bit on a respective external link. A trigger circuit is coupled to each link for receiving external trigger signals. Each external trigger signal is included along with data transmitted on the link and indicates when data is present on a respective link. A counter is coupled to the trigger circuit. The counter includes a trigger input and a predefined delay period.

Abstract: A system receives a multiplexed input signal having a plurality of channels for data. The system includes a finite state machine which performs a predetermined logic operation on data in each of the channels of the multiplexed input signal. A memory, coupled to the finite state machine, stores at least one context of the finite state machine for each of the channels of the multiplexed input signal.

Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The memory management unit transfers the network data between the transmit and receive state machines and the respective buffers based on prescribed interface protocol signals between the memory management unit and the transmit and receive state machines.

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells;

Abstract: An apparatus and method are disclosed for maintaining free buffer information for a network switch. A first Random Access Memory (RAM), located on the network switch, functions to store values that indicate whether or not free buffers, located in a second RAM, are available for storing received data frames. An input logic is provided for placing values in the first RAM to indicate which free buffers are available for storing the data frames. When free buffers are required to store data frames, the output logic searches the first RAM and locates values that indicate available free buffers in the second RAM. The output logic then generates buffer pointers that address the locations of the free buffers in the second RAM. The buffer pointers that are generated are stored in a small capacity queue on the network switch to provide immediate availability to free buffers.

Abstract: A First-In-First-Out (FIFO) memory device includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.

Abstract: An ATM switching node has an ATM switch (30) to which at least one inter-node physical link (56) is connected. In addition, a cell handling unit (32) connected to the ATM switch has a centralized queuing resource (230) which queues ATM cells which are to be routed through the ATM switch for transmission from the node on the physical link. ATM cells destined for the physical link from the queuing resource are discharged from the queuing resource in accordance with a parameter of the physical link. The parameter is preferably the capacity (e.g., transmission rate) of the physical link. In the illustrated embodiment, the node is one of the following nodes of a cellular telecommunications network: a base station (42); a base station controller (44); a mobile switching center (46).

Abstract: Disclosed is a cell interleaving method in an ATM switching system which is capable of reducing cell loss and transmission delay suffered in a conventional cell interleaving method.

Abstract: A network switch configured for switching data packets across multiple ports uses an external memory to store data frames. When a data frame is transmitted to the external memory, a frame header portion of the data frame is stored on the switch for processing by decision making logic. The switch memory is configured to store a number of the frame headers corresponding to each port on the switch along with frame pointer information indicating the location in the external memory where the data frame is stored.

Abstract: A communication system (300) comprises interfaces (311-314) at communication channels (361-364, respectively), coupled to a controller (340) by an address bus (320) and multiplexer (380). The interfaces (311-314) receive data cells and provide status signals (e.g., clav) indicating, for example, cell availability, independently from interface addresses (ADDR) being present at the address bus (320). The interfaces (311-314) continuously send the status signals to the multiplexer (380) which receives the interface address (ADDR) at a control input (386) and forwards the status information of the currently addressed interface to the controller (340).

Abstract: In an ATM (Asynchronous Transfer Mode) switch circuit, use efficiencies of address storage memories are increased even when a total number of output ports is increased. The ATM switch circuit is arranged by an ATM cell buffer memory, an ATM cell managing unit, an address storage memory, an empty address managing unit, and also a buffer address managing unit. In this ATM switch circuit, the address storage memory may be commonly used with respect to the output ports. As a result, since the length of the address chain corresponding to the output ports may be adjusted in accordance with the use frequencies of the output ports, the address storage memory can be effectively used, depending upon a plurality of output ports.