Abstract: Provided is a method for transferring data among a logical layer, physical layer, and storage device. The logical layer allocates a buffer to use to write data to a storage device. The physical layer manages access to the storage device. The logical layer determines an offset into the buffer based on a length of a physical header written by the physical layer and writes data to the buffer from the determined offset. The physical layer writes physical header information, wherein the physical header information does not extend past the offset in the buffer. The physical layer transfers content from the buffer to the storage device.

Abstract: A method and apparatus for determining a read address for received data in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise determining a minimum write address using a plurality of memory elements and using the minimum write address in connection with received read addresses to determine group read addresses.

Abstract: A method for processing a plurality of packets that includes receiving the plurality of packets from a network, analyzing each of the plurality of packets by a classifier to determine to which of a plurality of temporary data structures each of the plurality of packet is to be forwarded, forwarding each of the plurality of packets to one of the plurality of temporary data structures as determined by the classifier, forwarding a plurality of packets from the one of the plurality of temporary data structures to a virtual serialization queue associated with the one of the plurality of temporary data structures, wherein the virtual serialization queue is bound to a thread having a processing priority, and processing the plurality of packets on the virtual serialization queue using at least one processor bound to the virtual serialization queue and the processing priority.

Abstract: The present invention provides a cell disassembly unit which accurately reproduces the position of data on a time axis when ATM cells are converted into STM signals even if cell loss occurs in an ATM network. A cell loss detection circuit disassembles the ATM cells into bytes, sends them to the memory, and detects the number of lost bytes M of the ATM cells. A sequence number generation circuit generates the sequence number N, which is N=N+1 if there is no loss, and N=N+M if there is loss, in the sequence of the transmission of bytes from the cell loss detection circuit. A write address generation circuit generates a write address, and a read address generation circuit generates a read address. A selector sends either the bytes read from the memory or dummy data generated by the dummy data generation circuit to the outside as STM signals.

Abstract: A ring buffer is provided in the data holding section A3 of a data processing section 100A. A master-slave relationship between a plurality of data processing sections 100A, 100B is set. A data output synchronizing signal of the data processing section 100A acting as a master is supplied to the data processing section 100B acting as a slave. This makes it possible to synchronize the output data of the individual data processing sections, while suppressing the memory cost. Input connection terminals (A1) take in object data, an object data enable signal (INHDEN) from the outside, and an object read clock (IMCLK) from the outside. A data holding section (A3) stores object data on the basis of an internal clock. A synchronizing circuit (A4) reads the stored object data on the basis of INHDEN and IMCLK. An output connection terminal (A2) outputs output object data, INHDEN, and an internal clock equivalent to IMCLK to the outside.

Abstract: A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.

Abstract: A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.

Abstract: An apparatus for transitioning data contained on multiple memory storage devices, such as optical disks and memory cards, efficiently onto a data network by utilizing data bridges between the memory devices and the target network.

Abstract: Systems and methods for monitoring high-speed network traffic via sequentially multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module configured to be coupled to a first, server chassis, a first data port disposed on the first switch module and a set of first port data links configured to be coupled to a set of data port data links, each data link configurable to channel at least one of a normal data stream and a monitored data stream.

Abstract: A cell switching method and system are disclosed that divide an input ATM cell into ATM adaptation layer (AAL) 2-type common part sublayer (CPS) packets. The divided CPS packets are stored in different first storage areas, in accordance with virtual paths/virtual channels (VPs/VCs) of the respective CPS packets, and identifiers of the first storage areas are also stored. The stored CPS packets are read in the order of the stored first identifiers. Thereafter, the read CPS packets are stored in second storage areas, in accordance with respective CIDs, and second identifiers of the second storage areas are stored. The CPS packets stored in the second storage areas are read in the order of the stored second identifiers and multiplexed to generate ATM cells.

Abstract: A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.

Abstract: An apparatus receives packets from a network and inserts the packet data into the memory of a computer system. The invention reduces the amount of computer system memory bandwidth required to receive packets through the use of a retained data buffer. Packet headers and a summary of packet validation results are processed by network stacks within the computer system to identify the intended memory buffer in which the packet payload is to be placed. Packet payload data is directly placed from the retained data buffer to the intended memory buffer without the use of intermediate buffers. A preferred embodiment includes a data retention network interface card (DRNIC) which includes the required data retention buffer for use in direct placement of received data.

Abstract: A data transferring unit performs hit determination on a cache memory based on a management table and a request from a CPU board. If requested data is not available in the cache memory, the data transferring unit reads and sequentially transfers the requested data from a shared memory in packets of optimum packet length stored in a time table in such a way that the previous packet is transferred while the next packet is read. In addition, the data transferring unit measures a packet transfer time. A packet-length optimizing unit varies, based on the packet transfer time calculated by the data transferring unit and data stored in the time table, an optimum packet length so that the difference between the packet transfer time and a packet read time is minimized.

Abstract: A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is stored in a second memory space in the lookup table, while access is provided to the first set of routes stored in a first memory space in the lookup table. Access is provided to the first memory space through a first pointer stored in a subtree entry. After storing the second set of routes in the second memory space, access is switched to the first set of routes in the first memory space by replacing the first pointer stored in the subtree entry with a second pointer to the second memory space.

Abstract: A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.

Abstract: A system and method for using a single shared buffer to service multiple destinations for a telecommunications switch is disclosed. Upon receiving a cell of data to be sent to a destination, an interface stores the cell in a shared buffer. The address of the cell in the buffer is stored in a queue array. The address of the buffer address in the queue array is stored in a head array and a tail array. A threshold register tracks the global threshold for the total number of cells in the shared buffer and a destination threshold for each destination. The buffer can broadcast a data cell to a single location or send the same cell to multiple locations.

Abstract: Methods, apparatuses and systems for populating a data structure. The data structure may be established in a memory unit and may have a total number of N slots for entries. In this case, N is defined as an integer representing the total number of slots in the data structure, and N is further expressible as a power of two with an integer exponent x. Entries may then be stored into L slots of the data structure, with L being defined as an integer representing a number of slots that contain entries. To produce an index value, x bits of a binary representation of L may be swapped. A new data entry is then stored into an entry of the data structure represented by the index value.

Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to receive data from the at least one data port interface, determine if the data is to be stored in one of the first memory or the second memory, store the data in one of the first memory or the second memory as a linked list, retrieve the data from one of the first memory or the second memory, and forwards the data for egress.

Abstract: A digital signal-processing device is described which comprises a recording controller for control of recording in the memories drives a trigger-switching element arranged in the trigger line downstream of the two parallel-operating signal-processing units in such a manner that essentially the same timing period is recorded in both memories during a post-triggering period after a trigger time.

Abstract: In a method and arrangement for loading data from a transmission device into a non-volatile memory of a receiver device that can be connected with the transmission device, the non-volatile memory being erased only sector-by-sector, the data to be loaded are divided by the transmission device into a number of data packets and at least one part of the data packets is loaded into the memory in a load step. A check step that is implemented before the current load step in which a current load state of the memory is checked, the current load state indicating whether at least a part of the data packets has already been successfully loaded into the memory in a preceding load step. The data packets to be loaded into the memory in the current load step are determined dependent on the current load state.

Abstract: Various methods and apparatus are disclosed for reading or writing randomly accessible portions of a packet of data.

Abstract: An MFI synchronization manager determines the continuity of MFI values to manage the synchronization of the MFI values. A phase adjuster detects a reference VC-3 channel of VC-3 channels which make up a virtual concatenation based on detected MFI values. A write controller writes frame data into a phase adjustment memory based on a write permission signal from the phase adjuster and data valid/invalid information. A write frame manager manages the frame data written in the phase adjustment memory with respect to each of the VC-3 channels and generates a read permission signal for the frame data whose all VC-3 channels of the concatenation have been written. A read controller reads the frame data from phase adjustment memory according to the read permission signal.

Abstract: A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to receive data from the at least one data port interface, determine if the data is to be stored in one of the first memory or the second memory, store the data in one of the first memory or the second memory as a linked list, retrieve the data from one of the first memory or the second memory, and forwards the data for egress.

Abstract: A communication device configured to assign a data packet to a memory bank of a memory device is provided. The communication device includes an input port for receiving the data packet, a look-ahead logic module, a pointer assignment module, and an output port. The look-ahead logic module is configured to select an address of the memory bank of the memory device by overriding an address mapping scheme that permits successive data packets to be assigned to the same memory bank. The pointer assignment module is configured to assign a pointer to the data packet based upon the memory bank determined by the look-ahead logic module. In addition, the output port is configured to transfer the data packet to the memory bank of the memory device.

Abstract: A method for coalescing acknowledge packets within a server is disclosed. A Read Request queue having multiple queue pair entries is provided. Each of the queue pair entries includes a packet sequence number (PSN) field and an indicator field. In response to a receipt of a Write Request packet, an indicator field of a queue pair entry is set to indicate that an Ack packet has been queued within the queue pair entry, and a PSN of the Write Request packet is written into a PSN field of the queue pair entry. In addition, a Queue Write Pointer is maintained to point to the queue pair entry. In response to a receipt of a Read Request packet, the indicator field of the queue pair entry is set to indicate that a Read Request packet has been queued within the queue pair entry, and a PSN of the Read Request packet is written into the PSN field of the queue pair entry. Also, the Queue Write Pointer is advanced to point to a queue pair entry that is subsequent to the queue pair entry.

Abstract: A method for handling data between a clock and data recovery system CDR and a data processing unit DP of a telecommunications network node TNN of an asynchronous communications network, using a bit rate adaptation circuit BAS, the bit rate adaptation system BAS including a memory unit MEM with a write process circuit Wp controlled by the recovered clock Rclk and a read process circuit Rp controlled by the local clock Lclk where the bit rate adaptation system BAS also includes a pointer synchronization controller PSC which, depending on the data detected on the input data signal DIb1 of the bit rate adaptation system BAS, sets the read and write pointers to a fixed initial address value. A Clock and Data Recovery system and a telecommunications network node TNN of an asynchronous network, which include a bit adaptation circuit BAS according to the invention, are also disclosed.

Abstract: A data switching circuit (10). The data switching circuit comprises at least one input (10in) for receiving during a same time period a plurality of data streams (ICH0-ICH127). Each of the data streams comprises a plurality of like-sized data quantities. The data switching circuit further comprises a plurality of addressable memories (10x), wherein each of the plurality of addressable memories comprises a plurality of memory cells. The data switching circuit further comprises circuitry (11) for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time. Lastly, the data switching circuit further comprises reading circuitry (13, 14), coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities to output channels.

Abstract: A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location.

Abstract: A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first, second and third internal memory communicating with the first, second and third data port interface. A first and second memory management unit for communicating data and to control access to and from the second internal memory, are also provided. A communication channel is provided for communicating data and messaging information.

Abstract: In order to provide an ATM cell/packet switch which can easily maintain the band for the normality confirmation packet of the user data transfer path without influencing the user band at a state of in-band, and a communication control method using the switch, at least provided in the switch are: an SDRAM for storing the user data; a normality confirmation packet generator; a timing generator for generating the timing of a refresh cycle of the SDRAM; a selector for transferring the normality confirmation packet at the time of the refresh; and a packet reception unit for extracting the packet identifying information from the received packet data, and comparing the normality confirmation packet directly received from the packet generator to the normality confirmation packet received via the switch unit thereby to confirm the normality when the packet data is the normality confirmation packet.

Abstract: There is disclosed an QoS-oriented burstification method supporting various grades of burstification delay guarantee. For the arrival packets, the packets are sequentially inserted in a sequence of windows on weight basis, thereby forming a queue. The window size together with the weight of each flow determines a maximum number of packets of each flow in a window. For the departure packets, there is generated a burst consisting of a plurality of packets from the head of the queue when either a total number of packets reaches a maximum burst size or a burst assembly timer expires.

Abstract: A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.

Abstract: Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch.

Abstract: A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.

Abstract: To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnection, the data caching control units are divided into plural control clusters, each of the control clusters including at least two or more data caching control units, control of a cache memory is conducted independently for each of the control clusters, and one of the plural data caching control units manages, as a single system, protocol transformation units and the plural control clusters based on management information stored in a system management information memory unit.

Abstract: Mechanisms for reducing the number of block masks required for programming multiple access control lists in an associative memory are disclosed. A combined ordering of masks corresponding to multiple access control lists (ACLs) is typically identified, with the multiple ACLs including n ACLs. An n-dimensional array is generated, wherein each axis of the n-dimensional array corresponds to masks in their requisite order of a different one of the multiple ACLs. The n-dimensional array progressively identifies numbers of different masks required for subset orderings of masks required for subsets of the multiple ACLs. The n-dimensional array is traversed to identify a sequence of masks corresponding to a single ordering of masks including masks required for each of the multiple ACLs.

Abstract: The invention relates to a method and an apparatus for receiving and transmitting asynchronous transfer mode (ATM) cell streams over a bus. The invention provides a method for receiving ATM cells in a host from a client over a bus, comprising the steps of determining whether an ATM cell in a first storage device within the client is ready to be transferred over the bus to a second storage device within the host, preventing overflow of the second storage device by calculating a first available cell space in the second storage device as a function of a write value, a read value image and a size value of the second storage device, and transferring an ATM cell from the first storage device to the second storage device.

Abstract: A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Abstract: A method of the grooming traffic signals through a composite switch is disclosed that enables a traffic signal that is being transmitted between any two constituent switches to be re-routed through the composite switch without a hit (i.e., the dropping, replacing, inserting, or repeating of at least one bit in the traffic signal). This applies whether the constituent switches are adjacent in the composite switch or not. The composite switch in accordance with the illustrative embodiment comprises multiple routes between adjacent constituent switches and incorporates a mechanism that compensates for differential propagation delays along the routes. And still furthermore, the composite switch in accordance with the illustrative embodiment comprises alternative routes through different constituent switches and incorporates a mechanism that compensates for differential propagation delays through the constituent switches.

Abstract: The present invention is directed to synchronizing notification messages transmitted to egress control units to allow an even distribution of the messages. A plurality of packet buffer units (PBUs) may concurrently transmit notification messages to a particular egress control unit in response to packets received from a plurality of ingress control units. Each PBU includes a notification queue associated with the egress control unit for storing notifications generated by the PBU. Notifications in the notification queues are ordered according to the ingress units triggering the notifications. Notifications in each notification queue are retrieved via a time-driven pointer that is initialized to a different start entry position for the notification queues in each PBU. This allows each PBU to transmit, at any given time, notifications to the egress control unit that are associated with a different ingress unit.

Abstract: A network switch port receives, stores and then forwards incoming cells. The network switch assigns each incoming cell to one of a set of flow queues, each of which is allotted a portion of space in a cell memory. The switch port periodically computes a average of the number of cells assigned to each flow queue stored in the cell memory during a preceding period, and assigns a discard weight to each incoming cell that is a function of the amount by which the average for the cell's assigned flow queue exceeds a threshold level. The switch port randomly discards incoming cells assigned to the flow queue with a probability that increases with the incoming cells' assigned weights. The switch port stores incoming cells that are not randomly discarded in the cell memory and later forewords them from the cell memory.

Abstract: One embodiment of a method for switching ATM cells using Early Packet Discard and Partial Packet Discard is provided. Initially, a first cell of an AAL5 packet is received at an input port. Next, it is determined whether there is likely to be enough buffering available to handle the whole packet (i.e., up to 64 Kbytes). If it is determined that sufficient buffering is unlikely to be available, the entire packet is discarded. If it is determined that sufficient buffering exists, the cell is received and buffered for subsequent transmission. Next it is determined whether the flow's buffer is filled at any time after initial transmission of a AAL5 cell but before reception of the final cell. If such a state is determined, the current cell is discarded and a flag is set in the flow structure so that subsequent cells of the same packet, except the last, will also be discarded.

Abstract: A method and an apparatus to efficiently handle read completions that satisfy a read request are presented. The apparatus comprises a first port to receive data that partially satisfies a read request, a second port, wherein the data is forwarded via the second port if the second port is idle, a buffer to store the data if the second port is busy, and a combiner to combine the stored data with additional data that partially satisfies the read request as the additional data is received via the first port, wherein the second port forwards the combined data when the second port is not busy.

Abstract: There is disclosed herein a multi-port frequency step-down queue that efficiently transfers data from a fast clock domain to a slow-clock domain having parallel hardware resources. In one embodiment, the queue includes a set of registers that are sequentially selected by an input counter that receives the fast clock. As the registers are selected, they store a data item from the input data stream. The queue also includes multiple multiplexers each having inputs that are sequentially selected by an output counter that receives the slow clock. The first multiplexer is coupled to the first N registers in the queue, the second multiplexer is coupled to the second N registers in the queue, etc. In this manner, the step-down queue generates multiple output FIFO data streams at the slower clock rate. Each of the output data streams may then be processed in parallel.

Abstract: An apparatus and method for recovering abnormal control cells in an asynchronous transfer mode (ATM) exchange subscriber unit. A signal cell or control cell is transmitted and a plurality of reception first-in first-out memories (FIFOs) are sequentially checked to determine whether a new cell has arrived. If there is no start of cell (SOC) signal in an initial byte of a current cell under the condition that a cell synchronization loss signal is present in the current cell, or if the SOC signal is detected during transfer of the current cell, the current cell is determined to be abnormal. If the cell synchronization loss signal is abnormal, the current cell is discarded and an associated FIFO is fully emptied to recover cell synchronization.

Abstract: A switch and a process of operating a switch are described where a received data frame is stored into memory in a systematic way. In other words, a location is selected in the memory to store the received data frame using a non-random method. By storing the received data frame in this way, switches that employ this system and method increase bandwidth by avoiding delays incurred in randomly guessing at vacant spaces in the memory. The received data frame is stored until a port that is to transmit the received data frame is available. Throughput is further improved by allowing the received data frames to be stored in either contiguous or non-contiguous memory locations.

Abstract: Broadly speaking, an apparatus for efficiently utilizing a shared packet buffer memory in a switch and a method for operating the same is provided. More specifically, the apparatus includes a memory having a number of buffers configured to be operated in a ratcheted manner. The ratcheted manner in which the memory is operated causes each incoming data stream to be distributed across the number of buffers. Each stored data stream can also be retrieved from the number of buffers for output from the memory in a similar ratcheted manner. The memory uses a rotating selector to control the ratcheted manner of operation. Also, the memory is capable of simultaneously servicing each of a number of inputs and a number of outputs to which the memory is connected.

Abstract: A constant bit rate single program encoded transport stream is demultiplexed from a statistically multiplexed MPEG transport stream by separating a variable bit rate program from the multiplexed MPEG transport stream, loading the sequence of pictures that form the variable bit rate program into a smoothing buffer at a rate that does not exceed a desired constant bit rate and transferring the picture from the smoothing buffer at times indicated by decode time stamps associated with the pictures respectively. If a picture of the sequence becomes available no later than a specified amount of time prior to the picture's decode time stamp, then that picture is loaded into the smoothing buffer commencing the specified amount of time prior to the time indicated by the picture's decode time stamp. If a picture of the sequence becomes available later than the specified amount of time prior to the picture's decode time stamp, then that picture is loaded into the smoothing buffer as soon as possible.