Abstract: The invention relates to a time-alignment apparatus and a time-alignment method of a transmitter (TX) of a telecommunication system TELE. Successive data frames (ch1/0, ch2/0, ch3/0, ch4/0, ch8/0, ch300/0) are written to one or two frame memories (RAM1, RAM2) starting at a respective frame start write address (FRST-ADRchy). A third frame memory (RAM3) having a read state is read out in the column direction such that one data symbol of each storage resource (RES1, RES2 . . . RES300) can be output to a modulator unit (BBTX) of the transmitter (TX). The read/write state (WR/RD) of the three frame memories (RAM1, RAM2, RAM3) is cyclically switched through a first to third alignment mode (M1, M2, M3) such that always a first write state memory (RAM1) and a second write state memory (RAM2) are provided. An interleaving process can be carried out together with the time-offset adjustment if the storage resource is constituted by an interleaving matrix.

Abstract: To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units (10) and data caching control units (21) are connected to each other through an interconnection (31), the data caching control units (21) are divided into plural control clusters (70), each of the control clusters including at least two or more data caching control units (21), control of a cache memory (111) is conducted independently for each of the control clusters (70), and one of the plural data caching control units (21) manages, as a single system, protocol transformation units (10) and the plural control clusters (70) based on management information stored in a system management information memory unit (160).

Abstract: A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

Abstract: A method for determining parameters needed to communicate with a remote node in a computer network is provided. The invention comprises determining the location of the remote node to which an InfiniBand (IB) node might desire to communicate. This resolution comprises determining the location of the remote node based on a desired application or service, and then determining the IB parameters needed to communicate with the remote node. The resolution might also involve determining the specific queue pairs that associated with the service dynamically. The general solution is applied to IP service resolution.

Abstract: The present invention provides a cell disassembly unit which accurately reproduces the position of data on a time axis when ATM cells are converted into STM signals even if cell loss occurs in an ATM network. A cell loss detection circuit disassembles the ATM cells into bytes, sends them to the memory, and detects the number of lost bytes M of the ATM cells. A sequence number generation circuit generates the sequence number N, which is N=N+1 if there is no loss, and N=N+M if there is loss, in the sequence of the transmission of bytes from the cell loss detection circuit. A write address generation circuit generates a write address, and a read address generation circuit generates a read address. A selector sends either the bytes read from the memory or dummy data generated by the dummy data generation circuit to the outside as STM signals.

Abstract: A random access memory architecture and method of handling data packets is described. According to embodiments of the invention, an apparatus includes a first processing unit for receiving serial data input, a switch, and a plurality of serially connected random access memory devices. The random access memory devices transmit data packets and commands via write input ports, write output ports, read input ports, and read output ports. A method for routing data includes receiving serial data input in a first processing unit, generating a data packet based on the serial data input, transmitting the data packet to a first random access memory device via a write input port, decoding the data packet, determining whether to perform a command in the first random access memory device based on information in the data packet, and transmitting the data packet to a second random access memory device.

Abstract: An apparatus and a method for controlling memory in a base station modem supporting multi-users including a memory divided into logical blocks for supporting the multi-users, and a controller for allocating the memory blocks dynamically in hardware. This allows non-continuous memory allocation and the size of memory can be increased or reduced during operation through the dynamic allocation structure of the memory.

Abstract: A content addressable memory includes a priority encoder that is in communication with an array of the content addressable memory cells to receive match signals, and from the match signals generating an output index signal in accordance with a priority sequence of the match signals. The priority encoder has a plurality of input circuits to receive the match signals from the CAM array. A priority setting circuit receives a priority transformation signal indicating a priority index for modification of the priority sequence. An encoding circuit is in communication with the plurality of input circuits and the priority setting circuit for generating the output index signal in accordance with the priority sequence. The priority encoder circuit further includes an enabling circuit for receiving an enabling signal.

Abstract: An input port for a network switch includes a cell buffer for receiving incoming unicast and multicast cells and for writing each cell into an internal cell memory. The cell buffer thereafter forwards each unicast cell from the cell memory to one network switch output port and forwards a separate copy of each multicast cell to each of several network switch output ports. When the cell buffer writes a unicast cell to the cell memory, it sends a pointer to the storage location of the unicast cell to a queue manager. When the cell buffer writes a multicast cell to the cell memory, it sends several pointers to the queue manager, one for each output port that is to receive a copy of the multicast cell, with each pointer pointing not to the multicast cell's storage location but to an empty storage location in the cell memory. The cell buffer also maintains a database relating each pointer it sent to the queue manager to an actual storage location of a unicast or multicast cell.

Abstract: A cell disposal avoidance system is provided that can avoid disposal of the cells resided in the QoS buffer when a traffic of a specific QoS class in an ATM switch increases. The ATM switch includes a storage cell number monitor, a software data section 813, and a software controller 812. The storage cell number monitor monitors congestion of plural QoS buffers in the buffer 3, 5. The software data section 813 stores a cell reading priority (WRR value) attached for each QoS buffer. The software controller 812 dynamically changes the WRR value when congestion of a QoS buffer is in a congestion state (at generation of cell disposal or buffer congestion alarm) and increases the WRR value of the QoS buffer in a cell disposal state. Cells are divided in a time division mode according to the weight of the WRR value and read in a round format from the QoS buffer. The ATM switch resets the WRR value to an initial value when the congestion of the QoS buffer ceases.

Abstract: A communication control apparatus which effectively uses a memory and does not need complicated hardware is realized. Each area of a frame assembly memory 2 is set to the maximum frame length which is handled. When a cell of a new connection is inputted, a memory write control unit (1) allocates the connection to an empty area in the memory (2) and writes the cell therein. When the cell of the same connection as that already allocated to any area is inputted, it is written into the allocated area. If a plurality of cells of one frame have already been written in the area of the same connection, the connection is allocated to another new area and the cell is written therein. A memory read control unit (3) reads out the cells of one frame and outputs them as one completed-frame data.

Abstract: A method and apparatus for accessing a non-symmetric dual-slot address table having two entries 0, 1 that are different in size. When writing data, the data is hashed to generate a hash value. Then, the data is written to a slot corresponding to the hash value in the entry 0. When there was data in the slot 0, the hash value is mapped to a sub-address and a share value, and then a slot 1 corresponding to the sub-address is selected from the entry 1. Afterwards, the SMAC tag, the share value and the source port are written to the slot 1. In addition, when transmitting the packet, a hash value is generated according to the DMAC address. Then, a SMAC tag, the share value and the source port are read according to the hash value. After compared, the packet is transmitted.

Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

Abstract: An input or output switch port for a network switch converts each incoming packet into a cell sequence stores each cell in a cell memory. The switch port includes a traffic manager for queuing cells for departure from the cell memory and then signaling the cell memory to read out and forward cells in the order they are queued. The traffic manager selectively queues cells for departure on either a cell-by-cell or sequence-by-sequence basis. When cells are queued for departure on a cell-by-cell basis, cells of two or more sequences may be alternately read out and forwarded from the cell memory. Thus cells of different sequences may be interleaved with one another as they depart the cell memory. When a cell sequence is queued on a sequence-by-sequence basis all of its cells are read out of the cell memory and forwarded as a contiguous sequence and are not interleaved with cells of other sequences of the same departure queue.

Abstract: A logic system for resolving port contentions associated with memory-access requests in data packet routing is provided. The logic system comprises a determination logic for assessing and reporting port status of busy or not busy, a command mechanism for issuing commands contingent on determination results and a staged buffer memory for holding pending requests waiting for permission to access the memory. A single request at the head of the buffer memory is considered for port access whereupon if a port is determined to be busy, the command logic issues appropriate commands to units responsible for downloading packets from the memory and for sending new memory-access requests.

Abstract: The present invention includes a detection unit for detecting an active virtual channel of arriving ATM cells, and a management memory unit for managing management information about the detected active virtual channel on a virtual-channel-to-virtual-channel basis, wherein a frame-by-frame process is performed on cells whose virtual channel identifier matches that of an active virtual channel managed by the management memory unit. In this manner, virtual-channel-by-virtual-channel processing is achieved in ATM leased line services that are provided on a virtual-path-by-virtual-path basis, thereby dispensing with needs to register a virtual channel into management memory in advance and allowing a large number of virtual channels to be accommodated.

Abstract: A ternary content addressable memory device. The device includes a ternary CAM array segmented into a plurality of array groups, each of which includes a number of rows of ternary CAM cells. Each array group is assigned to a particular priority by storing the priority number for each array group in an associated storage element. Data entries are then stored in array groups according to priority.

Abstract: A network interface device includes receive logic, which is coupled to receive from a network a sequence of data packets, each packet including respective header data. A protocol processor is coupled to read and process the header data so as to identify a group of the received packets that contain respective fragments of a data frame, the fragments having a fragment order within the data frame. Host interface logic is coupled to a host memory accessible by a host processor, and is controlled by the protocol processor so as to allocate space for the data frame in the host memory, and to reassemble the fragments of the data frame in the fragment order in the space allocated in the host memory.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

Abstract: A multicasting system and method for use in a shared memory-based switch that includes an input subqueue reading block for reading out data inputted thereto, selecting one bit from an output port bitmap at a time and outputting output port information of one bit and class information as a data stream together with an enable signal.

Abstract: A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONET output signal path associated with a respective second time slot. Each input signal path includes a pointer interpreter, and each output signal path includes a FIFO buffer serially coupled to a pointer generator. The architecture further includes a synchronization buffer in each input signal path for transferring the input signal to the clock rate of the time slot interchanger. The architecture permits greater levels of integration when the time slot interchanger has more inputs than outputs, and/or the time slot interchanger provides the output signal to a pointer processor to transfer the output signal to the clock rate of the output signal path.

Abstract: A control unit, ATM cell and process for writing data into registers of at least one device comprising a management interface or for reading values from registers of such devices, wherein communication between at least one management unit which generates the data to be written or which undertakes further processing of read-out data and the control units via an ATM inband protocol occurs so as to provide an option to inexpensively read or write data. The control units, which have access to the registers of at least one of the devices by way of the management unit, with instructions and information for specific devices connected to the respective control unit, are integrated into the payload of the ATM cells. The control units implement the instructions and, if applicable, transmit a response ATM cell back to the management unit.

Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.

Abstract: In a system, device, and method for controlling access to a memory, a memory interface device is used to coordinate access to a memory device by a number of host applications. The memory interface device is situated between the number of host applications and the memory device. The memory interface device received memory access requests from the number of host applications, interacts with the memory device for servicing the memory access requests, and provides result/status information to the number of host applications. The memory interface device maintains a separate context for each memory access request in order to correlate each memory access request with the host application that issued the memory access request and the result/status information generated for the memory access request.

Abstract: The present invention is directed to buffer arrangements (e.g., via concatenation) to support differential link distances at full bandwidth.

Abstract: The present invention provides a unitary mechanism for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM module (101) for convergence of the telecommunications traffic includes an ATM processor (120) configured to perform QoS, OAM processing and switching in an ATM system. Function modules (102,104,105) and data ports (106,108) are configurable to transceive data, voice and video traffic in which the traffic is packetized in ATM data cells.

Abstract: A cell disposal avoidance system is provided that can avoid disposal of cells resided in the QoS buffer when a traffic of a specified QoS class in an ATM switch increases. The ATM switch includes a storage cell number monitor, a software data section 813, and a software controller 812. The storage cell number monitor monitors congestion of plural QoS buffers in the buffer 3, 5. The software data section 813 stores a cell reading priority (WRR value) attached for each QoS buffer. The software controller 812 dynamically changes the WRR value when congestion of a QoS buffer is in a congestion state (at generation of cell disposal or buffer congestion alarm) and increases the WRR value of the QoS buffer in a cell disposal state. Cells are divided in a time division mode according to the weight of the WRR value and read in a round format from the QoS buffer. The ATM switch resets the WRR value to an initial value when the congestion of the QoS buffer ceases.

Abstract: A packet switch includes an input buffer memory unit having a logic queue corresponding to an output line, a control module for a first pointer indicating a scheduling start input line, a control module for a second pointer indicating a scheduling start output line of scheduling target outlines, a request management control module for retaining transmission request data about a desired output line, a scheduling processing module for starting a retrieval from within plural pieces of transmission request data from the output line indicated by the second pointer, and selecting an output line that is not ensured by other input lines, a packet buffer memory unit for temporarily storing a plurality of fixed-length packets and sequentially outputting the fixed-length packets, a switch unit for switching the fixed-length packets outputted from the packet buffer memory unit, and an address management unit for segmenting an address of the packet buffer memory unit into fixed-length blocks for a plurality of packets, an

Abstract: The present apparatus and method of use comprises a system that enables a cell of data to be transmitted one time over a high speed data bus to an switch system where it is then distributed to each of the destinations for which it is intended. A fabric access device and a multiplex devices are each formed to have groups of buffers for buffering signals according to type. The first group of buffers is for temporarily storing data that is to be delivered to only one destination. The second group of buffers is for holding the cells that are to be transmitted to a plurality of devices. In those embodiments in which the unicast and multicast cells are transmitted over the same line or bus a parsing unit examines a field within the header portion of each cell to determine whether the cell is a unicast or multicast cell. If the cell is a unicast cell, it is temporarily stored within the unicast receive buffer set. If the cell is a multicast cell, then it is temporarily stored in the multicast buffer set.

Abstract: A system and method for processing control cells to prevent event missequencing and data loss are described. At least one control unit is processed to retrieve communication information related to data received along one or more communication links in a network. The at least one control unit is then stored in one or buffers. Finally, the at least one control unit is further processed to retrieve link information related to the one or more communication links.

Abstract: A packet memory system is provided. The packet memory system includes a memory cell array for storing a predefined number of packets. Each packet includes a predetermined number of segments. Each of the segments defines a starting point of a memory access. A packet decoder coupled to the memory cell array receives packet select inputs for selecting a packet. A segment decoder coupled to the memory cell array receives segment select inputs for selecting a segment. A data flow multiplexer is coupled to the memory cell array for transferring data between a data bus and the memory cell array. Command and mode registers receive command, read/write (R/W) and chip select (CS) inputs for opening a packet. Responsive to an opened packet, the packet select inputs provide a length for the memory access. Each of the segments has a preprogrammed length. Also each of the segments can be defined for a cache line.

Abstract: A switching element including first, second and third ports each comprising a plurality of lines is disclosed. A first memory cell includes a storage element, a first pass gate for selectively coupling a first line of the first port to the storage element, a second pass gate for selectively coupling a first line of the second port to the storage element, and a third pass gate for selectively coupling a first line of the third port to the storage element. A second memory cell includes a storage element, a first gate for selectively coupling a second line of the first port to the storage element, a second pass gate for selectively coupling a second line of the second port to the storage element, and a third pass gate for selectively coupling a second line of the third port to the storage element.

Abstract: A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: A multiplex communication system having a data repeater, which can prevent data from being lost so as to improve reliability of data communication, when a data repeater of a multiplex communication system repeats data. A multiplex communication system is made up of a plurality of communication groups including a plurality of communication lines and a data repeater. The data repeater is made up of receiving buffers, sending buffers, a data controller and a transfer-address table. The data controller selects multiplex communication lines through which the received data is to be repeated and transfers the received data thereto. The data controller has a priority-reset means for increasing a priority of a received data before being sent. The priority-reset means prioritizes a sending of the data from the data repeater, even if the data sent from the data repeater collides with the other data on the multiplex communication lines through which the received data is to be repeated.

Abstract: In a relay unit for relaying frames between a sending source and a receiving end by transmitting the frames from a transmitting-receiving buffer to the receiving end after the frames received from the sending source have temporarily been stored in the transmitting-receiving buffer, the frames are in the transmitting-receiving buffer, while the storage positions of the frames in the transmitting-receiving buffer are being managed in order of storage. Each time a new frame is stored in the transmitting-receiving buffer after the number of the frames in the transmitting-receiving buffer has reached a predetermined number, the storage area, in which the oldest frame among the frames is stored, is released from the transmitting-receiving buffer. With this arrangement, by contriving how to utilize the transmitting-receiving buffer, tracing a frame can be performed at high speeds, without providing a dedicated storage area for storing trace information and incurring complexity of the process.

Abstract: At the provider edge of a core network, an egress interface may schedule based on a class dominance model, a destination dominance model or a herein-proposed class-destination dominance model. In the latter, queues are organized into sub-divisions, where each of the subdivisions includes a subset of the queues having a per hop behavior in common and at least one of the subsets of the queues is further organized into a group of queues storing protocol data units having a common destination. Scheduling may then be performed on a destination basis first, then a per hop behavior basis. Thus providing user-awareness to a normally user-unaware class dominance scheduling model.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: An integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry comprises context buffers and data buffers. The co-processor circuitry receives and stores one of the communication packets in one of the data buffers. The co-processor circuitry correlates the one communication packet with one of a plurality of channel descriptors. The co-processor circuitry associates the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor. The co-processor circuitry prevents multiple valid copies of the one channel descriptor from existing in the context buffers. In some examples of the invention, this is accomplished by tracking a number of the data buffers associated with the one context buffer.

Abstract: Methods and apparatus are disclosed for handling transient anomalies in a communications or computer device or system, such an inverse multiplexing for ATM (“IMA”) device. Such transient anomalies may include out of IMA frame (“OIF”) anomalies. In one implementation, cells comprising a stream of packets are received over multiple links along with indications of OIF conditions for these links. During a period of an inactive OIF condition on a link, cells are received over the link and placed in a buffer at a next location. After an OIF condition is detected, cells are ignored and a write process waits until the OIF condition is no longer active. At which point, a buffer position is determined to place the next valid cell. This cell should be placed in the same buffer position as it would have been if there had never been an active OIF condition.

Abstract: A microprocessor architecture (310) has a plurality of functional units arranged in a parallel manner between one or more source buses (412 and/or 414) and one or more result buses (490). At least one of the functional units within the architecture is a content addressable memory (CAM) functional unit (430) which can be issued CPU instructions via a sequencer (480) much like any other functional unit. The operation of the CAM (430) may be pipelined in one or more stages so that the CAM's throughput may be increased to accommodate the higher clock rates that are likely used within the architecture (310). One embodiment involves pipelining the CAM operation in three stages (510, 520, and 530) in order to sequentially perform data input and precharge operations, followed by match operations, and followed Finally by priority encoding and data output.

Abstract: A method and apparatus are described for interfacing between a network interface and a bus. For the network interface-to-bus side, the method comprises (a) forming a network address of a message transferred via the network interface to the bus, and (b) mapping the network address to a bus address of the bus, the bus address being within an address space occupied by a bus device coupled to the bus. For the bus-to-network interface side, the method comprises (a) forming a bus index from a bus address of the bus where the bus address is within an address space occupied by a bus device coupled to the bus; and (b) mapping the bus index to a network address of a message transferred via the network interface to the bus.

Abstract: A group switching apparatus for multi-channel data is disclosed. It includes a speech memory to temporarily store a time slot to be switched, and a connection memory (CM) to store group connection information. Also, it includes a processor matching unit to interface group connection information provided from an upper processor to the CM and a counter to count a system clock signal and output a read address for the CM. Additionally, an offset generating unit receives group connection information outputted from the CM and generates a first offset value according to a signal representing an ‘ON’ state of group connection, and an adder adds the output of the counter and the output of the offset generating unit and outputting the added value as a read address for the SM.

Abstract: A DMA system includes a plurality of transmit-receive pairs (102, 104) for communicating on a bus. A DMA controller (108) supervises bus handling. The DMA controller (108) includes a priority controller (114), a bus sniffer (112), and a context machine (116). The bus sniffer (112) and context machine (116) identify block transfers as frame or cell transfers and supervise interleaving. The priority controller (114) resolves the priority of each of the constituent transfers of the frame or cell block transfers using a matrix of priority tokens.

Abstract: A system and corresponding method for randomly reordering a plurality or sequence of elements (E). In certain embodiments, ATM cells received by a switching apparatus may be randomly reordered as they proceed through an ATM switching apparatus, so as to enable the cells to be treated in a more fair manner. In one exemplary embodiment, a number or value within a given range(s) is randomly generated for each element E in a sequence or group to be randomly reordered. Each element E is shifted through a number of empty logic units or positions determined by the randomly generated number for that element, until finally being stored in one such unit. If none of the randomly generated number(s) for an element fall within the given range, a reserve number may be used to indicate how many empty logic units the element should be shifted, or a retry flag if set may cause a new set of random numbers to be generated for the element at issue.

Abstract: The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. In addition to a FIFO, an internal RAM capable of storing packets in a randomly accessible manner is provided between a link core and a CPU in a data transfer control device conforming to the IEEE 1394 standard. The RAM storage area is divided into a header area, a data area, and a CPU work area, and the header and data areas are divided into areas for reception and transmission. Tags are used to write the header of a receive packet to the header area and the data thereof to the data area. The data area is divided into areas for isochronous transfer and asynchronous transfer. Pointers are provided for controlling the size of each area in RAM variably, and the size of each area can be varied dynamically after power is switched on. Each area has a ring buffer structure.

Abstract: In one embodiment, a method including transmitting data cells through a plurality of queues to an input of a processor is disclosed. The method includes transmitting data cells from an output of the processor to corresponding virtual circuits. The amount of data transmitted through each queue is computed. The cumulative amount of data transmitted through all queues is also computed. For each queue, a ratio of the amount of data transmitted through the queue to the cumulative amount of data transmitted through all queues is determined. The method also determines an amount of processor time for each queue using the ratio for the queue.

Abstract: A method for controlling cell transmission on a basis of 1 byte between FIFOs of a UTOPIA interface, thereby performing cell transmission more speedily and more smoothly, which is achieved by advancing start timing of cell transmission by defining active timing of cell enable signal and cell available (CA) signal between FIFOs of the UTOPIA interface to a moment when a 1-byte data is available. The CA signal becomes active (high signal) when a TX FIFO has data with greater than 1 byte and a RX FIFO is able to receive data with greater than 1 byte. The cell enable (Enb) signal becomes active when an input CA signal in the TX FIFO is in a ‘high’ state and the TX FIFO has data with greater than 1 byte to be transmitted, and when an input CA signal in the RX FIFO is in a ‘high’ state and the RX FIFO is able to receive data with greater than 1 byte. As a result, a cell can be transmitted much faster as much as 52 bytes*clock and traffic performance of system can be improved considerably.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.