Abstract: A reduced-memory vectored DSL system reduces the bandwidth and memory storage demands on a vectored DSL system in which FEXT data is transmitted and stored. When test signal data, such as training and/or tracking data, is sent to determine FEXT characteristics of the DSL system, error signals are available for all or substantially all of the upstream and/or downstream frequency band DSL tones used in the system. Dividing a frequency band into sub-bands, only a subset of tones in each sub-band is used for deriving FEXT data. For tones in the sub-band subsets, full-precision FEXT data values can be derived. For other tones, approximations of the FEXT data can be derived. Memory is reduced in both the transmission of such FEXT data (between upstream and downstream ends) and within an upstream-end device such as a DSLAM that performs vectoring using a separate or internal vectoring processing apparatus.

Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided.

Abstract: A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.

Abstract: The embodiments herein relate to a method in a communications network comprising a communications link connecting a first device to a second device. The communications link comprises an upper layer having a variable delay and a lower layer having a constant delay. The first device comprises a first clock and the second device comprises a second clock. The communications network synchronizes the first clock via the lower layer of the communications link with the second clock. The communications network determines, at the second device, a residence time for a first message when transmitted from the first device to the second device via the upper layer of the communications link.

Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

Abstract: Embodiments of methods that are useful to avoid overflow in fixed-length buffers. In one embodiment, the methods dynamically adjust parameters (e.g., sample time) and reconfigure data in the buffer to allow new data samples to fit in the buffer. These embodiments allow data collection to automatically adapt, e.g., by adjusting the sample rate to allow the data to fit in the limited buffer size. These embodiments can configure hardware and/or software on a valve positioner of a valve assembly to improve data collection for use in on-line valve diagnostics and other data processing techniques.

Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.

Abstract: Various examples of techniques for identifying a corrupt data lane and using a spare data lane are described herein. Some examples include a method of coordinating spare lane usage between link partners. One such example comprises analyzing data from a link partner to identify a corrupt lane, and communicating the corrupt lane to the link partner, wherein the communication does not require sideband communication channel. In some embodiments, communicating the corrupt lane to the link partner comprises identifying a transmit lane corresponding to the corrupt lane, transmitting a set of data intended for a corresponding transmit lane using a spare data lane, and transmitting bad data to the link partner using the corresponding transmit lane.

Abstract: A circuit includes: a rectifier configured to receive a first clock signal and a second clock signal and output a rectified signal, wherein the second clock signal is the same as the first clock signal except for an offset in timing; a low-pass filter configured to receive the rectified signal and output a filtered signal; and an analog-to-digital converter configured to convert the filtered signal into a digital signal.

Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.

Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where m2 and n2 are real numbers that are different from one another and respectively differ from m1 and n1. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.

Abstract: Power saving in computing devices is provided. A first computing device communicates with a second computing device using a first set of tones. A low power event is detected by the first computing device. In response to the detected low power event, a request to communicate using a second set of tones is sent to the second computing device by the first computing device. The second set of tones has fewer tones than the first set of tones, and may be a subset of the first set of tones.

Abstract: An apparatus is provided. The apparatus includes a flip-flop including an input configured to receive a setup time and delay control (SDC) signal, and an output buffer including first and second conductive paths. The second conductive path is non-conductive when the SDC signal has a first value at the input and is conductive when the SDC signal has a second value at the input. The apparatus includes a propagation delay sensor configured to estimate a propagation delay of the flip-flop, and, when the estimated propagation delay exceeds a threshold, supply the SDC signal having the second value to the input of the flip-flop.

Abstract: Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function.

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract: According to one embodiment, a signal transmission apparatus being AC-coupled with a receiving apparatus through a digital transmission line includes a transmitting module configured to transmit a differential signal based on an encoded bit serial input signal such that a low frequency component of the differential signal to be transmitted is maintained at a constant level when the differential signal based on the encoded bit serial input signal is transmitted to the digital transmission line where the encoded bit serial input signal includes a ratio of the number of logic 1 to the number of logic 0 which is different from 5:5.

Abstract: A device compensates for distortions of a serial data signal introduced by a communication channel in a serial communication system. The device includes main path, first and second delay paths, first and second pulse generators, and combiner. The first and second delay paths delay a tapped-off portion of the serial data signal by first and second delay amounts, respectively, where the first delay amount is less than a main path delay amount and the second delay amount greater the main path delay amount. The first and second pulse generators generate first and second compensation pulses in response to the serial data signal delayed by the first and second delay amounts, respectively. The combiner combines the first and second compensation pulses with the main path delayed serial data signal, where the first and second compensation pulses compensate for magnitude loss and nonlinear phase of the main path delayed serial data signal.

Abstract: The present invention relates to a method includes: implementing, by the board in the BBU1, frequency synchronization between a system clock of the board in the BBU1 and a system clock of the board in the BBU0 by using a synchronous Ethernet clock that is output by the board in the BBU0; and implementing, by the board in the BBU1, time synchronization between the system clock of the board in the BBU1 and the system clock of the board in the BBU0 by using an IEEE1588 clock that is output by the board in the BBU0. The present invention can enable the multimode base station to support more standards.

Abstract: Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an RZ signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode, that receives the RZ signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.

Abstract: A lens apparatus is detachable from an image pickup apparatus. The lens apparatus includes a controller configured to communicate with the image pickup apparatus in synchronization with a first signal. A communication contains a plurality of blocks in the same cycle of the first signal. The controller transmits information of a first time period to the image pickup apparatus, and prohibits a communication of an m-th block from starting before the first time period passes after a communication of an n-th block starts or ends where n is an integer equal to or larger than 1 and m is an integer larger than n.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped.

Abstract: A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.

Abstract: The present invention relates to a method for adjusting transitions in a bit stream of a signal to be evaluated by comparison with a predetermined expected bit stream, comprising the steps of receiving said bit stream signal by a transition adjustment filter, providing a transition frame signal to said transition adjustment filter, said transition frame signal providing information for eliminating non-deterministic clock latencies within said bit stream of said received signal, and adjusting said bit stream of said received signal according to said transition frame signal resulting in an adjusted bit stream being in alignment to said expected bit stream.

Abstract: An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line, a coarse phase alignment logic circuit coupled to the tapped delay line, and a selector coupled to the tapped delay and the coarse phase alignment logic circuit. An apparatus for timing and data recovery for burst mode receivers comprising: a receiver, a coarse phase alignment circuit coupled to the receiver, at least one analog to digital converter (ADC) coupled to the coarse phase alignment circuit such that the coarse phase alignment circuit is positioned between the receiver and the ADC, and a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit produces a recovered data output.

Abstract: Interfacing between radio units in a base station in a mobile communication system may use synchronized clocks. A controller device has a tracking clock circuit for generating a transmit clock, the tracking clock circuit comprising a clock input for receiving a reference clock and a sync input for receiving an external synchronization signal. A multiplying phase locked loop generates the transmit clock in dependence on the reference clock and a divider output of a controllable divider coupled to the transmit clock. A tracking loop has a phase detector coupled to the sync input and the divider output for detecting a phase error between the external synchronization signal and transmit clock, and a phase control circuit for generating a phase control signal based on the phase error, the phase control signal being coupled to a control input of the controllable divider for adapting the division function.

Abstract: A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).

Abstract: Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced spurs. In particular, implementations of switch controllers described herein include a poly-phase clocking scheme, as opposed to a single phase to clock the charge pump stages of an negative voltage generator. In some implementations poly-phase clocking schemes reduce the clock signal induced spurs and may preclude the need for additional on-chip or off-chip decoupling capacitors that add to the cost and physical size of a complete front end module solution.

Abstract: A receiver circuit includes: a data interpolation switched capacitor circuit which samples a data signal and outputs a voltage value interpolated from a sampled voltage value in correspondence with an interpolation code indicating an interpolation ratio; a comparator which performs comparison between the voltage value outputted from the data interpolation switched capacitor circuit and a threshold value; a phase detection circuit which detects a boundary based on an output of the comparator and decides whether to advance or delay a phase; and an interpolation code generation circuit which generates an interpolation code corresponding to an output of the phase detection circuit, wherein a phase offset related to sampling is imparted and an offset corresponding to an amount of the phase offset is imparted to the threshold value of the comparator.

Abstract: In a computer-implemented method of adjusting a local clock at a receiver in a packet network, the local clock is generated by a phase locked loop locked to a master clock with the aid of time-stamped timing packets arriving over the network from the master clock with a packet delay distribution about a nominal delay. The timing packets are filtered to adjust for the packet delay distribution. A control input for the phase locked loop is derived from the timing packets. The amount of skew in the packet delay distribution about the nominal delay is determined, and the arrival times of timing packets are then selectively modified to correct for the amount of skew in the packet delay variation distribution prior to filtering the timing packets.

Abstract: The present invention relates to a method and apparatus for controlling supply voltage of clock and data recovery circuit.

Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.

Abstract: Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs.

Abstract: A signal propagation system for communicating timing information comprises a processing resource (300) arranged to generate a first timing signal for communicating the timing information, the first timing signal having a first frequency spectrum associated therewith. An electronic circuit (110) is provided having an input for receiving the timing information. An electrical connection (310) between the processing resource (300) and the electronic circuit (110) is also provided. A signal transformation module (304) for communicating the timing information, and the signal transformation module (304) is arranged to translate the first timing signal into a second timing signal for communicating the timing information. The second timing signal has a second frequency spectrum associated therewith that comprises fewer harmonics than the first timing signal, thereby reducing electromagnetic energy emitted by the electrical connection.

Abstract: An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.

Abstract: An image rejection (IR) circuit is configured to receive a complex signal from a radio frequency (RF) mixer, where the complex signal includes an in-phase signal portion and a quadrature signal portion. This IR circuit may include: an in-phase path to remove first mismatch information from the in-phase signal portion and associated with at least one in-phase multi-tap filter; a quadrature path to remove second mismatch information from the quadrature signal portion and associated with at least one quadrature multi-tap filter; and a correlation unit to independently update each of the multiple taps of the in-phase multi-tap filter and the quadrature multi-tap filter according to a priority scheme.

Abstract: There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards.

Abstract: The present invention relates to a method for compensating timing errors of real-time clocks, which comprises a compensating step, wherein in step 1, assign CNT to be 0 and execute step two; in step 2, assign FLAG to be 1 when a rising edge of 1 Hz clock is arrived and execute step 3; in step 3, judge FLAG and M3, if FLAG=1 and M3<0, execute step 4 while waiting until CNT=S4; if FLAG=1, CNT=0 and M3>0, execute step 5; otherwise execute step 2; in step 4, execute an assignment operation, CNT=0, M3=M3+S4, FLAG=0 and restart step 2; in step 5, execute an assignment operation, CNT=S4, M3=M3?S4, FLAG=0, and restart step 2. A sampling frequency of relative errors ERR of the present invention is adjustable, and a compensatory accuracy is much higher.

Abstract: An I2C interface is provided which has a data line and a clock line, the clock line having a first input buffer, and the data line having a second input buffer and an output buffer, the data line being provided for the transmission of a data input signal and a data output signal, the clock line being provided for the transmission of a clock signal, the clock line having a first delay element, and the data line having a second delay element and a third delay element. A method for operating an I2C slave interface is also provided.

Abstract: A signal receiver is configured to receive multiple time-domain input signals. A plurality of the input signals among the multiple time-domain input signals is selected and transformed into frequency-domain signals. The frequency-domain signals are shifted in phase by a negative value of a respective reference phase, and the phase-shifted signals are combined into one signal. The combined signal is then multiplied with a stored signal to generate a signal product and transformed into a time-domain signal. Peak detection is performed on the time-domain signal.

Abstract: Provided is a reception apparatus including: a correction unit that corrects phase compensation for each one of multiple phase-compensated segments that are connected one after another, in which the correction unit includes a timing generation unit that, based on a phase of a known signal, generates a timing at which an amount of the phase compensation is initialized, an amount-of-correction generation unit that, based on the phase of the known signal, generates an amount of correction for correcting the amount of the phase compensation, and a phase correction unit that performs phase correction on the phase compensation using the amount of the correction that is generated by the amount-of-correction generation unit.

Abstract: A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each interpolation circuit receives multiple phase clocks, and interpolates an interpolation clock from two of the phase clocks. The phase clocks have the same frequency but different phases. The edge detection circuit is connected electrically to the delay chain, and generates an output clock according to an edge of the interpolation clock.

Abstract: Methods and systems are provided for using decision feedback phase error correction during signal processing. When an input signal comprises a plurality of sub-carriers, each of the plurality of sub-carriers may be processed separately, wherein the processing may comprise determining for each one of the plurality sub-carriers error related information; and the determined error related information may be applied as separate feedback, such as to allow separately adjusting subsequent processing of the corresponding one of the plurality of sub-carriers. The error related information may comprise phase error related information. At least part of the error related information based on data carried by the corresponding one of the plurality of sub-carriers. The plurality of sub-carriers comprises orthogonal frequency-division multiplexing (OFDM) based sub-carriers. Error related information obtained from processing of at least some of the plurality of sub-carriers may be shared.

Abstract: The present invention relates to a method includes: implementing, by the board in the BBU1, frequency synchronization between a system clock of the board in the BBU1 and a system clock of the board in the BBU0 by using a synchronous Ethernet clock that is output by the board in the BBU0; and implementing, by the board in the BBU1, time synchronization between the system clock of the board in the BBU1 and the system clock of the board in the BBU0 by using an IEEE1588 clock that is output by the board in the BBU0. The present invention can enable the multimode base station to support more standards.

Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

Abstract: In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.

Abstract: A channel in a multiple carrier communication system is equalized by computing a desired spectral response, shortening the impulse response of the channel so that a significant part of an energy of the impulse response is confined to a region that is shorter than a target length and filtering the signal based on the desired spectral response. A multiple carrier communication system may include a primary impulse shortening filter that receives an output signal of an analog to digital converter and accepts coefficients. A secondary impulse shortening filter may receive the output signal of the analog to digital converter, output an output signal, and pass coefficients to the primary impulse shortening filter. A reference signal generator may output a reference signal. A comparator may compare the output signal and the reference signal and output a resulting error signal. An adaptive processor may compute coefficients for the secondary impulse shortening filter based on the error signal.