Abstract: A method detects a threshold crossing instant at which a signal crosses a threshold, by: sampling the signal at plural sampling instants spaced from one another by a sampling period; detecting consecutive first and second sampling instants at which the signal has a first signal value lower than or equal to the threshold, and the signal has a second signal value higher than the threshold, respectively; calculating a first interval indicative of a time between the threshold crossing instant and the first sampling instant; setting a reference signal having a reference amplitude representing the first interval relative to a reference scale; generating a signal with a delay depending on said reference signal; generating a threshold crossing detection signal at an instant delayed by a second interval; calibrating the reference scale of the reference amplitude so that the second interval is substantially equal to the first interval.

Abstract: A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal.

Abstract: The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data.

Abstract: Described herein are systems and methods for synchronization in a networked environment. For example, some embodiments provide methods for synchronizing a client device having a client media time reference with a server device having a server media time reference. In some cases such methods are embodied in computer readable code that is executable on one or more processors. Furthermore, some embodiments provide hardware, such as networked media devices that are configured to perform such methods. In overview, in some embodiments a client obtains timing information from a server and, on the basis of this timing information, applies an adjustment to a client control time reference, thereby to synchronize the client media time reference with the server media time reference. Some embodiments are particularly directed to the situation where there is a desire to synchronize networked media devices across a combination of wired and wireless networks.

Abstract: Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.

Abstract: A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.

Abstract: FIR filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component, with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the on signal. In another embodiment, a FIR filter includes a delay line with a total delay longer than the period of the jitter. A signal is passed down the delay line, the number of signal edges that have occurred as the signal passes each delay element in the counted. Drivers corresponding to the delay elements in which a number of signal edges occur at the desired frequency during the period of fixed pattern jitter activate impedance elements attached to those delay elements.

Abstract: A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract: An overhead processor for data transmission in digital communications is disclosed. Incoming data is transmitted along a datapath. If there are two or more groups of incoming data, arriving separately, the initial group(s) of received data can be held in an elastic store until the arrival of additional group(s) of data, and upon the arrival of additional group(s) of data, all received data are combined and transmitted into flip-flop(s). The data is transmitted from said flip-flop(s) to a logic element to determine the new data context of imminent incoming data prior to any additional incoming bytes arriving along the datapath. Therefore, the number of overhead processors required for multi-byte data transmission is reduced, potentially reducing the number of required overhead processors in digital communications to 1.

Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Abstract: Embodiments relate to systems and methods for reducing jitter caused by frequency modulation of a clock signal including modulating the frequency of the clock signal based on a predetermined modulation signal m(t), and compensating an accumulated jitter J(t) caused by the frequency modulation of the clock signal such that an absolute value of the accumulated jitter J(t) never exceeds a predetermined jitter limit Jlim.

Abstract: A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.

Abstract: Method, device and system for detecting a disturbance, e.g., at least one short mechanical impact (shock or vibration) on a clock of a slave device by detecting a non-typical variation of a tracking error, i.e., a tracking error having a deviation that exceeds a predetermined threshold, wherein such a non-typical variation can be determined by the deviation from a statistical measure, e.g., a variance or a standard deviation, such that the determination of the quality of a clock signal is advantageously allowed and thus suitable counter-measures are provided. The method, device and system are applicable for all kinds of technical systems comprising slave devices that have a clock, e.g., devices in industrial and automation systems. The method, device and system are also applicable in communication systems that use a protocol to synchronize the clocks of its devices, e.g., Profinet.

Abstract: The present technology relates to protocols relative to utility meters associated with an open operational framework. More particularly, the present subject matter relates to protocol subject matter for advanced metering infrastructure, adaptable to various international standards, while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field. The present subject matter supports meters within an ANSI standard C12.22/C12.19 system while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field, all to permit cell-based adaptive insertion of C12.22 meters within an open framework. Cell isolation is provided through quasi-orthogonal sequences in a frequency hopping network. Additional features relate to apparatus (both network and device related) and methodology subject matters relating to uplink routing without requiring a routing table.

Abstract: Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.

Abstract: There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal.

Abstract: Symbol timing acquisition is described for a wireless broadband signal received at a user terminal from a gateway via a satellite. In-phase and quadrature channels of the wireless signal may each be sampled at a rate of one sample per symbol. The samples may be interpolated to generate an early interpolation and a late interpolation for each of the samples. A difference measurement is obtained between the early interpolation and the late interpolation for a set of the samples. A number of the difference measurements may be averaged, and symbol timing may be modified based on the average. This process may be continued on an iterative basis to acquire symbol timing.

Abstract: An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal.

Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.

Abstract: A wideband frequency synthesizer and a frequency synthesizing method thereof are provided. The wideband frequency synthesizer includes a phase-locked loop unit, a first voltage-controlled oscillating unit and a first frequency mixer unit. The phase-locked loop unit receives a reference signal and a feedback signal and generates a first oscillating signal according to the reference signal and the feedback signal. The first voltage-controlled oscillating unit generates a second oscillating signal. The first frequency mixer is coupled to the phase-locked loop unit and the first voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal for mixing frequencies of the first oscillating signal and the second oscillating signal to generate an output signal and taking the output signal as the feedback signal for outputting to the phase-locked loop unit.

Abstract: A node device includes a processor, a wireless RF circuit, a memory, and a timer. The processor measures a clock time. The wireless RF circuit receives a clock time information frame containing clock time information used for correcting the clock time. The memory stores a transmission processing time period, as a fixed value, from when a transmission source node device of the clock time information frame obtains the clock time information until when the transmission source node device transmits the clock time information frame. The timer measures a reception processing time period, which is a period of time from when the clock time information frame is received until when the clock time information is obtained. The node device sets to the processor a value obtained by adding the fixed value and the reception processing time period to the clock time information.

Abstract: A patient medical signal processing system adaptively reconstructs a medical signal sampled using a varying sampling rate. The system includes an input processor and a signal processor. The input processor receives first data and second data. The first data represents a first portion of a medical signal derived by sampling at a first sampling rate and the second data represents a second portion of the medical signal derived by sampling at a second sampling rate. The first and the second sampling rates are different and comprise a master clock rate or an integer division of the master clock rate. A signal processor provides a reconstructed sampled medical signal by, interpolating the second data to provide third data at the first sampling rate and combining the first data and the third data to provide the reconstructed sampled medical signal.

Abstract: A receiver may process a received signal to generate a processed received signal. The receiver may generate, during a sequence estimation process, an estimate of a phase error of the processed received signal. The receiver may generate an estimate of a value of a transmitted symbol corresponding to the received signal based on the estimated phase error. The generation of the estimate of the phase error may comprise generation of one or more phase candidate vectors. The generation of the estimate may comprise calculation of a metric based on the one or more phase candidate vectors. The calculation of the metric may comprise phase shifting the processed received signal based on the estimated phase error resulting in a phase-corrected received signal. The calculation of the metric may comprise calculating a Euclidean distance based on the phase-corrected received signal and one or more symbol candidate vectors.

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.

Abstract: Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.

Abstract: A wireless communications system including a mobile station MS and base stations BS1 and BS2, wherein one or both of the mobile station MS and the base stations BS1 and BS2 is provided with a unit for notifying information of a frame position with the possibility of transmission of packets based on detection of deterioration of a reception quality and wherein the mobile station MS is provided with a unit for determining a frame position without the possibility of transmission of packets and shifting to a peripheral cell detection mode at this frame position based on information of a frame position with the possibility of transmission of packets, whereby it is possible to shift to a peripheral cell detection mode without lowering the transmission efficiency and without complicating the processing.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: A transmitting interconnect interface inserts clock mismatch compensation symbols into a transmitted data stream so as to allow the receiving interconnect interface to compensate for clock frequency mismatch between transmit-side and receive-side clocks. The transmitting interconnect interface adjusts the rate of insertion of these symbols based on a determination of the clock frequency mismatch. The transmitting interconnect interface can incrementally adjust the insertion rate to change substantially proportionally with changes in the clock frequency mismatch. Alternatively, the transmitting interconnect interface can set the insertion rate to one of two levels. By adapting the insertion rate to the current measured clock frequency mismatch, the bandwidth penalty incurred by transmitting clock mismatch compensation symbols in excess of that necessary to permit receiver clock tolerance compensation can be reduced, thereby permitting more transmit bandwidth to be used for transmitting data.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: A technique to provide hybrid compensation to correct for drifts in a reference frequency output from a digitally-controlled crystal oscillator (DCXO). A first compensation is provided to the DCXO to adjust for overlap or discontinuity of the reference frequency caused by switching capacitors in the capacitor array that controls drift of the reference frequency output. The second compensation is obtained at a phase-locked loop (PLL) that receives the reference frequency signal from the DCXO. The second compensation adjusts the PLL to adjust for variations of the reference frequency that remain after performing compensation in the DCXO.

Abstract: Clock compensation for GPS receivers. A receiver in accordance with the present invention comprises a Radio Frequency (RF) portion, and a baseband portion, coupled to the RF portion, wherein the baseband portion comprises a crystal, an oscillator, coupled to the crystal, wherein the oscillator generates a clock signal based on a signal received from the crystal, a counter, coupled to the oscillator via the clock signal, a comparator, coupled to the counter, a controller, at least one logic gate, coupled to the comparator and the controller, and a combiner, coupled to the at least one logic gate, the controller, and the counter and producing an accurate clock signal therefrom.

Abstract: A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.

Abstract: Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.

Abstract: A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.

Abstract: Provided is a transmission device that transmits or receives synchronous data used to perform synchronization of a clock through a transmission path having a variable transmission band and includes a transmission band acquiring unit that acquires a current transmission band in the transmission path, a calculating unit that calculates a time necessary until the synchronous data is received after the synchronous data is transmitted through the transmission path based on the transmission band, and accumulates the calculated time and a staying time of the synchronous data in its own device as delay information recorded in the synchronous data, and a transmitting unit that writes a value of a result of accumulation by the calculating unit to the synchronous data as new delay information of the synchronous data, and transmits the synchronous data.

Abstract: A signal receiving circuit having an equalizer calibration function. The signal receiving circuit includes a sampling circuit, output driver and clock signal generator. The sampling circuit captures samples of a data signal in response to a sampling clock signal. The output driver outputs an equalizing signal to an input of the sampling circuit in response to a first clock signal. The clock signal generator adjusts a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.

Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal.

Abstract: A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.

Abstract: A high performance CDR circuit. The circuit includes a first and second sampler, a first and second charge-pump coupled to the first and the second sampler, a capacitor coupled to the first charge pump, and a filter coupled to the second charge pump. A VCO circuit is coupled to the first charge pump and the second charge pump, wherein a path for setting a frequency is provided by the first charge pump and the capacitor, and wherein a path for phase is provided by the second charge pump, wherein a voltage of the capacitor is stable to enable the VCO to tolerate CIDs.

Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Abstract: Method and apparatus for determining a transport bit rate for a multiprogram transport stream (MPTS) is described. In one example, a plurality of transport bit rates is computed for a respective plurality of programs in the MPTS. A highest transport bit rate and a lowest transport bit rate are selected from the plurality of transport bit rates. An average transport bit rate is computed from the highest transport bit rate and the lowest transport bit rate. The average transport bit rate is provided as an initial transport bit rate for the MPTS. Jitter in the MPTS may be compensated using the initial transport bit rate.

Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.

Abstract: Disclosed are a method and apparatus for estimating symbol timing in a non-synchronized OFDM system. The present invention includes synchronizing a frame of a received signal, estimating the symbol timing of each symbol of the frame based on the synchronization, compensating for the symbol timing using a phase difference attributable to a Symbol Timing Offset (STO), variably changing within a Cyclic Prefix (CP) interval due to the frequency offset of a sampling clock and thermal noise, and performing channel equalization using a preamble based on output including corrected phase rotation.

Abstract: A method of communication to a semiconductor device includes: transmitting a sampling clock signal from a first semiconductor device to a second semiconductor device; transmitting a training signal from the first semiconductor device to the second semiconductor device while transmitting of the sampling clock signal, the training signal comprising plural test patterns sent sequentially to the second semiconductor device, phases of at least some of the test patterns being adjusted to be different from each other during transmitting of the training signal; receiving first information from the second semiconductor device over a first signal line, the first signal line separate from a data bus connected between the first semiconductor device and the second semiconductor device; and transmitting a data signal over the data bus while transmitting the sampling clock signal, the data signal sent at a timing with respect to the sampling clock signal responsive to the received first information.

Abstract: Briefly, in accordance with one or more embodiments, mobile station or user equipment receives pilot signals from two or more infrastructure nodes in a distributed antenna system, and calculates phase or timing information, or combinations thereof, from the pilot signals. The mobile station feeds back the phase or timing information, or combinations thereof, to the infrastructure nodes, and then receives one or more subsequent transmissions from the infrastructure nodes with phase shift or timing adjustments, or combinations thereof, calculated by the infrastructure nodes and applied to the spatial streams transmitted by the infrastructure nodes.