Abstract: A reception circuit includes: a sampling circuit to sample an input data signal based on a clock signal and output a sampled signal; a data interpolation circuit to interpolate the sampled signal based on phase information corresponding to the sampled signal and output an interpolated data signal; an interpolation error decision circuit to output an interpolation error based on the sampled signal and the phase information; a decision/equalization circuit to equalize the interpolated data signal using an equalization coefficient set based on the interpolation error, to check an equalized interpolated data signal and to output a checked signal; and a phase detection circuit to generate the phase information based on at least one of the checked signal and the equalized interpolated data signal and output the phase information to the data interpolation circuit and the interpolation error decision circuit.

Abstract: The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.

Abstract: Methods and structures are disclosed for aligning high speed data across a plurality of lanes. In one embodiment, a method and integrated circuit (“IC”) is provided for receiving and aligning scrambled training data across a plurality of data lanes before the data is descrambled. In some implementations, a known scrambled training pattern is different in each lane and alignment includes comparing incoming training data in each lane to different known scrambled training patterns in each lane. In some implementations, after scrambled data is aligned and then descrambled, it is checked against a known unscrambled training pattern to make sure that alignment of the scrambled training data was correct. In an alternative embodiment, data is descrambled before being aligned, but deskew circuitry output is monitored to determine if a training pattern ends at the same time across the plurality of lanes being aligned.

Abstract: Disclosed herein is a mobile terminal and an operation control method thereof in which a delay time of the screen lock execution is controlled according to the type of application, thereby improving the inconvenience of a user interface and effectively managing a battery according to an interrupt when required to continuously receive an input from the user or continuously provide visual information to the user. For this purpose, a mobile terminal according to an embodiment of the present disclosure may include an input unit configured to receive a user input; an execution controller configured to execute screen lock if the user input is not received for a predetermined time; and a change controller configured to change the predetermined time based on a type of application.

Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Abstract: In a method of recovering timing information over packet networks, raw network delays are measured using timing packets sent between a transmitter and receiver. The expected delay is predicted using a minimum statistics adaptive filter to track local minima of measured time delays over a smoothing window. Only those incoming timing packets which meet a particular criterion relative to the expected delay within a smoothing window are selected, and a local clock is adjusted based on the measured timing delays from the selected timing packets.

Abstract: A serializer-deserializer (SERDES) includes a clock-data recovery block, a control block, and a low-pass filter. The control block contains a state machine that includes a fast convergence mode utilizing an unstable operating point and a slow tracking mode utilizing a stable operating point. The control block is configured to start in the fast convergence mode to allow quickly locking the recovered clock to the incoming data stream by replicating movement commands resulting in multiple phase adjustments for each transition. To facilitate proper operation of the SERDES, the fast convergence mode is exited after N-bits and a slow tracking mode is entered to provide stable operation. The control block accepts filtered transition-data and data-transition phase state signals and converges to a phase aligned state in less than 2N-bits where N represents the number of phases in one data bit.

Abstract: In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a phase relationship between the first clock and the second clock. Then, the phase-adjustment circuit in the clock-adjustment circuit adjusts a phase of the first clock relative to the second clock if the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that transfers data from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: Circuits and methods are described for adaptive timing and communications. Described circuitry includes circuitry to receive an incoming data signal based on a receive clock signal, which is based on a local clock signal (LCS); an offset adjustment circuit to receive timing information relating the LCS to the incoming data signal and calculate a phase offset and a frequency offset indicative of adjustment(s) to be made to the LCS; a first phase interpolator to produce the receive clock signal by adjusting the LCS in response to the phase offset and the frequency offset; a clock recovery circuit to generate the timing information responsive to whether the receive clock signal leads or lags the incoming data signal; a second phase interpolator to produce a transmit clock signal by adjusting the LCS in response to the frequency offset; and circuitry to transmit an outgoing data signal based on the transmit clock signal.

Abstract: A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal.

Abstract: The present specification describes techniques and apparatus for reducing eye monitor data samplers in a receiver. A single eye monitor data sampler is used for multiple normal data samplers in a receiver.

Abstract: A clock and data recovery circuit injects a noise waveform into the control loop to offset the data sampling point artificially in order to induce errors. The amplitude of the injected waveform can be varied to ascertain the effect on the bit error rate (BER) so as to be able to evaluate the temporal noise margin.

Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.

Abstract: A data clock recovery system is provided. A phase detector is configured to sample an input data stream by way of a data clock and a second clock to generate a first signal indicating whether a data clock lags or leads a preferred phase of the data clock in relation to an input data stream. A phase controller is configured to process the first signal to shift a phase of the second clock toward a second preferred phase, and to shift a phase of the data clock toward the first preferred phase after the shifting of the phase of the second clock.

Abstract: Provided is a network synchronization method and apparatus for performing a time synchronization between nodes. When a system starts up and the time synchronization between the nodes is initiated, the network synchronization method and apparatus may enhance jitter, wander, and a time synchronization performance by gradually increasing a window size for a propagation time measurement. When a full window of propagation time measurements is collected, the network synchronization method and apparatus may enhance jitter, wander, and the time synchronization performance by applying an exponential to a computation of an average propagation time value.

Abstract: Methods and apparatus for maintaining the maximum achievable data rate on a DSL line, up to and including a rate to which a user subscribes is described. Performance monitoring is conducted on the DSL line on an ongoing basis to determine noise margins in each direction. Each noise margin is compared against pre-determined decreasing/increasing thresholds to determine whether the line characteristics dictate a data rate change without loss of synchronization. The invention supports dynamic provisioning changes including application driven service level change requests, e.g., new bandwidth-on demand services. In some embodiments, a combination of existing and new embedded operations channel (EOC) messages are used to implement the modem data rate changes. New EOC messages may be implemented using some of the reserved and/or vendor proprietary Opcodes currently permitted. Modem assigned data rate changes are implemented without a disruption of service, e.g.

Abstract: A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.

Abstract: In the disclosed system and method phase (and optionally amplitude) shifts are applied at an OFDM transmitter to resource blocks within a given slot to implement Crest Factor Reduction (CFR). The phase shifts may differ between resource blocks and are selected to reduce the peaks in the OFDM waveform. The resource block phase shifts do not affect the demodulation process when the equalization at the receiver is performed on individual blocks separately. As a result, the crest factor reduction is achieved without increasing the EVM or BER in the received signal. In addition, a computational efficient algorithm for determining the resource block phase shifts needed for CFR is disclosed.

Abstract: In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

Abstract: A method and a device for multi-channel data alignment in a transmission system are provided, wherein the method comprises receiving a first stream data and a second stream data, determining a deleting/inserting state of the first stream data and the second stream data to generate an information of mismatch data due to a speed difference situation, generating a reverse inserting control signal or a reverse deleting control signal to completely restore the original first stream data and/or the original second stream data at a transmission end, deleting/inserting the first stream data and the second stream data simultaneously after receiving the deleting/inserting state of the first stream data and the second stream data, and outputting the corrected first stream data and the corrected second stream data without mismatching.

Abstract: A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in a received signal in which a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule; a pattern matching portion which performs pattern matching between the received signal and the synchronization system; a symbol counter which outputs a symbol number; a timing detection portion which detects the frame synchronization signal of each frame based on a pattern matching processing result and to output the symbol number at the detection timing; and a frequency error detection portion which detects a change of the symbol number and to detect a clock frequency error of the symbol period based on the detection.

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.

Abstract: A chirp receiver processes broadcast chirp signals in the frequency domain to distinguish direct path signals from multipath signals. The receiver processes received chirp signals consisting of respective pulsed frequency sweeps by combining the signals with a synchronized local chirp signal and phase adjusting and concatenating the results over multiple sweeps based on estimated clock phase errors and expected phase rotations of the direct path signals, and produces a sine wave. The phase adjustment and concatenation allows the use of longer Fast Fourier Transforms, which provide increased accuracy of frequency estimation and separate component signals that are very close in frequency. The frequency corresponding to the direct path signal is identified by the lowest frequency bin in which power is above a predetermined noise threshold. The receiver then determines a time delay based on the identified frequency and uses the time delay to calculate accurate clock phase error and position.

Abstract: A method and apparatus for performing jitter buffering is provided herein. During operation, a system will utilize variable-length jitter buffers within each receiver. Each receiver will then be assigned an appropriate jitter-buffer size based upon system constraints. In one embodiment of the present invention jitter-buffer size is adjusted on a per call (or even per call/speech segment) basis and is based on both the source and destination capabilities.

Abstract: A source device counts a clock CLKpixel for pixel data using a transmitting counter, adds a counted value Csource(t) of the transmitting counter at a timing of transmitting a video packet Pvideo to the sink device to a header part of the video packet Pvideo as a time stamp value Csource(t), and transmits the video packet Pvideo to the sink device. The sink device receives the video packet Pvideo, extracts the time stamp value Csource(t) from the header part of the video packet Pvideo, generates a fixed reference clock CLKref based on the counted value Csource(t) of the transmitting counter using a first PLL, circuit, and generates the clock CLKpixel for the pixel data of the source device based on the reference clock CLKref using a second PLL circuit.

Abstract: A data output circuit of a semiconductor apparatus includes a clock skew compensation repeater configured to control a delay amount of a clock in response to skew compensation codes and output a data synchronization clock; a mismatch compensation driver configured to synchronize internal data with the data synchronization clock and output the internal data synchronized with the data synchronization clock by controlling a transition timing of the internal data according to mismatch compensation codes; and a data output driver configured to generate output data in response to an output of the mismatch compensation driver.

Abstract: According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and transmits a deskew signal related to the multi-level-coded signals. The communication system also includes a receiving apparatus with a decoding section that decodes the multi-level-coded signals to generate decoded signals, and a deskew processing section that performs deskew processing for compensating skew among the decoded signals of the multiple channels. The deskew signal generation section generates the deskew signal that has been framed by extracting a part of the data from each of the channels of the input signals, adding framing data for enabling a receiving apparatus to recognize which channel the extracted data has been extracted from, and performing rate conversion.

Abstract: A serial bus device for transmitting a packet to a link partner is provided. The serial bus device includes a processing unit and a clock difference compensation unit coupled to the processing unit. The processing unit generates the packet. The clock difference compensation unit determines whether to transmit at least one skip ordered set to the link partner prior to the packet according to a type of the packet, so as to compensate for a clock difference for the link partner.

Abstract: Provided is a signal processing apparatus including: an equalizer circuit that amplifies a predetermined frequency band of an input signal and outputs an output signal; a sampler circuit that samples the output signal amplified by the equalizer circuit with the output signal being offset in an amplitude direction using a multiphase clock system; an area information calculation circuit that calculates area information of an eye opening in an eye diagram of the output signal based on the output signal sampled by the sampler circuit; and a control circuit that controls amplification of the equalizer circuit based on the area information of the eye opening calculated by the area information calculation circuit.

Abstract: A device is described for receiving data transmitted using asynchronous data transmission technology, in particular audio and video data, which receives a clock signal, having a memory device (17), which stores the received data for the required period of time in order to compensate for transmission delays (Cell Delay Variation). The clock signal is sent to the memory device (17) for reading out the data. Furthermore, a method is described for receiving data signals using asynchronous data transfer technology, with the received data signals being temporarily stored and read out at the studio clock rate.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in which the spread amount is in proportion to the digital parallel signal. The delta sigma modulator, electrically connected to the triangular modulator, generates a divider divisor, including the decimal and an integer, according to the digital modulation signal. The frequency divider divides the frequency of the output signal clock according to the divider divisor to generate a divided clock signal, in which the frequency of the divided clock signal is substantially equal to a quotient result from dividing the frequency of the output clock signal with the divider divisor. The phase lock loop adjusts the frequency of the output clock signal according to the divided clock signal and a reference clock signal.

Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods of in-phase and quadrature mismatch analysis and correction. For example, a method in accordance with an embodiment of the invention may include re-encoding an estimated symbol of an input signal having an in-phase component and a quadrature component, based on an analysis of a mismatch between said in-phase component and said quadrature component.

Abstract: A digital waveform synthesizer (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesizer (10) which produces a synthesized output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A testing method for carrying out an accuracy testing operation on a system time signal of a computer device under test includes the following steps. First, first and second clock cycle parameters of an operation clock signal (CPU clock) are respectively recorded in response to first and second triggering edges triggered by an external reference time signal. Next, a reference clock cycle parameter is determined according to the first and second clock cycle parameters. Then, third and fourth clock cycle parameters of the operation clock signal are respectively recorded in response to third and fourth triggering edges triggered by the system time signal. Next, a to-be-measured clock cycle parameter is obtained according to the third and fourth clock cycle parameters. Thereafter, error information of the system time signal is obtained according to the to-be-measured clock cycle parameter and the reference clock cycle parameter.

Abstract: A method and system of fine timing synchronization for an OFDM signal. The OFDM signal is coarse timing synchronized, generating a synchronization sequence and a CFR (Channel Frequency Response). The synchronization sequence is removed. A correlation coefficient of the correlation between the CFR applied to a number of carriers and the number of carriers with different window shifts is calculated. The largest window shift corresponding to a downsampling factor is indicated by the lowest correlation coefficient greater than a threshold. The CFR is downsampled by the downsampling factor, and an inverse FFT is performed on the downsampled CFR with a reduced number of calculations reduced by the downsampling factor, transforming the CFR into a CIR. A fine timing synchronization position is determined from the CIR and is utilized by an FFT unit within an OFDM receiver to accurately receive OFDM symbols of the OFDM signal.

Abstract: Systems and methods are described that may be used to detect and correct carrier phase offset in a signal. A phase offset corrector receives an equalized signal representative of a quadrature amplitude modulated signal and derives a phase-corrected signal from the equalized signal. The equalized signal is sliced to obtain real and imaginary sequences and a frame synchronizer performs a correlation of the real and imaginary sequences with corresponding parts of a stored frame-sync pseudo-random sequence. Phase correction is based on the maximum real and imaginary values of the correlation. The signal is typically quadrature amplitude modulated signal is modulated using punctured trellis codes. Quadrature phase shift keying modulation, 16-QAM, 64-QAM and other QAM schemes may be used.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.

Abstract: A system recovers a local media clock from a master media clock based on time-stamped packets received from a transmitter. The packets may include audio, video, or a combination of both, sampled at a rate determined by the master media clock at the transmitter. Timestamps in the packets may be based on values of a remote real-time counter at the transmitter that is synchronized with a local real-time counter at a receiver. The local media clock may be syntonized with the master media clock through the clock periods. The clocks may be synchronized by syntonizing the clocks and adjusting the phase of the local media clocks based on timestamps and a real-time counter.

Abstract: An improved system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty. The proposed system and method perform clock recovery by including an improvement in the form of dynamically varying thresholds. Reconstruction of the clock signal is performed in accordance with the minimum network delay estimation based on an adjustable threshold, i.e., the latency change threshold, which increases when the noise threshold increases and decreases when the noise threshold decreases.

Abstract: A control circuit receives a first clock signal at a first frequency, a frequency division signal specifying a divisor number, and a second clock signal at a second frequency (higher than the first frequency). The control circuit includes a phase control block that defines non-overlapping portions of a pulse of the second clock to include center, left and right portions. A determination is then made as to whether an edge of the first clock is located within the center portion. In response to such a determination, a number of periods of the second clock signal which occur within one or more periods of the first clock signal is compared to a number derived from the divisor number to generate a frequency selection signal indicative of that comparison. A controlled oscillator circuit generates the second clock signal at the second frequency, wherein the second frequency is specified by the frequency selection signal.

Abstract: Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

Abstract: An apparatus for sampling clock recovery (SCO) and methods for estimating and compensating SCO are provided. The apparatus comprises a symbol timing adjustment module for shifting forward or backward symbol timing of the transmitted OFDM symbols; a discrete Fourier transform (DFT) processor for performing DFT to an output from the symbol timing adjustment module; a channel estimator for undertaking a channel frequency response estimation based on a channel estimation sequence; a SCO phase rotator for receiving and performing phase shift on the transmitted OFDM symbols of a frame header and a frame payload; an SCO estimation stage for undertaking an SCO estimation based on a pilot-subcarrier-related output of the SCO phase rotator and the CFR estimation; and an SCO compensation distributor for dividing the SCO estimation into integer and fractional portions and then distributing them into the symbol timing adjustment module and the SCO phase rotator, respectively.

Abstract: Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.