Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.

Abstract: Disclosed herein is a mobile terminal and an operation control method thereof in which a delay time of the screen lock execution is controlled according to the type of application, thereby improving the inconvenience of a user interface and effectively managing a battery according to an interrupt when required to continuously receive an input from the user or continuously provide visual information to the user. For this purpose, a mobile terminal according to an embodiment of the present disclosure may include an input unit configured to receive a user input; an execution controller configured to execute screen lock if the user input is not received for a predetermined time; and a change controller configured to change the predetermined time based on a type of application.

Abstract: A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases.

Abstract: Provided are a clock regeneration circuit and a receiver, wherein difference values (V1, V2, V3) from an ideal value can be obtained for respective three sample data (T1, T2, T3) which are obtained by oversampling a 4-level FSK demodulated signal at a higher frequency than that of a symbol clock and in which sample data (T2) at a symbol point (P) is included at a median, and a sampling timing of the symbol point (P) is shifted toward a point where the sample data (T3) having a smaller difference value is obtained, by a time corresponding to the difference value (V2) at the symbol point. Thus, the clock regeneration circuit and the receiver are capable of regenerating a stable clock from multi-level modulated waves in a small calculation amount.

Abstract: In one embodiment of the invention, an apparatus may comprise a memory to receive original video data that includes a continuity of time stamps and a discontinuity of time stamps. A processor may shift a first time stamp from the continuity of time stamps to the discontinuity of time stamps by an adaptively modified distance and play the shifted time stamp in a smooth fashion.

Abstract: A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract: Waveform data of selected bits having jitter or noise is generated wherein the waveform date represents a serial digital signal. A signal generator displays a jitter/noise setting area and a bit selection area on a display device where jitter or noise is set and the jitter or noise settings are applied to only the bit selected with the bit selection area. The bit is selected through various ways. A user may directly input a bit pattern to be selected. Box objects corresponding to the respective bits in the digital signal may be displayed and one or more of the bits can be selected by selecting one of the box objects. Frequently used bit patterns may be stored and provided using a menu-driven interface for selecting a bit pattern. An arbitrary number of consecutive bits may be designated for receiving jitter or noise and displayed.

Abstract: A first phase adjustment circuit adjusts phases of a data decision clock signal and a first boundary decision clock signal according to a phase adjustment amount based on an output signal of a data decision circuit and an output signal of a first boundary decision circuit. A second phase adjustment circuit adjusts a phase of a second boundary decision clock signal according to a result of adding the phase adjustment amount and a phase adjustment amount offset. An adaptive equalization control circuit adjusts an equalization coefficient of an equalization circuit according to a data width of an output signal of the equalization circuit based on a logical comparison result between the output signal of the data decision circuit and an output signal of a second boundary decision circuit when the phase adjustment amount offset is changed.

Abstract: What is disclosed is a method of operating a communication system. The method includes receiving a request to initiate a communication session with a wireless communication device, wherein the request indicates an application type. The method also includes determining a spreading code based on the application type, and transferring the spreading code to the wireless communication device. The method also includes receiving communications for the communication session encoded with the spreading code and decoding the encoded communications based on the spreading code.

Abstract: An acquisition module includes a coherent correlator configured to receive a transmission having a pilot signal and correlate the received transmission with a local copy of the pilot signal to produce a first output, a delayed correlator configured to delay the first output and correlate the first output with the delayed first output to produce a second output, and a detector configured to detect the pilot signal in the transmission based on the second output.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A passive phase jitter modulation (PJM) tag is charged with power in a continuous wave (CW) section. When receiving a command from a reader, the passive PJM tag must recognize the command and determine exactly when to begin demodulating the command. Only then can the passive PJM tag demodulate the command. To this end, a synchronization apparatus for accurately demodulating a signal input to a PJM tag includes a plurality of correlators correlating a received phase jitter-modulated signal with a template of an internal matched filter which is in the same form as at least a portion of a modified frequency modulation (MFM) flag.

Abstract: A method and an arrangement for cycle slip detection for timing recovery of a received analog signal including asynchronously sampled digital data are implemented with a timing recovery control loop using a technique known as interpolated timing recovery and improved cycle slip detection as well as improved cycle slip correction based on said cycle slip detection. The method includes using an output signal of the loop filter in the control loop for timing recovery, generating averaged timing error values from said filtered timing error signal and accumulating changes of the averaged timing error values in adjacent blocks of samples which exceed a first threshold. Accumulated averaged timing error changes of adjacent blocks which exceed a second threshold are then declared as cycle slip and the number of cycle slips is determined by a third threshold being a tolerance threshold.

Abstract: A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.

Abstract: The present invention relates to the communication field and discloses a method and an apparatus for implementing pulse synchronization, so that the control on a single-chip multi-channel device can be simplified. A method for implementing pulse synchronization includes: when a cycle count value corresponding to a reference symbol port of the multiple ports reaches a length of a predetermined pulse cycle, obtaining, by a microprocessor, cycle count values corresponding to the multiple ports; obtaining lengths of temporary synchronization cycles of the multiple ports according to the length of the predetermined pulse cycle and the cycle count values corresponding to the multiple ports; and sending the lengths of the temporary synchronization cycles to logic circuits corresponding to the multiple ports. Embodiments of the present invention are mainly applied in communication systems to output pulse symbols synchronously.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: The present invention describes methods and circuitry for a sub-rate bang-bang phase detector, in which the reference clock has frequency that is a fraction of the bit rate of the received data stream. The sub-rate bang-bang phase detector is enabled by multiple phases of the reference clock.

Abstract: While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.

Abstract: A clock regeneration circuit according to the present invention that generates a clock signal that is synchronized to an input signal, includes: a detection section which detects points at which the input signal transitions; a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal; a calculation processing section which generates a second histogram by calculation processing based on the first histogram, and calculates a phase adjustment value of the clock signal based on the second histogram; and a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value.

Abstract: Transmission of information between user equipment (UE) and base stations in a wireless network occurs using a stream of periodic data. A modem in the UE operates synchronized to a first clock source to produce the stream of periodic data at a chip rate. Transceiver circuitry is synchronized to a variable clock source to receive the stream of data from the first circuitry at a rate according to the variable clock source. A fixed phase relationship is maintained between the variable clock source and the first clock source while the data period is uniform by adjusting the variable clock in response to detected phase errors. Occasionally, one period of the periodic data is changed by a defined amount. The fixed phase relationship is restored over a number of periods in a gradual manner by changing the frequency of the variable clock by an amount. By restoring the phase relationship gradually, quality degradation of the transmitted signal is reduced.

Abstract: An intermittent operative communication apparatus can send data, received from a source communication device, to any receiver communication device at a predetermined interval and wait for receiving data at the predetermined interval. The communication apparatus has a selector for selecting one or multiple receiver communication devices as a reference communication device that gives a reference timing at which the communication apparatus waits for receiving data, and a timing controller for setting a timing, at which the communication apparatus waits for receiving data, to a timing according to operation of any reference communication device.

Abstract: In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop utilizes a frequency error estimator implemented as a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps, and a loop filter implemented as a series combination of an adaptive-bandwidth filter and a proportional-integral controller.

Abstract: A demodulating circuit includes: a fast Fourier transform circuit which fast Fourier transforms a received signal and outputs a plurality of carrier signals; an output selecting circuit which selects at least two signals from the plurality of carrier signals, the at least two signals including a first signal modulated in accordance with a first modulation method and a second signal modulated in accordance with a second modulation method; an inverse fast Fourier transform circuit which inverse Fourier transforms transmission path characteristic values including a first transmission path characteristic value obtained based on the first signal and a second transmission path characteristic value obtained based on the second signal; and an FFT window control circuit which controls a position of an FFT window based on the inverse Fourier transformed transmission path characteristic values.

Abstract: In one embodiment, an apparatus comprises an adaptive filter, a timing recovery unit, and a reverse interpolation filter. The adaptive filter has adaptive filter coefficients that are adjusted based on a first error signal at a first sample rate and filters a first signal at the first sample rate to obtain a second signal at the first sample rate. The timing recovery unit interpolates the second signal at the first sample rate to obtain a third signal at a second sample rate; and estimates a partial response signal at the second sample rate corresponding to the third signal. The a reverse interpolation filter interpolates a second error signal at the first sample rate, which is a difference between the third signal and the partial response signal, to obtain the first error signal at the first sample rate for feeding back to the adaptive filter.

Abstract: Disclosed is an adaptive modulation scheme and apparatus thereof using an Analog/Digital (AJO) converter with variable bit resolution or clock frequency, the A/D converter including a transmitter including a modulator to modulate data to be transmitted according to a modulation scheme received from a receiver, an A/D converter to convert the modulated data into an analog signal using a bit resolution or a clock frequency received from the receiver, and a radio frequency (RF) processor to transmit the analog signal to the receiver through a wireless channel and a receiver including an RF processor to receive data through a wireless channel, a calculator to calculate a Signal to Noise Ratio (SNR) of the data received through the RF processor, and a modulation controller to search a predetermined setting table for a corresponding modulation scheme and bit resolution using the calculated SNR and to transmit to a transmitter.

Abstract: An image reading device including: a photoelectric conversion device that outputs an analog signal corresponding to an image read from a document; an A-D converter that converts the analog signal into a digital signal; a spread spectrum clock generation unit configured to generate a spread spectrum clock by executing frequency-modulation on a reference clock having a constant frequency; an acquisition timing setting unit configured to set an acquiring timing of the analog signal with reference to the spread spectrum clock; and an acquisition timing correction unit configured to execute a delay correction for the acquiring timing of the analog signal set by the acquisition timing setting unit in accordance with a frequency of the spread spectrum clock defined when the analog signal is outputted. The analog signal acquired at the corrected acquiring timing corrected by the acquisition timing correction unit is converted into the digital signal.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: Methods and apparatuses for reducing noise in frequency to digital converters (FDCs). An FDC apparatus includes a first FDC, a second FDC and a combiner. The first and second FDCs are configured to independently sample an input signal according to a sample clock to generate first and second digital signals, each representing the instantaneous frequency of the input signal. The combiner is configured to form a resultant digital signal from the first and second digital signals. The first and second FDCs are designed and combined in the noise-canceling FDC apparatus so that the first and second signals they generate have correlated noise profiles in a frequency range of interest. When combined by the combiner to form the resultant digital signal, the resultant digital signal has a signal power to noise power ratio greater than the signal power to noise power ratios characterizing the first and second digital signals of the individual first and second FDCs.

Abstract: Integrated circuits with data communications circuitry are provided. The data communications circuitry on an integrated circuit may receive data that was transmitted from another integrated circuit at a data rate. The data communications circuitry may include oversampling circuitry that oversamples the data to produce an oversampled version of the data at an oversampled data rate. Downsampling circuitry in the data communications circuitry may be used to downsample the oversampled data. The downsampling circuitry may include cascaded groups of registers that store the oversampled data. The outputs of each of the groups of registers may be combined to form a combined parallel output. A downsampling control circuit may have a multiplexer that selects a subset of the signals from the combined parallel output in response to control signals from a transition detector. A middle bit detector may extract a bit value from the selected subset to use as the downsampled output.

Abstract: A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of dynamically variable delay circuits each has a plurality of predetermined delay amounts. Clocked circuits are coupled to respective clock signals provided by respective phase-locked loops. A performance detector is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops. The phase-locked loops are turned off and on and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract: A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2?. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.

Abstract: A method of frequency search for a digitally controlled oscillator (DCO) with multiple sub-bands. The method comprises providing multiple workable pre-control codes, each control code comprising a most significant bit (MSB), corresponding to each frequency of the DCO for selection, selecting one of the workable pre-control codes according to the MSBs thereof, and providing the selected control code to the DCO.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment comprises observing a digital signal from within an RF circuit, manipulating the signal with digital signal processing techniques, and determining if the RF circuit passes a test based upon results from the manipulating. Since the signal is clocked at a much lower frequency than an RF output of the RF circuit and the manipulation is performed digitally, testing can be performed at different stages of the production cycle and expensive test equipment can be eliminated.

Abstract: A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Abstract: A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Abstract: A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Abstract: A transmitting/receiving system and a data processing method of the same are disclosed herein. The receiving system may include a receiving unit, a first processing unit, and a second processing unit. The receiving unit receives a broadcast signal including mobile service data and an FIC segment from at least one slot. The first processing unit acquires FIC segments from the broadcast signal and obtains an FIC chunk, wherein the obtained FIC chunk is configured of a chunk header and a chunk payload. Herein, the chunk header may include FIC chunk major protocol version information and FIC chunk minor protocol version information, and the chunk payload may include signaling information between at least one ensemble and at least one mobile service. The second processing unit processes the FIC chunk based upon the FIC chunk major protocol version information and the FIC chunk minor protocol version information.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and transmits a deskew signal related to the multi-level-coded signals. The communication system also includes a receiving apparatus with a decoding section that decodes the multi-level-coded signals to generate decoded signals, and a deskew processing section that performs deskew processing for compensating skew among the decoded signals of the multiple channels. The deskew signal generation section generates the deskew signal that has been framed by extracting a part of the data from each of the channels of the input signals, adding framing data for enabling a receiving apparatus to recognize which channel the extracted data has been extracted from, and performing rate conversion.

Abstract: Certain embodiments of the present disclosure relate to a method for tracking of a carrier frequency offset. A soft combined frequency tracking discriminator is proposed as a part of the closed loop structure that can provide fast tracking of the frequency offset in an initial pull-in mode, and can also track small residual frequency variance in a fine-tracking mode.

Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

Abstract: An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.