Abstract: A method of manufacturing a multi-chip module includes: securing a plurality of chips on a surface of a flat-shaped member through a solder bump; connecting the plurality of chips with each other by a bonding wire, at surfaces, opposite to the flat-shaped member side, of the plurality of chips; and electrically connecting the plurality of chips with a board, at the surfaces, opposite to the flat-shaped member side, of the plurality of chips.

Abstract: A hybrid multilayer substrate in an electronic package. The substrate includes a first portion having m layers and a second portion having n layers such that m is less than n. The first portion has a first height and the second portion has a second height. The first height is different than the second height. In another embodiment, a surface is formed between the first portion and the second portion, and a shielding material can be applied to the surface. In a different embodiment, the hybrid multilayer substrate is manufactured for shielding a first die from a second die.

Abstract: A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board.

Abstract: Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract: An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract: A device and a method for realizing reliable electrical contacts at low temperature and low pressure between conducting materials on, for example, different substrates are disclosed. In one aspect, a rough and brittle intermetallic layer is formed on a conducting material on a first substrate. A soft solder material layer on the other substrate is used for contacting the brittle and rough intermetallic layer that will break. As the solder material is relatively soft, contact between the broken intermetallic layer and the solder material can be realized over a large portion of the surface area. At that stage, a second intermetallic layer is formed between the solder material and the first intermetallic layer realizing electrical contact.

Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 ?m or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract: Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Abstract: Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die.

Abstract: A flip chip package may include package substrate, a semiconductor chip, conductive bumps, a molding member and a heat sink. The semiconductor chip may be arranged over an upper surface of the package substrate. The conductive bumps may be interposed between a lower surface of the semiconductor chip and the upper surface of the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The heat sink may make contact with the semiconductor chip to dissipate a heat in the semiconductor chip. An ultrasonic wave may pass through only one interface between the semiconductor chip and the molding member, so that scattering of the ultrasonic wave may be suppressed.

Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Abstract: A light emitting die package is provided which includes a metal substrate having a first surface and a first conductive lead on the first surface. The first conductive lead is insulated from the substrate by an insulating film. The first conductive lead forms a mounting pad for mounting a light emitting device. The package includes a metal lead electrically connected to the first conductive lead and extending away from the first surface.

Abstract: A semiconductor device can include a semiconductor chip, a protective layer pattern, an under bump metallurgy (UBM) layer, and conductive bumps. The semiconductor chip can include a pad and a guard ring. The protective layer pattern can be formed on the semiconductor chip to expose the pad and the guard ring. The UBM layer can be formed on the protective layer and can directly make contact with the pad and the guard ring. The conductive bumps can be formed on a portion of the UBM layer on the pad. Thus, the UBM layer and the guard ring can directly make contact with each other, so that a uniform current can be provided to the UBM layer on the pad regardless of a thick difference of different portions of the UBM layer.

Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.

Abstract: A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.

Abstract: A chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for voltage supply, and a fuse (3) that electrically connects the internal supply connection (VBAT) and is arranged within the chip design (1).

Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

Abstract: A sapphire wafer dividing method including a cut groove forming step of forming a plurality of cut grooves on the back side of a sapphire wafer along a plurality of crossing division lines formed on the front side where a light emitting layer is formed, a modified layer forming step of forming a plurality of modified layers inside the sapphire wafer along the division lines, and a dividing step of dividing the sapphire wafer into individual light emitting devices along the modified layers as a division start point, thereby chamfering the corners of the back side of each light emitting device owing to the formation of the cut grooves in the cut groove forming step.

Abstract: There is provided a semiconductor device and a manufacturing method therefor, the semiconductor device requiring flip-chip mounting of a fine pitch electrode, wherein the fine electrode is easily manufactured, resin sealing is not required, and reliability can be improved. In the semiconductor device, one or more LSI chips (1), having an insulating layer (3) surface and an electrode (2) surface on one side, and a substrate (4), having an insulating layer (6) surface and an electrode (5) surface on one side, are bonded by having surfaces of the electrodes and surfaces of the insulating layers face each other via a bonding layer (7) made in a thin film form, in a region excluding the surfaces of the electrodes (2, 5) and the surfaces of the insulating layers (3, 6) in areas surrounding the electrodes.

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Abstract: A semiconductor device includes a semiconductor chip having an element formation surface on which at least one element is formed and including a plurality of electrode pads formed on the element formation surface, an interconnect substrate having a principal surface facing the element formation surface of the semiconductor chip and including a plurality of connection pads formed at positions of the principal surface facing the respective corresponding electrode pads, and a plurality of solder bumps provided between the respective corresponding electrode pads and connection pads, and configured to electrically connect the respective corresponding electrode pads and connection pads together. An UBM layer is formed on a portion of each solder bump closer to the corresponding electrode pad and a barrier metal layer is formed on a portion of each solder bump closer to the corresponding connection pad, and the two layers have substantially the same composition of major materials.

Abstract: The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on the back surface of a semiconductor element to be flip chip-connected onto an adherend, the film containing a resin and a thermoconductive filler, in which the content of the thermoconductive filler is at least 50% by volume of the film, and the thermoconductive filler has an average particle size relative to the thickness of the film of at most 30% and has a maximum particle size relative to the thickness of the film of at most 80%.

Abstract: An electronic device includes a wiring board; a semiconductor device arranged at an upper side of the wiring board with an electrically conductive member being arranged therebetween; a covering member arranged at an upper side of the semiconductor device; and a supporting member arranged at a lower side of the wiring board, the supporting member having a convex portion facing the wiring board, the supporting member being connected to the covering member and supporting the wiring board at the convex portion.

Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Abstract: An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

Abstract: Thermally induced stress in a semiconductor die, i.e., in a complex metallization system thereof, may be reduced by “dividing” a package substrate into two or more substrate sections, which may have formed therebetween an appropriate stress buffer region, for instance a region of superior resiliency. In this case, the total deformation of the package substrate may be reduced, thereby also reducing the thermally induced stress forces in the complex metallization system of the semiconductor die. Hence, for a given size and complexity of a metallization system, an increased production yield and superior reliability may be achieved.

Abstract: Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Abstract: A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a component area on a first main surface of the first substrate, and wherein first contact pads are arranged outside of the component area, forming an open top frame structure around the component area on the first main surface of the first substrate, providing a second substrate having second contact pads, arranged symmetrically to the first contact pads and electrically and mechanically connecting the first main surface of the first substrate with the first main surface of the second substrate, so that the frame structure and the second substrate from a cavity or recess around the electronic component on the first substrate.

Abstract: A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.

Abstract: A semiconductor device has a plurality of semiconductor die mounted to a carrier. An adhesive material is deposited over a portion of the semiconductor die and carrier to secure the semiconductor die to the carrier. The adhesive material is deposited over a side of the semiconductor die and over a surface of the carrier. The adhesive material can be deposited over a corner of the semiconductor die, or over a side of the semiconductor die, or around a perimeter of the semiconductor die. An encapsulant is deposited over the semiconductor die and carrier. The adhesive material reduces shifting of the semiconductor die with respect to the carrier during encapsulation. The adhesive material is cured and the carrier is removed. The adhesive material can also be removed. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die are singulated through the encapsulant and interconnect structure.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.

Abstract: A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.

Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Abstract: The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane.

Abstract: Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating has a major outer surface at a second distance from the first side of the support member. The second distance is approximately the same as the first distance such that the outer surface of the protective coating is generally co-planar with the outer surface of the bond sites carried by the projection.

Abstract: A method for rejoining an IC die, removed from an existing substrate, to a new substrate, is disclosed herein. In one embodiment, such a method includes grinding an existing substrate from an IC die to create a substantially planar surface exposing interconnects and surrounding underfill material. A new substrate is provided having electrically conductive pedestals protruding therefrom. The electrically conductive pedestals are positioned to align with the exposed interconnects and have a melting point substantially higher than the melting point of the interconnects. The method places the exposed interconnects in contact with the electrically conductive pedestals. The method then applies a reflow process to melt and electrically join the exposed interconnects with the electrically conductive pedestals. A structure produced by the method is also disclosed.

Abstract: The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film having a light transmittance at a wavelength of 532 nm or 1064 nm of 20% or less, and having a contrast between a marking part and a part other than the marking part after laser marking of 20% or more.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of the individual dies facing toward the substrate and with a plurality of terminals on the active side of the individual dies aligned with corresponding holes in the substrate. The singulated dies are attached to the substrate after forming the holes in the substrate.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.