Flip-chip-type Assembly Patents (Class 438/108)
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Patent number: 8748228Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.Type: GrantFiled: August 17, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tongsuk Kim, Jangwoo Lee, Heeseok Lee, Kyoungsei Choi
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Patent number: 8749056Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.Type: GrantFiled: May 26, 2011Date of Patent: June 10, 2014Assignee: Infineon Technologies AGInventors: Daniel Kehrer, Stefan Martens, Tze Yang Hin, Helmut Wietschorke, Horst Theuss, Beng Keh See, Ulrich Krumbein
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Patent number: 8745860Abstract: A method for manufacturing a printed wiring board includes forming on a support board a first resin insulation layer, forming a second resin insulation layer on the first resin insulation layer, forming in the second resin insulation layer an opening portion in which an electronic component having an electrode is mounted, accommodating the electronic component in the opening portion of the second resin insulation layer such that the electrode of the electronic component faces an opposite side of the first resin insulation layer, forming on the first surface of the second resin insulation layer and the electronic component an interlayer resin insulation layer, and forming in the interlayer resin insulation layer a via conductor reaching to the electrode of the electronic component.Type: GrantFiled: February 29, 2012Date of Patent: June 10, 2014Assignee: Ibiden Co., Ltd.Inventor: Tsuyoshi Inui
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Patent number: 8748229Abstract: A semiconductor device includes a supporting board, a first semiconductor element mounted on a main surface of the supporting board; and an electronic component provided between the supporting board and the first semiconductor element; wherein the supporting board includes a concave part formed in a direction separated from the first semiconductor element; and at least a part of the electronic component is accommodated in the concave part.Type: GrantFiled: August 23, 2012Date of Patent: June 10, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Takayuki Norimatsu
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Patent number: 8748227Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.Type: GrantFiled: September 9, 2008Date of Patent: June 10, 2014Assignee: Megit Acquisition Corp.Inventors: Jin-Yuan Lee, Ching-Cheng Huang, Mou-Shiung Lin
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Publication number: 20140151873Abstract: A semiconductor device including a first semiconductor chip and a second semiconductor chip which are bump bonded to each other with a clearance therebetween sealed with resin injected from a prescribed position on the first semiconductor chip in a manner that a space between bumps formed by bump bonding is filled with the resin, and a plurality of concave and convex sections which are formed on a surface side of the first semiconductor chip, the surface being bonded with the second semiconductor chip, and have a protruding section which straddles at least one convex section out of convex sections of the plurality of concave and convex sections formed in a surrounding section of a bonding region between the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: September 4, 2013Publication date: June 5, 2014Applicant: Sony CorporationInventors: Takayuki Tanaka, Kana Iwami
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Publication number: 20140151880Abstract: Embodiments of the present disclosure provide a package on package arrangement comprising a first package including a substrate layer including a top side, and a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface, and a first die coupled to the bottom side of the substrate layer. The arrangement also comprises a second package including a plurality of rows of solder balls and at least one of one or both of an active component or a passive component. The second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package. The active component and/or a passive component is attached to the substantially flat surface of the top side of the substrate layer of the first package.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: Marvell World Trade Ltd.Inventors: Huahung Kao, Shiann-Ming Liou
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Publication number: 20140154838Abstract: In one embodiment the mounting apparatus mounts an upper chip on a lower chip, and thermally presses the upper chip with the lower chip. The mounting apparatus includes a first movement part for mounting the upper chip on the lower chip and preliminarily bonding by thermal pressing, and a second movement part for mainly bonding the plurality of upper chips preliminarily bonded with the plurality of lower chips for a longer time. The second movement part thermally presses the upper chips preliminarily bonded on the lower chip in a state that the upper chips are adsorbed on an adsorption surface parallel to a loading surface of the lower chip on which the upper chips are loaded.Type: ApplicationFiled: December 4, 2013Publication date: June 5, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yukimori YOSHIAKI, Kajinami MASATO, Ueyama SHINJI
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Patent number: 8742559Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.Type: GrantFiled: March 14, 2012Date of Patent: June 3, 2014Assignee: Renesas Electronics CorporationInventor: Noriyuki Takahashi
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Patent number: 8743561Abstract: An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.Type: GrantFiled: June 11, 2010Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Bo-I Lee, Chien-Hsiun Lee
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Patent number: 8739402Abstract: A method of manufacture of an electrical bridge including the following steps: (a) providing a first flexible electrically insulating material, (b) laminating a pattern of a second electrically conductive material, on the first material, (c) separating a strap having a connection portion formed from the pattern of electrically conductive material.Type: GrantFiled: December 17, 2008Date of Patent: June 3, 2014Assignee: Microconnections SASInventors: Jean Pierre Radenne, Christophe Mathieu, Laurent Berdalle
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Patent number: 8741762Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: GrantFiled: October 21, 2013Date of Patent: June 3, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Hao Liu, Yi Sheng Anthony Sun, Ravi Kanth Kolan, Chin Hock Toh
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Patent number: 8741691Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.Type: GrantFiled: April 20, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chung Yee, Chun Hui Yu
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Patent number: 8742603Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.Type: GrantFiled: September 15, 2010Date of Patent: June 3, 2014Assignee: QUALCOMM IncorporatedInventors: Omar J. Bchir, Milind P. Shah, Sashidhar Movva
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Patent number: 8736002Abstract: The sensor assembly comprises a substrate (1), such as a flexible printed circuit board, and a sensor chip (2) flip-chip mounted to the substrate (1), with a first side (3) of the sensor chip (2) facing the substrate (1). A sensing area (4) and contact pads (5) are integrated on the first side (3) of the sensor chip (2). Underfill (18) and/or solder flux is arranged between the sensor chip (2) and the substrate (1). The sensor chip (2) extends over an edge (12) of the substrate (1), with the edge (12) of the substrate (1) extending between the contact pads (5) and the sensing area (4) over the whole sensor chip (2). A dam (16) can be provided along the edge (12) of the substrate (1) for even better separation of the underfill (18) and the sensing area (4). This de sign allows for a simple alignment of the sensor chip on the substrate (1) and prevents underfill (18) from covering the sensing area (4).Type: GrantFiled: November 18, 2009Date of Patent: May 27, 2014Assignee: Sensirion AGInventors: Markus Graf, Werner Hunziker, Franziska Brem, Felix Mayer
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Publication number: 20140141568Abstract: A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill.Type: ApplicationFiled: January 24, 2014Publication date: May 22, 2014Applicant: INVENSAS CORPORATIONInventors: Kazuo Sakuma, Ilyas Mohammed, Philip Damberg
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Publication number: 20140138826Abstract: A bare-die first package includes a patterned insulating layer that exposes first package balls in vias. The vias enable a second package to be positioned on the first package in a proper ball-to-ball alignment without the need for flattening or coining.Type: ApplicationFiled: March 8, 2013Publication date: May 22, 2014Applicant: Qualcomm IncorporatedInventor: Rajneesh Kumar
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Publication number: 20140141544Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Meow Koon Eng, Sui Waf Low, Min Yu Chan, Yong Poo Chia, Bok Leng Ser, Wei Zhou
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Publication number: 20140141567Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Inventors: Lei Shi, Yan Xun Xue, Yuping Gong
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Publication number: 20140138827Abstract: According to various embodiments, a flip chip package structure is provided in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer.Type: ApplicationFiled: January 27, 2014Publication date: May 22, 2014Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas
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Patent number: 8730676Abstract: A composite component includes a first joining partner, at least one second joining partner and a first joining layer situated between the first joining partner and the second joining partner. In addition to the first joining layer, at least one second joining layer is provided between the first and the second joining partner; and at least one intermediate layer is situated between the first and the second joining layer.Type: GrantFiled: January 25, 2010Date of Patent: May 20, 2014Assignee: Robert Bosch GmbHInventors: Michele Hirsch, Michael Guenther
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Patent number: 8728845Abstract: The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask.Type: GrantFiled: March 24, 2011Date of Patent: May 20, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Lin, Ping-Yin Liu, Lan-Lin Chao, Jung-Huei Peng, Chia-Shiung Tsai
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Patent number: 8728864Abstract: A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SDâ„¢ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.Type: GrantFiled: November 26, 2012Date of Patent: May 20, 2014Assignee: SanDisk Technologies Inc.Inventors: Ning Ye, Robert C. Miller, Cheemen Yu, Hem Takiar, Andre McKenzie
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Patent number: 8722517Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray.Type: GrantFiled: April 18, 2011Date of Patent: May 13, 2014Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Goji Shiga, Fumiteru Asai, Toshimasa Sugimura
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Patent number: 8723318Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.Type: GrantFiled: December 11, 2012Date of Patent: May 13, 2014Assignee: Tessera, Inc.Inventor: Belgacem Haba
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Patent number: 8716875Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.Type: GrantFiled: January 18, 2013Date of Patent: May 6, 2014Assignee: Marvell World Trade Ltd.Inventor: Sehat Sutardja
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Patent number: 8716859Abstract: A flip chip package structure is proposed in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer.Type: GrantFiled: January 10, 2012Date of Patent: May 6, 2014Assignee: Intel Mobile Communications GmbHInventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas
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Publication number: 20140117523Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Inventors: Yueh-Se Ho, Yan Xun Xue, Hamza Yilmaz, Jun Lu
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Publication number: 20140120661Abstract: Disclosed are various flip chip packaging methods. In one embodiment, a method can include: (i) arranging a plurality of pads on a chip; (ii) arranging a plurality of first connecting structures on the plurality of pads, where each of the first connecting structures comprises a first metal; (iii) arranging a plurality of second connecting structures on the plurality of first connecting structures, where each second connecting structure comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal; and (iv) flipping the chip with the first and second connecting structures and arranging corresponding of the second connecting structures on pads of a substrate to form electrical connection between the chip and the substrate via the first and second connecting structures.Type: ApplicationFiled: August 26, 2013Publication date: May 1, 2014Applicant: Silergy Semiconductor Technology (Hangzhou) LTDInventor: Xiaochun Tan
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Publication number: 20140117535Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
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Publication number: 20140120662Abstract: The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved.Type: ApplicationFiled: December 17, 2013Publication date: May 1, 2014Applicant: Spansion LLCInventor: Masanori ONODERA
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Patent number: 8710643Abstract: The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.Type: GrantFiled: February 2, 2011Date of Patent: April 29, 2014Assignee: Altera CorporationInventors: Teck-Gyu Kang, Yuan Li, Yuanlin Xie
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Patent number: 8709935Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.Type: GrantFiled: February 15, 2013Date of Patent: April 29, 2014Assignee: STATS ChipPAC, Ltd.Inventors: DaeSik Choi, OhHan Kim, SungWon Cho
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Patent number: 8709867Abstract: A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.Type: GrantFiled: March 5, 2012Date of Patent: April 29, 2014Assignee: Alpha & Omega Semiconductor Inc.Inventors: Kai Liu, Lei Shi, Jun Lu, Anup Bhalla
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Patent number: 8709869Abstract: A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.Type: GrantFiled: September 14, 2012Date of Patent: April 29, 2014Assignee: Intel CorporationInventors: John J. Beatty, Jason A. Garcia
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Patent number: 8709866Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.Type: GrantFiled: August 9, 2013Date of Patent: April 29, 2014Assignee: Micron Technology, Inc.Inventors: Setho Sing Fee, Lim Thiam Chye, Tongbi Jiang
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Patent number: 8709940Abstract: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.Type: GrantFiled: March 11, 2011Date of Patent: April 29, 2014Assignee: Unimicron Technology Corp.Inventors: Shing-Ru Wang, Hsien-Shou Wang, Shih-Ping Hsu
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Publication number: 20140113411Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.Type: ApplicationFiled: December 20, 2013Publication date: April 24, 2014Applicant: Spansion LLCInventors: Naomi MASUDA, Masataka HOSHINO, Ryota FUKUYAMA
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Publication number: 20140110863Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: ApplicationFiled: September 10, 2013Publication date: April 24, 2014Applicant: International Rectifier CorporationInventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 8703600Abstract: An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.Type: GrantFiled: March 11, 2010Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Takashi Togasaki
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Patent number: 8703537Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.Type: GrantFiled: September 18, 2013Date of Patent: April 22, 2014Assignee: NeuroNexus Technologies, Inc.Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, Kc Kong, Rio J. Vetter, Mayurachat Ning Gulari
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Patent number: 8703534Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.Type: GrantFiled: January 29, 2012Date of Patent: April 22, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Kriangsak Sae Le
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Patent number: 8703541Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.Type: GrantFiled: April 6, 2012Date of Patent: April 22, 2014Assignee: Stats Chippac Ltd.Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
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Patent number: 8703540Abstract: A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.Type: GrantFiled: January 15, 2013Date of Patent: April 22, 2014Assignee: Semtech CorporationInventors: Andrew J. Bonthron, Darren Jay Walworth
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Patent number: 8703533Abstract: A semiconductor package includes a substrate having a connection terminal with a groove on its surface. Nanopowder may be disposed on a bottom of the groove. A semiconductor chip may be flip-chip bonded to the substrate by the nanopowder. A filler member may be interposed between the substrate and the semiconductor chip.Type: GrantFiled: December 28, 2011Date of Patent: April 22, 2014Assignee: SK Hynix Inc.Inventor: Si Han Kim
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Patent number: 8703539Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.Type: GrantFiled: June 29, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsiun Lee, Kai-Chiang Wu
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Patent number: 8698303Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: GrantFiled: September 30, 2011Date of Patent: April 15, 2014Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi
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Patent number: 8698324Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface contains a black pigment.Type: GrantFiled: December 22, 2010Date of Patent: April 15, 2014Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Takeshi Matsumura, Goji Shiga
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Patent number: 8697492Abstract: A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element.Type: GrantFiled: November 2, 2010Date of Patent: April 15, 2014Assignee: Tessera, Inc.Inventors: Belgacem Haba, Ilyas Mohammed, Ellis Chau, Sang Il Lee, Kishor Desai
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Patent number: 8697493Abstract: Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods.Type: GrantFiled: July 18, 2011Date of Patent: April 15, 2014Assignee: SoitecInventor: Mariam Sadaka