Abstract: A method of treating a lead in a chip package. A conductive lead is positioned such that it extends across a gap in a dielectric substrate and is secured at either end to a first surface of the substrate. Directed energy is then applied to a desired portion of the surface of the lead within the gap. As a result of the application of energy, a surface layer of the lead is recrystallized thereby creating a fine grain, dense surface layer of lead material. Surface contaminates may be vaporized and contaminants at the grain boundaries of the recrystallized surface layers may be driven away from the grain boundaries such that a treated lead is more ductile and has better resistance to thermal cycling after the lead has been attached to a chip contact.

Abstract: A method and apparatus for connecting a lead of a lead frame to a contact pad of a semiconductor chip using a laser or other energy beam is herein disclosed. The lead may be wire bonded to the contact pad by heating the ends of a wire until the wire fuses to the contact pad and lead or an energy-fusible, electrically-conductive material may be used to bond the ends of the wire to the contact pad and lead. In addition, this invention has utility for both conventional lead frame/semiconductor chip configurations and lead-over-chip configurations. In addition, with a lead-over-chip configuration, the lead may be directly bonded to the contact pad with a conductive material disposed between the lead and the contact pad.

Abstract: A universal substrate includes an input/output (I/O) layer having a fixed I/O assignment of I/O locations for connection with a printed circuit board or the like. A chip receiving layer is provided for receiving one of at least two different but allied semiconductor chips, wherein each of the at least two different but allied chips include a set of bond pads and have a unique wire-out requirement. A first layer includes a plurality of bond pads and vias, the plurality of bond pads including at least two sets of bond pads, wherein each set is adapted for bond connection with a respective one of the at least two different semiconductor chips when received by said receiving means and further in accordance with a respective wire-out requirement.

Abstract: A method of manufacturing a lead frame comprises the steps of preparing a three-layered material comprising a metal base, an etching stopper layer made of a metal material different from that of the metal layer formed on a first surface of the metal base and a chromium layer formed on the etching stopper layer, forming a resist layer having a negative pattern relative to an inner lead to be formed on the chromium layer of the three-layered material, forming an inner lead by plating copper by using the resist layer as a mask, forming an outer lead on the metal base, removing a back of a region in which an inner lead of the metal base is formed by etching, removing the etching stopper layer, and removing the chromium layer.

Abstract: Disclosed are methods and apparatuses for manufacturing a semiconductor device package utilizing a lead frame which has one or more encapsulant material flow diverters. The lead frame having material flow diverters includes a multiplicity of leads and at least material flow diverter. The material flow diverter is arranged in such a manner as to control the amount of encapsulant material which is directed both above and below an attached die during the encapsulation process.

Abstract: A leadframe (1) includes a main frame having longitudinal outer rails (4) and a number of sub-frame (8) separated from the main frame by a slit (6) extending around at least part of the perimeter of the sub-frame (8). A plurality of flag portions (2), on which a semiconductor die is to be mounted, extend from the mainframe and a plurality of lead portions (12) extend from the sub-frame (8) towards the flag portions (2). The sub-frame (8) is bent twice in a zig-zag fashion so as to be in a plane parallel to that of the main frame so that the corresponding flag and lead portions overlap without affecting the dimensions of the outer edge portion of the main frame.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

Abstract: A designing method calculates leadframe tip arrangement. The method comprises the steps of setting a leadframe tip arrangement region opposed to a die pad sideline of a leadframe, setting a leadframe tip arrangement line in the leadframe arrangement region, and arranging a predetermined number of leadframe tips on the leadframe tip arrangement line at proper intervals. The method allows for the independent calculation of various parameters.

Abstract: A device and method for increasing integrated circuit density comprising a pair of superimposed dies with a plurality of leads extending between the dies. The device is produced by providing a lower die which has a plurality of bond pads on a face side of the lower die. A layer of dielectric or insulative shielding is applied over the lower die face side. Leads are applied to an upper surface of the shielding layer. A plurality of lower die bond wires is attached between the lower die bond pads and an upper surface of their respective leads. A second layer of dielectric or insulative shielding is applied over the leads and the portion of the lower die bond wires extending over the lead upper surfaces. A back side of the upper die is adhered to an upper surface of the second shielding layer. A plurality of upper die bond wires are attached between a plurality of bond pads on a face side of the upper die and the upper surface of their respective leads.

Abstract: A semiconductor device which is greatly reliable and is also advantageous in high-density mounting, as well as the method for producing the semiconductor device, includes a filmy material placed along the peripheral sides of the semiconductor chip and along one surface of the semiconductor chip. The conductor pattern is provided on the filmy material such that one end of the pattern is connected to the corresponding electrode which has been provided on the other surface of the semiconductor chip and the other end is opposed to the back of the semiconductor chip. Hereby a semiconductor device can be realized which is greatly reliable and is also advantageous for high-density mounting. Besides, the semiconductor device is produced in such a way that a cutting and bending process of each lead and the film tape is performed toward the tape carrier package, so that the other end of each lead is opposed to the back of the semiconductor chip, holding the film tape between them.

Abstract: A leadframe for an IC package and a method of manufacturing the same are provided. The leadframe can be manufactured in such a manner as to provide suitable bondability, molding compound characteristic, and solderability. The leadframe includes a base structure made from a conductive material. A silver plating is formed over the base structure of the leadframe, and a palladium plating is formed over the silver plating. Depending on actual requirements, a copper layer and a nickel plating can be formed between the silver plating and the base structure of the leadframe, and a palladium/nickel plating can be formed between the silver and palladium platings. Further, a gold layer can be formed over the palladium plating. The palladium plating and the palladium/nickel plating can be formed all over the leadframe or selectively formed only in the external-lead area of the leadframe.

Abstract: A conductive plastic lead frame and method of manufacturing same, suitable for use in IC packaging. In a preferred embodiment the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A lead frame is prepared which has a plurality of leads whose inner lead portions are coupled to a support member and a notch formed across the bottom surface of each inner lead portion near at its front portion on the support member side. After an LSI chip is adhered to the support member, pads on the chip are connected via bonding wires to corresponding inner leads of the plurality of leads. The chip and inner lead portions are buried in an insulating layer made of resin or the like as protective coating. Each inner lead portion is cut with a cutting device such as laser beam at the notch position to separate the inner lead portion from the support member. Thereafter, the separated assembly unit is accommodated in a package made of resin or the like, and the outer leads are cut and shaped. For an assembly method of a semiconductor device including a wire bonding process, bonding defects to be caused by deformed leads can be reduced.

Abstract: A method of making chip stacks begins with the formation of a plurality of panels having apertures therein and conductive pads on opposite sides thereof. Solder paste is deposited on the conductive pads prior to mounting plastic packaged IC chips within each of the apertures in each of the panels so that opposite leads thereof reside on the conductive pads at opposite sides of the apertures. The plural panels are then assembled into a stack, such as by use of a tooling jig which aligns the various panels and holds them together in compressed fashion. The assembled panel stack is heated so that the solder paste solders the leads of the packaged chips to the conductive pads and interfacing conductive pads of adjacent panels together, to form a panel stack comprised of a plurality of chip package stacks. Following cleaning of the panel stack to remove solder flux residue, the individual chip package stacks are separated from the panel stack by cutting and breaking the stack.

Abstract: Process for manufacturing arrays of metal balls for interconnect testing and/or interconnect bonding of microelectronic devices and the like with substrates are formed by securing metal balls in predetermined patterns of apertures in an insulating membrane or film. The pattern of apertures corresponds with the pattern of metal interconnect pads on a microelectronic device or the like and the corresponding pattern of interconnect pads on the substrate. The metal ball arrays may be used for testing and/or may be heated and reflowed to bond the microelectronic device to the substrate.

Abstract: A process for manufacturing a metal plane support for making multi-layer lead frames adapted to be used for semiconductor devices. The lead frame support is made of a single thin metal strip having a plurality of lead frames continuously arranged in the longitudinal direction, the metal plane support is also made of a single thin metal strip and includes a plurality of metal planes, such as power supply planes, ground planes of the like, continuously arranged in the longitudinal direction corresponding to said plurality of lead frames. A pair of side rails are extending in the longitudinal direction for supporting the metal planes therebetween. The metal planes are connected to the rails via separating portions for removing the rails from the metal planes, after the metal planes are adhered to the corresponding lead frames.

Abstract: A unit printed circuit board (PCB) carrier frame used in the fabrication of a heat sink-attached ball grid array (BGA) semiconductor packages and a method for BGA semiconductor packages using the unit PCB carrier frame. The unit PCB carrier frame has a plurality of die pads each defined at its peripheral edges by elongated slots formed at a strip or reel-shaped frame member. For the fabrication of heat sink-attached BGA semiconductor packages, unit PCBs are bonded to the die pads of the unit PCB carrier frame. Accordingly, the bending of the packages is minimized even when they pass through subsequent processes requiring a high temperature. As a result, it is possible to obtain a maximum number of unit PCBs from a PCB panel, thereby achieving an improvement in productivity.

Abstract: A pair of metal lead frames are stacked together with a plurality of solder coated semiconductor chips sandwiched between respective pairs of overlapped portions of the lead frames and the lead frame stack is then disposed within a fixture comprising spaced apart clamping means for clamping together the overlapped portions of the lead frames. Only the clamping means contact the frame stack and in thermally and electrically insulated relation therewith for minimizing heat loss from and electrical shorting of the lead frame stack to the fixture. Electrodes are tightly clamped against exposed ends of the lead stack for passing electrical current through the stack for causing electrical resistance heating of the stack and the soldering of the chips to the lead frames.

Abstract: A semiconductor die assembly and methods of forming same comprising a lead frame having a plurality of lead fingers and a semiconductor die having a plurality of electric contact points on an active surface of said semiconductor die. The electric contact points are located or rerouted on the semiconductor die active surface so as to maximize the size and spacing of electric contact points relative to the lead fingers, which may be custom-configured to match the "open" array of contact points and widened to enhance surface area for connection thereto. This arrangement results in large and robust flip-chip type interconnections between the electric contact points and the lead frame, eliminating the need for wirebonding and for adhesive connections of the lead frame to the die active surface.

Abstract: A method for improving adhesion from a leadframe to a metallic wire is disclosed including using a laser beam to remove selected areas of an package adhesion enhancing layer to expose a layer on the leadframe which has a higher adhesion to metallic wires. The package adhesion enhancing layer is from the group consisting essentially of aluminum oxide, anti-tarnish finishes, and dielectrics.The exposed layer on the leadframe is selected from the group consisting essentially of silver, nickel, palladium.

Abstract: A semiconductor package is produced by the following steps. A plurality of circuit boards are prepared, each board having an opening for forming a cavity and a surface providing with a circuit pattern having bonding sections at a peripheral area of the opening. The bonding sections of the respective circuit boards are covered with protective films. A laminated body is formed by laminating the plurality of circuit boards by means of adhesive sheets arranged between the respective circuit boards. Upper and lower substrates are also laminated on upper and lower surfaces of the plurality of circuit boards, respectively, by means of adhesive sheets to close the cavity. The protective films are subsequently removed from the bonding sections of the respective circuit boards of the laminated body.

Abstract: A quad flat pack arrangement which provides for an electrically enhanced integrated-circuit package structure is disclosed. An integrated-circuit die is centrally attached to the top surface of a thermally-conductive, and electrically conductive or insulated substrate. A lead frame having a plurality of inwardly-extending bonding fingers has the bottom sides thereof attached to the top surface of the substrate by a non-conductive adhesive so that an open portion thereof overlies the integrated-circuit die. The plurality of bonding fingers are disposed so as to peripherally surround the integrated-circuit die. A double-sided printed circuit board having first and second conductive layers disposed on its opposite sides is disposed over and bonded to the lead frame. Bonding wires are used to interconnect bonding pads on the integrated-circuit die to the first and second conductive layers. A plastic material is molded around the substrate, die, lead frame, printed circuit board and conductive layers.

Abstract: Disclosed herein are a method of fabricating a power semiconductor device having joiners that (205) vertically extend from outer sides of leads (203, 204) of a tie bar (201) of a power circuit lead frame (20) respectively, while joiners (308) vertically extend from outer sides of leads (303, 307) of a tie bar (301) of a control circuit lead frame (30) respectively to be opposed thereto. Forward end portions (205a) of the joiners (205) are joined to rear surfaces of forward end portions (308a) of the joiners (308) at a device center portion.

Abstract: The present invention is premised on a semiconductor device in which one semiconductor chip is mounted on each of both faces of a die pad of a lead frame. The semiconductor chips are disposed such that the projected lines, on the die pad, of the corresponding sides of the semiconductor chips, intersect with each other at an angle of 45.degree.. The tips of inner leads are located in the sides of a virtual octagon formed by outwardly enlarging an octagon formed by connecting, to one another, the apexes of the semiconductor chips. The sides of the virtual octagon are respectively opposite to the sides of the semiconductor chips. The number of the inner leads of which tips are located in each of the sides of the virtual octagon, is the same as the number of bonding pads disposed at each of the sides of the semiconductor chips.

Abstract: A lead-on-chip package manufacturing method includes an insulating liquid adhesive depositing step on lead attaching regions formed on an active surface of a semiconductor on a wafer. The adhesive deposition may be accomplished by a screen printing method in which the adhesive is forced through hole patterns of a metal screen, or by a dispensing method in which a liquid adhesive is dispensed from needles of a dispensing head that is movable over the wafer surface and is aligned with the wafer. The dispensing technique may be applied to a plurality of chips in step-by-step fashion, or in a simultaneous manner by using a multi-needled dispensing head.

Abstract: A method of forming a semiconductor memory device comprises the steps of providing a semiconductor die, forming a temporary protective material over a surface of the die, and attaching the die to a first lead frame portion. Next, a protective material is contacted with a second lead frame portion and, subsequently, the second lead frame portion is electrically connected with the second lead frame portion with bond pads on the first surface of the die with bond wires. Subsequent to electrically connecting the die and the second lead frame portion the protective material is removed.

Abstract: A process for manufacturing a tape automated bonding circuit with interior sprocket holes including: a substrate; at least one conductor deposited on the substrate; a functional area on the substrate defined by a polygon surrounding the conductor with all sides of the polygon adjacent to a segment of the conductor and with interior angles of the polygon between the sides of the polygon greater or equal to ninety degrees and having at least one sprocket hole within the functional area on the substrate. The sprocket hole is used to engage and drive the tape automated bonding circuit through processing steps. In a specific embodiment the functional area on the substrate has a first set of two sprocket holes within the functional area, which are used to engage and drive the tape automated bonding circuit through processing steps.

Abstract: A solid tape automated bonding method includes steps of: applying a pattern of a first dry film on a first portion of a copper plate; forming wiring; forming bumps; removing dry film and exposing the wiring and the bumps; selectively laminating an insulator layer onto portions of the exposed copper plate and the wiring; laminating a metal layer on the insulator layer; applying glue on the metal layer, the bumps, and respective exposed portions of the wiring and the copper plate; etching the copper plate thus exposing one side of the wiring as ball pads and exposing one side of the insulator layer; coating solder resist on the exposed bottom side of the insulator layer; removing the glue; attaching a die against the bumps; applying mold compound onto the die so as to fix the die in place; and attaching solder balls onto the ball pads. This method provides relatively high density of wiring and simplification in manufacturing.

Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are formed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.

Abstract: A leadframe integrated circuit package is provide with an interposer structure for electrically interconnecting a die with the leadframe. The interposer has a rigid substrate, which is mounted in the leadframe in place of a conventional integrated circuit die. Interposer bonding pads at the periphery of the substrate are connected to bond fingers of the leadframe, e.g., by wire bonding. The interposer bonding pads are electrically connected to the die using a network of routing lines connected to a central array of interposer array pads. The array of interposer array pads is connected to a corresponding array of die array pads on the die using metal bumps.

Abstract: A method and apparatus for connecting a lead of a lead frame to a contact pad of a semiconductor chip using a laser or other energy beam is herein disclosed. The lead may be wire bonded to the contact pad by heating the ends of a wire until the wire fuses to the contact pad and lead or an energy-fusible, electrically-conductive material may be used to bond the ends of the wire to the contact pad and lead. In addition, this invention has utility for both conventional lead frame/semiconductor chip configurations and lead-over-chip configurations. In addition, with a lead-over-chip configuration, the lead may be directly bonded to the contact pad with a conductive material disposed between the lead and the contact pad.

Abstract: Method for producing semiconductor devices comprises a first step in which a plurality of metal substrates each of which is provided with a die mounting region at a central portion thereof are connected in series to produce a train of connected metal substrates by means of first connecting tabs and a pair of first side rails each of which is provided with first positioning pilot apertures are connected to the train by means of second connecting tabs to produce a metal substrate frame, a second step in which a plurality of circuit substrates each of which is provided with a lead pattern around an opening formed at the central portion thereof are connected in series by means of third connecting tabs to produce a train of connected circuit substrates and a pair of second side rails each of which is provided with second positioning pilot apertures are connected by fourth connecting tabs to produce a circuit substrate frame, a third step in which both frames are alinged with each other making use of the first and

Abstract: A semiconductor chip connection component having numerous leads extending side-by-side across a gap in a support structure, each lead having a frangible section to permit detachment of one end of the lead from the support structure in a bonding process. The frangible sections are formed by treating the lead-forming material in an elongated treatment zone extending across the regions occupied by numerous leads. The process avoids the need for especially fine etching to form notches in the lateral edges of the leads.