Abstract: An apparatus for reversing upper and lower surfaces of a lead frame which passes through a silver-plating process in a lead frame manufacturing process includes at least one guide rail having a curved portion for guiding the lead frame to be fallen down and reversed along an arc of the curved portion, and a conveying roller provided under the guide rail to horizontally convey the fallen lead frame. Thus, since the lead frame is reversed through a specific structure without use of any robot, the malfunction problem of the prior art is solved and costs are reduced.

Abstract: A method of producing individual integrated circuit package units includes the steps of: providing a base which includes a leadframe, a plurality of package precursors, and a continuous encapsulating epoxy layer bonded integrally with the leadframe; and singulating the package precursors. The leadframe has a plurality of metallic connection bars and extension parts formed integrally with the connection bars. The package precursors are singulated by cutting the leadframe and the epoxy layer along first and second cutting streets. The cutting of the base is performed by cutting into the first and second cutting streets with a cutting tool, which can be a single-blade or dual-blade, thereby separating the connection bars from the inner leads.

Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.

Abstract: A method of making a Fe-Ni strip whose chemical composition comprises, by weight: 36% ≦Ni+Co≦43%; 0%≦Co≦3%; 0.05%≦C≦0.4%; 0.2%≦Cr≦1.5%; 0.4%≦Mo≦3%; Cu≦3%; Si≦0.3%, Mn≦0.3%; the rest being iron and impurities, the alloy having an elastic limit Rp0.2 more than 750 Mpa and a distributed elongation Ar more than 5%. The alloy is optionally recast under slag. The strip is obtained by hot-rolling above 950° C., then cold-rolling and carrying out a hardening treatment between 450° C. and 850° C., the hardening heat treatment being preceded by a reduction of at least 40%. The invention is useful for making integrated circuit support grids and electronic gun grids.

Abstract: The resin-encapsulated semiconductor device of the present invention includes: a die pad provided by thinning a lower portion of a lead frame; a semiconductor chip mounted on the die pad; a plurality of leads provided by thinning an upper portion of the lead frame; a connection member for connecting the semiconductor chip and the lead with each other; a plurality of suspension leads connected to the die pad; and an encapsulation resin for encapsulating an upper portion of the lead frame. In this way, it is possible to further reduce the thickness of a resin-encapsulated semiconductor device, while upsetting the die pad. Furthermore, the stress occurring from the encapsulation resin is absorbed by the self flexural deformation of the die pad and the lead, which are thinned, thereby improving the connection reliability.

Abstract: A method for joining lead frames in a chip stack package or a package stack, a chip stack package, and a method of forming a chip stack package. A joining mediator is formed on joining portions of at least one lead frame. The joining mediator has an anti-oxidation property and an inter-metallic diffusion property, and may be formed of gold wires, gold bumps, gold bars, solder bumps, solder, or solder bars. By clamping or compressing the lead frames under heat and pressure, the joining mediator forms an inter-metallic joint layer that reliably interconnects the lead frames at the joining portions.

Abstract: A multi-chip semiconductor package using a lead-on-chip lead frame. The lead-on-chip package places two or more lead-on-chip dice into one package that are either attached to their own lead-on-chip lead frame or are mounted to the same lead-on-chip lead frame and subsequently wire bonded to provide electrical connection from the dice to the lead frame while in substantially the same arrangement without requiring the assembly of the multiple semiconductor dice and lead frame to be flipped for additional wire bonding attachment of the dice to the lead frame.

Abstract: A non-leaded semiconductor device which does not cause a flaw and contamination with a foreign substance on mounting surfaces of external electrode terminals of another non-leaded semiconductor device, and a method of fabricating the same. In fabrication of the non-leaded semiconductor device, a matrix-type leadframe containing a matrix of a plurality of unit leadframe patterns is prepared, a semiconductor chip is secured on each unit leadframe pattern, conductive wires are connected between electrodes of the semiconductor chip and inner ends of terminal leads of each unit leadframe pattern, and then single-sided molding is performed to encapsulate the semiconductor chip, conductive wires, and inner end parts of terminal leads in a package part. In this single-sided molding, a contact-preventive part thicker than the package part is formed outside the package part using injected resin.

Abstract: A CDBGA package comprises a thermal dissipating substrate and a plurality of conductive bumps. A plurality of vias are formed on a circuit substrate and correspond to the conductive bumps. A plurality of ground pads, ball pads and nodes are formed on the circuit substrate, wherein the ground pads are located in the vias. A solder mask layer covers the patterned trace layer. A plurality of bonding pads are formed on a chip and are electrically connected to the nodes. A molding compound encapsulates the chip, nodes and bonding pads. A plurality of solder balls are located on the ground pads and ball pads, wherein the solder balls fill the vias and are electrically connected to the conductive bumps.

Abstract: In a lead frame which comprises lead portions extended from a frame portion toward an inside like a teeth of a comb and each having a top end portion, a center portion, and a base portion connected to the frame portion, the top end portion and the center portion are connected via a first constriction portion, and the center portion and the base portion are connected via a second constriction portion, and thickness of both side surface portions of the center portion and the top end portion of each lead portion are set thinner than thickness of remaining portions of each lead portion.

Abstract: A semiconductor device comprises: a semiconductor chip; a copper series lead frame with no residual of a rustproof film, including a die pad mounted with said semiconductor chip, and a plurality of leads disposed so that inner ends of said leads are positioned along the periphery of said die pad; copper wires to directly connect electrodes on said semiconductor chip to the inner ends of said plurality of leads; and a resin molded member to hermetically seal said semiconductor chip, a large proportion of said lead frame and said copper wires, wherein a water soluble rustproof agent is applied over outer lead segments, protruding from said resin molded member, of said plurality of leads.

Abstract: A method of implementing a micro BGA is introduced. More specifically, the method discloses packaging an integrated circuit into an integrated circuit assembly. The method first mounts polyimide tape to a lead frame. The polyimide tape serves as a substrate for the integrated circuit package. Next, a piece of elastomer is coupled to said polyimide tape. Then an integrated circuit die is attached to said elastomer. Lead beams are then bonded from bond pads on said die to said lead frame. Solder balls are attached to said lead frame. The attached solder balls may be located beyond the area of said die.

Abstract: The lead frame of the present invention is a lead frame used in resin encapsulation of a semiconductor chip using an encapsulation mold that includes a die cavity to be filled with an encapsulation resin, the lead frame including: a first region exposed to the die cavity; a second region that is surrounding the first region and to be clamped by the encapsulation mold; a third region exposed to an ambient air with the die cavity being filled with the encapsulation resin; and at least one groove formed on a surface of the lead frame that is opposite to another surface of the lead frame on which the first region is present, the at least one groove extending from an area corresponding to the first region across another area corresponding to the second region so as to reach the third region.

Abstract: A semiconductor package which is improved in thinness and heat radiation and a method for making the same. The package includes a semiconductor chip electrically connected to leads of a leadframe via input and output bond pads. The leadframe may have a ground ring formed therein. The leads and semiconductor chip are at least partially encapsulated by an encapsulant. The semiconductor chip and leads have bottom surfaces which are externally exposed to improve heat radiation and reduce the thickness of the package. The package is made by placing the leadframe having leads onto adhesive tape, affixing a semiconductor chip into an open space on the leadframe, pressurizing the leadframe and chip downwardly for securement to the adhesive tape, electrically connecting input bond pads and output bond pads on the chip to the leads; at least partially encapsulating the leads and semiconductor chip; removing the tape from the bottom surfaces of the leads and chip; and cutting the leadframe to form the package.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant.

Abstract: A stacked semiconductor package including: a first chip; a plurality of first leads of which one side of each of the first leads is attached to the first chip by an insulating adhesive member and electrically connected to the first chip; a first molding compound for sealing the first chip and the first leads, including holes for exposing a predetermined portion of each of the plurality of the first leads, and the first molding compound does not cover a side of the first leads opposite the holes; a first conductive portion formed within the holes included in the first molding compound; an external terminal electrically connected to the first conductive portion; a second chip; a plurality of second leads attached on the second chip by the insulating adhesive member, and being electrically connected to the second chip; a second molding compound for sealing the second chip and the second leads, and exposing a predetermined portion of the second leads; a plurality of conductive connection units for electrically co

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments of the carrier include easier handling, reduced probability of defective end products, and increased control in choosing the thinness of the substrate film. For example, the substrate film carrier can be used for lead-over-chip (LOC) assemblies and lead-under-chip (LUC) assemblies to create ball grid arrays (BGA), pin grid arrays (PGA), dual in-line packages (DIP), and the like.

Abstract: Techniques for maintaining the optical coupling efficiency between photonic devices of an optoelectronic module and its interconnecting optical fibers are described. The techniques ensure that the mating surfaces of an optical sub-assembly and a chip sub-assembly remain planar to each other throughout and after the soldering process of the optoelectronic manufacturing process. These techniques include the use of a ceramic fixture made of a stack of plates having openings that secure the orientation of the optical and chip sub-assemblies. The fixture can have one or more openings to secure a respective one or more combination of optical and chip sub-assemblies. A high temperature tape can also be used to maintain the parallelism between the optical and chip sub-assemblies. An optical sub-assembly having pedestals on its bottom surface can also be use to maintain parallelism of the optical and chip sub-assemblies. Methods of using each technique is also described.

Abstract: A method and apparatus for increasing the integrated circuit density of a thin small outline package (“TSOP”) semiconductor assembly is provided by stacking two semiconductor dice and electrically connecting the substantially centrally located bond pads of substantially identically arranged bond pads of each die the same surface of a single lead frame. Each semiconductor die may be electrically connected to a plated, common connection surface of the lead frame. The lead frame may include downsets to properly position the semiconductor assembly within the package. Further, if wire bonds are used as electrical connection elements, stitch bonding may be employed to enhance rigidity of the bond wires and to modify electrical characteristics of the electrical connection elements.

Abstract: A hybrid semiconductor package is formed from a die having two opposed elongate die edges with conductive bond pads arranged transversely relative to the rows of outer leads. A first portion of inner leads is off-die wire bonded to some of the bond pads, and a second portion of inner leads is insulatively attached as LOC leads between the bond pads along the opposed die edges. The hybrid package results in shorter inner leads of increased pitch enabling improved line yield at wire bond and encapsulation, as well as improved electrical performance, particularly for packages with very small dice.

Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Abstract: A method for attaching an electronic die to a substrate is disclosed. Preferably, the method includes depositing a pad of low temperature die attachment material within a die attachment area on the substrate, positioning the die over the pad of low temperature die attachment material, and compressing the die against the substrate to expel air trapped within the pad of low temperature die attachment material. Further, a bead of containment material is deposited onto the substrate to define the die attachment area. In this manner, the die attachment material is contained on the substrate. Thus, the method of the present invention improves the reliability of the electronic die.

Abstract: A semiconductor element is first fixed on a frame. The semiconductor element and a plurality of leads are connected together. The semiconductor element is sealed with molding resin, to thereby fabricate a package having a length per side of 14 mm or more. After tie bars interconnecting a plurality of leads have been cut, a package is subjected to heat treatment at a predetermined temperature.

Abstract: A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads. A plurality of external connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chip in the adjacent chip-receiving window.

Abstract: The present invention relates to a method of manufacturing an integrated circuit package, including providing a lead frame without a die attachment pad, the lead frame having a ridge portion protruding from a base portion, the ridge portion having an upper surface and defining an upper portion of a cavity, the base portion having a lead and a lower surface, attaching an adhesive strip to at least the lower surface of the base portion to seal a bottom portion of the cavity, encapsulating the cavity such that at least a portion of the upper surface of the ridge portion of the lead frame and at least a portion of the lower surface of the base portion are exposed, and removing the adhesive strip.

Abstract: A stereolithographically fabricated, substantially hermetic package surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. Stereolithographic processes may be used to fabricate at least a portion of the substantially hermetic package from thermoplastic glass, other types of glass, ceramics, or metals. The substantially hermetic package may be used with semiconductor device assemblies or with bare or minimally packaged semiconductor dice, including dice that have yet to be singulated from a wafer. The stereolithographic method may include use of a machine vision system including at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position, orientation, and features of a semiconductor device assembly, semiconductor die, or other substrate on which the substantially hermetic package is to be fabricated.

Abstract: A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape secured to a rigid frame. The rigid frame maintains tension in the sheet of sticky tape to provide a stable surface to which the lead frame panel can be affixed. Installation of IC chips and encapsulation in protective casings is performed as in conventional IC package manufacturing. If encapsulant material is to be dispensed over the IC chips, an encapsulant dam can be formed around the lead frame panel to contain the flow of encapsulant material. The temporary support fixture can be used in any IC package manufacturing process in which lead frames require supplemental support.

Abstract: A semiconductor device comprising a substrate including a metal portion and a resin portion and having a plurality of through holes formed in the resin portion, conductive members formed within the through holes, a semiconductor chip attached to one surface of the substrate, and a plurality of solder balls attached to the other surface of the substrate. The semiconductor chip and solder balls are electrically connected through the conductive members.

Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.

Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.

Abstract: A semiconductor chip assembly includes a semiconductor chip, a conductive trace, a connection joint, an insulative adhesive and an encapsulant. The conductive trace includes a routing line and a pillar. The routing line extends within and outside a periphery of the chip, and the pillar is disposed outside the periphery of the chip and extends away from the chip. The connection joint contacts and electrically connects the routing line and the pad. The adhesive is sandwiched between the routing line and the chip and contacts a surface of the routing line that faces away from the chip, thereby interlocking the routing line to the assembly. The encapsulant extends into a channel in the pillar, thereby interlocking the pillar to the assembly.

Abstract: The semiconductor device includes a semiconductor chip having a first electrode and a second electrode formed on a first main surface and a third electrode formed on a second main surface opposite the first main surface. A first portion of a first lead is placed on the first electrode and a second portion of the first lead is located outside the semiconductor chip. A first portion of a second lead is placed on the second electrode and a second portion of the second lead is located outside the semiconductor chip. A plurality of projecting electrodes are provided between the first portion of the first lead and the first electrode and between the first portion of the second lead and the second electrode to electrically connect them. An insulating sheet is provided between the first portion of the first lead and the first main surface of the semiconductor chip and between the first portion of the second lead and the first main surface of the semiconductor chip.

Abstract: In a motor driving device, an IC chip of a drive circuit for driving a motor is die-bonded to one island of a leadframe, and a diode chip of a protection diode for preventing the drive circuit from being destroyed when supplied power is connected to the IC chip with reverse polarities is die-bonded to another island of the leadframe. The supplied-power pad of the IC chip is wire-bonded to the second island, which serves as the cathode electrode of the diode chip.

Abstract: In a method of manufacturing a lead frame for use in a leadless package such as a quad flat non-leaded package (QFN), a base frame is first formed which includes a region for resin-molding a plurality of semiconductor elements to be mounted on one surface of the base frame, the region being partitioned into land shapes, and in which a die-pad portion and lead portions around the diepad portion are defined severally for the individual semiconductor elements to be mounted in each of the partitioned regions for resin-molding. Next, an adhesive tape is attached to the other surface of the base frame, and subsequently a cut portion is provided at a portion corresponding to a region between two adjacent partitioned regions for resin-molding, of the adhesive tape.

Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation. Since each die attach site includes a die attached thereto, the structural integrity of the mounting substrate is maintained and there is greater volume control of encapsulation material in the transfer molding operation to prevent waste and shortage of the encapsulation material.

Abstract: An integrated circuit package includes a package body, such as a transfer molded plastic or preformed ceramic package body, having an integrated circuit die positioned therein. A lead frame, such as a peripheral lead, Leads-Over-Chip (LOC), or Leads-Under-Chip (LUC) lead frame, includes a plurality of leads with portions enclosed within the package body that electrically connect to the integrated circuit die. A heat sink is positioned at least partially within the package body so a surface of a first portion of the heat sink faces the lead frame in close proximity to a substantial part, such as at least eighty percent, of the area of the enclosed portion of the lead frame to thereby substantially reduce an inductance associated with each of the leads.

Abstract: A stacked-die assembly and a method of manufacturing a stacked-die assembly having a plurality of microelectronic devices. In one embodiment, a stacked-die assembly can include a first die, a second die juxtaposed to the first die, and an interface substrate coupled to the first and second dies. The first die can have a first integrated circuit and a first terminal array coupled to the first integrated circuit, and the second die can have a second integrated circuit and a second terminal array coupled to the second integrated circuit. The interface substrate can comprise a body, a first contact array on the body that is electrically coupled to the first terminal array of the first die, a second contact array on the body that is electrically coupled to the second terminal array of the second die, and at least one ball-pad array on the body.

Abstract: A conductive plastic lead frame and method of manufacturing the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of lead-free solder on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.

Abstract: A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of external nodes is formed on the second surface of the substrate unit, and the external nodes are electrically connected to the nodes. A multimedia chip has an active surface and a corresponding back surface, and a plurality of bonding pads are formed on the active surface of the multimedia chip. The back surface of the multimedia chip is adhered on the die pad of the substrate unit. A molding compound encapsulates the multimedia chip, the first surface of the substrate unit, and the conductive wires, and exposes the second surface of the substrate unit and the external nodes.

Abstract: An un-packaged or semi-packaged, electrically tested electronic device, free from infantile mortality, characterized in that it comprises a silicon platelet or die (11) having a top surface and a bottom surface, in which an integrated circuit is realized externally accessible through a plurality of connection pads and an array of connection pins (10; 13; 14) which are mechanically and removably connected to said silicon die (11) by connection means and are electrically connected to the connection pads of said silicon die (11) by electric connection means (12).

Abstract: The semiconductor device is manufactured as follows. That is, after the die pad section, on which the semiconductor chip is mounted, the inner lead section and at least a part of the outer lead section are arranged in the cavity of the metal mold on the lead frame. Moreover, the sealing resin is filled into the cavity of the metal mold and hardened therein. Moreover, the sealing resin located on a surface layer region of the outer lead section of the lead frame removed.

Abstract: A lead frame for semiconductor device comprising inner leads, outer leads, and dam bars, the inner leads being divided into two groups which are located in opposed areas of the lead frame divided by the center line of the array of the electrode pads of a semiconductor chip to be mounted on the lead frame, and the inner lead having a first end and a second end, the first ends of the respective inner leads being arranged into arrays along an array of electrode pads of the semiconductor chip, so that the array of the first ends has a pitch corresponding to a pitch in the array of the electrode pads, the second ends of the respective inner leads being arranged into arrays at opposed sides of the lead frame, to have a pitch larger than the pitch in the array of the first ends, wherein at least some of the inner leads are arranged to have lengths between the first and the second ends which are substantially equivalent to each other. A semiconductor device using the lead frame is also disclosed.

Abstract: A hollow package includes a package body composed of an epoxy resin having a low thermal coefficient of linear expansion, wherein the package body includes a recess for receiving an electronic component, and leads, for extracting electrodes of the electronic component, extending from the inner surface of the recess, via the upper surface of the package body, to the peripheral surface, and a transparent sealing plate bonded onto the upper surface of the package body with an ultraviolet-curable resin.

Abstract: A method for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC remain connected to the assembly strip. The assembly strips are then passed to a test apparatus that transmits test signals to the ICs through the formed leads. The IC devices are then separated from the assembly strip using a singulation apparatus, and the separated ICs are stored in tubes for delivery. Visual inspection is also performed at various stages.