Abstract: The present invention provides a mold injection method for semiconductor device by which the problem of residual metal is overcome. The inventive method comprises following steps: die attaching; wire bonding; attaching solder-resisting tape around the die; molding; removing the older-resisting tape; marking; ball placement: and singulation.

Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.

Abstract: In a method for handling in parallel a plurality of circuit chips, which are arranged in a first arrangement, which corresponds to their arrangement in the original wafer, on the surface of an auxiliary carrier, the plurality of circuit chips is picked up by a plurality of pick up devices. The plurality of pick up devices with the picked up circuit chips is moved simultaneously to one or several carriers, in such a way that, simultaneously with the motion, the first arrangement of the circuit chips is changed into a second arrangement, which is different from the first arrangement. Then the circuit chips are simultaneously placed in the second arrangement on the one or several carriers.

Abstract: A stereolithographically fabricated, substantially hermetic package surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. Stereolithographic processes may be used to fabricate at least a portion of the substantially hermetic package from thermoplastic glass, other types of glass, ceramics, or metals. The substantially hermetic package may be used with semiconductor device assemblies or with bare or minimally packaged semiconductor dice, including dice that have yet to be singulated from a wafer. The stereolithographic method may include use of a machine vision system including at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position, orientation, and features of a semiconductor device assembly, semiconductor die, or other substrate on which the substantially hermetic package is to be fabricated.

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: A method is provided for packing semiconductor die. The method includes the following steps: Firstly, a metal frame having a specific pattern is provided. Then, a material on the backside surface of a plurality of dice is laminated. The plurality of dice is located upon the metal frame. A metal wire is bonded to connect the plurality of dice below. Next, first molding the plurality of dice and parts of the metal frame to expose parts of the metal frame is achieved by a chemical compound to seal the plurality of dice. Then, the second individual/conformal molding the plurality of dice is carried out by the chemical compound. Next, a plurality of metal balls is placed to connect under other parts of the metal frame as an individual/conformal die package. Finally, the individual die package is punched to pack the semiconductor die.

Abstract: A multi-hip semiconductor package is proposed, in which a first chip and a second chip are mounted on opposing surfaces of a lead frame in a staggered manner. This staggered arrangement assures the die bonding quality for firmly disposing the second chip in the semiconductor package without being detrimental affected by the first chip. Moreover, as both opposing surfaces of the lead frame have chips mounted thereon, a mold flow of a molding resin used in a molding process can be balanced, so that turbulence the mold flow is decreased, and void formation can be avoided. In addition, the semiconductor package can incorporate a third chip in a stacked manner with respect to the first or second chip. This therefore further improves the functionality and performance of the semiconductor package.

Abstract: A method of manufacturing a semiconductor chip that has electrode pads on the chip front surface and disposed inside a conductive outer ring. A film circuit is disposed on the chip front surface side. External connection thermals are formed on the film circuit so as to project there from. First leads electrically connect part of the electrode pads to part of the external connection terminals. A second lead electrically connects a grounding or power supply electrode pad to the outer ring, and a third lead electrically connects a grounding or power supply external connection terminal to the outer ring.

Abstract: A method for bonding inner leads of lead frame to substrate includes the steps of: (a) providing a substrate, the substrate having a plurality of connection pads formed on the electrical bonding surface of the substrate; (b) providing a lead frame with a dam tape adhered on of the inner leads of the lead frame; (c) thermally compressing the inner leads of lead frame onto the substrate, wherein a solder material is formed between the inner end and the corresponding connection pad of the substrate and the solder material is limited by the dam tape during inner lead bonding, so that there is stable electrical and mechanical connection between inner leads and the substrate.

Abstract: A method of making a leadless semiconductor package mainly comprising the steps of: attaching a tape onto the bottom of a lead frame; attaching a semiconductor chip to the die pad of the lead frame and electrically coupling the semiconductor chip to the leads of the lead frame; forming a package body over the semiconductor chip and the lead frame in a manner that each lead of the lcad frame has at least a portion exposed from the bottom of the package body; removing the tape; and grinding the bottom of the package body as well as the exposed portions of the lead frame till each lead of the lead frame is less than about 1 mil thick thereby reducing the problems due to CTE mismatch between the leads and the package body.

Abstract: An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.

Abstract: A laminated semiconductor chip fabricated by fixing back surfaces of first and second semiconductor chips, respectively having a principle surface and the back surface, to each other. Each of the principle surfaces of the laminated semiconductor chip is fixed to a corresponding surface of a lead frame. A standing linear portion of a metallic wire on a ball bond side is pulled up in parallel with a side surface of the semiconductor chip in its thickness direction and a side surface of the inner lead in its thickness direction, and subjected to wire bonding. Thus formed semiconductor chip is covered by a sealing resin material so that an outer lead protrudes from a side surface of the sealing resin. Thus, the thickness of the semiconductor device can be made thin, a cost can be reduced, and a quality can be improved to deal with a tendency of increments of capacities of electronic equipments.

Abstract: A semiconductor device substrate which can be easily conveyed and a semiconductor device fabrication method using the substrate. The semiconductor device fabrication method includes forming a solder resist on a semiconductor element mounting plate-shaped substrate having major and minor sides and containing organic matter, having a linear expansion coefficient A different from that of the substrate, warping the substrate along a minor-side direction, and conveying the warped substrate.

Abstract: A method and structure for attaching a lead frame to a heat sink are provided. In one embodiment, a layer of thermally conductive, electrically insulating epoxy is formed on a heat sink and the epoxy layer is fully cured. A thermoplastic adhesive layer is formed on the epoxy layer, and the heat sink is clamped to the lead frame such that the thermoplastic layer contacts the lead frame. The thermoplastic layer is heated to its melting point and then cooled, thereby joining the heat sink and the lead frame. In a variation, a partially cured B-stage epoxy layer is used to replace the thermoplastic layer. The B-stage epoxy layer is fully cured to connect the lead frame to the heat sink.

Abstract: A power semiconductor die has a drain contact, a source contact, and a gate contact. A lead frame has first, second, and third terminals. A metal sheet has first and second contacting portions and a bridging portion interconnecting the first and second contacting portions. The power semiconductor die is mounted on the lead frame such that the drain contact is connected to the first terminal. The metal sheet is attached to the top surface of the power semiconductor die and the second and third terminals of the lead frame such that the source contact and the second terminal are connected to the first contacting portion, and such that the gate contact and the third terminal are connected to the second contacting portion. The bridging portion is subsequently cut for disconnecting electrically the first and second contacting portions.

Abstract: A multi-chip semiconductor package using a lead-on-chip lead frame. The lead-on-chip package places two or more lead-on-chip dice into one package that are either attached to their own lead-on-chip lead frame or are mounted to the same lead-on-chip lead frame and subsequently wire bonded to provide electrical connection from the dice to the lead frame while in substantially the same arrangement without requiring the assembly of the multiple semiconductor dice and lead frame to be flipped for additional wire bonding attachment of the dice to the lead frame.

Abstract: A method for forming a semiconductor device includes steps that provides a lead frame which has a die pad and a plurality of leads extending toward an outside from the die pad, that mounts a semiconductor chip on the die pad, that defines a plurality of inner leads by cutting a predetermined cut portion on the each of the leads locating around the semiconductor chip, and that bonds with a wire between the each of inner leads and the semiconductor chip. Accordingly, the method for forming the semiconductor device can get applicable lead frame for several sizes of a semiconductor chip.

Abstract: A lead frame including signal-connecting leads, a die pad and support leads is provided. A semiconductor chip is bonded to the die pad with an adhesive. The semiconductor chip, electrode pads and the signal-connecting leads are electrically connected to each other with metal fine wires. And these members are encapsulated in a resin encapsulant. The back surface of the die pad is subjected to half etching or the like to form a convex portion and a flange portion surrounding the convex portion. Since a thin layer of the resin encapsulant exists under the flange portion, the resin encapsulant can hold the die pad more strongly and the moisture resistance of the device can be improved with the lower surface of the die pad protruding from the resin encapsulant. As a result, the characteristics of a resin-molded semiconductor device having a die pad exposed on the back surface of a resin encapsulant can be improved.

Abstract: A process for manufacturing a semiconductor device (70) using selective plating and etching to form the packaging for such device. A flat sheet (20) of conductive material is selectively plated with a conductive etch resistant material to form a plurality of die attach areas (22) on one side (23) of the sheet (20) and to define die contact (24) and lead contact (26) areas on the opposite side (27) of the sheet. Mold locks (34) which also serve as interconnect bonding areas are selectively plated on the side (23) of the sheet in association with each of the die attach areas (22). Semiconductor die (40) are attached to each of the die attach areas (22) and bonded (42) to the tops of the mold locks (34). A unitary molded resin housing (50) is formed overlying all of the semiconductor device die (40). The underside (27) of the conductive sheet (20) is selectively etched using the plated etch resistant material (24), (26) as an etch mask to form isolated die contact areas (60) and lead contact areas (62).

Abstract: An integrated circuit package. The package includes a substrate that has a first internal conductive bus and a second internal conductive bus that are located on a common layer of the substrate and dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface of the package by vias that extend through the substrate. The first and second busses are located on a common layer of the substrate. The package contains an integrated circuit which is mounted to a heat slug that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers are connected to the internal busses by conductive strips that wrap around the edges of the shelf. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package.

Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced.

Abstract: Chip lead frames are made by disposing a die having terminals on a substrate surface to form a cavity between the die and the substrate and contacts between the terminals and the substrate. A compound is applied to the surface such that the compound enters that cavity and forms a layer on the upper substrate surface. The layer can impart sufficient rigidity to the assembly that the substrate can be etched to produce a lead frame. Also disclosed are devices that include a die, a lead frame, and a continuous network that can form a layer on the lead frame and fill the cavity between the die and the lead frame.

Abstract: A stereolithographically fabricated, substantially hermetic package. The package surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. The substantially hermetic package may be fabricated from thermoplastic glass, other types of glass, ceramics, or metals. Stereolithographic processes are used to fabricate at least a portion of the substantially hermetic package. These processes may be used to form a substantially hermetic package around the semiconductor dice of assemblies including carrier substrates or leads. Stereolithographic processes may also be used to fabricate the substantially hermetic packages on bare or minimally packaged semiconductor dice, including on dice that have yet to be singulated from a wafer. As at least a portion of the substantially hermetic package is stereolithographically fabricated, that portion can have a series of superimposed, contiguous, mutually adhered layers of a suitable hermetic material.

Abstract: A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers via an anisotropic epoxy. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon.

Abstract: The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.

Abstract: A method and apparatus for increasing integrated circuit density in a semiconductor die assembly, and specifically, a dual LOC semiconductor die assembly. A first and a second die are substantially symmetrically back bonded to a die attach site on a opposing sides of a base lead frame. A first and a second offset lead frame, each having a plurality of lead fingers, are then attached to the base lead frame on opposing sides thereof so that their lead fingers respectively extend over the first and second dice in a cantilevered manner. Wire bonds are formed between lead ends of each of the lead fingers to corresponding bond pads on the first and second dice for electrical connection therebetween. The assembly is then encapsulated in a transfer molding process, after which the stacked dual LOC semiconductor assembly is subjected to a trim and form operation.

Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.

Abstract: The present invention relates to a packaged semiconductor comprising:

Abstract: A flexible sheet used in manufacture of microelectronic components is held on a frame formed from a rigid material so that the frame maintains the sheet under tension during processing and thereby stabilizes the dimensions of the sheet. The frame may be formed from a rigid, light-transmissive material such as a glass, and the bond between the frame and sheet may be made or released by light transmitted through the frame. Preferred features of the framed sheet minimize entrapment of processing liquids such as etch solutions, thereby minimizing carryover of processing solutions between steps. The frame may have contact openings which permit engagement of a metallic layer on the sheet by an electrode carrying electroplating or etching current without disturbing the main portion of the sheet where features are to be formed or treated.

Abstract: A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

Abstract: A push-back circuit board frame on which a semiconductor device is mounted, including a circuit board, the board being detached from the frame and being returned to an original position in the frame, a cavity formed at an edge of the circuit board in the frame, a semiconductor chip mounted on the circuit board, a resin sealing the semiconductor chip on the circuit board, and a support base made of the same material as the resin, formed in the cavity, where all of the resin is formed simultaneously, and connected each other.

Abstract: A tape ball grid array (TBGA) semiconductor package having a one metal layer interconnect substrate is provided. Further provided is a method for making the TBGA package having electrical connection through the one metal layer interconnect substrate down to a ground plane. The method includes: (a) defining at least one via hole through the one metal layer interconnect substrate; (b) filling the at least one via hole of the one metal layer interconnect substrate with a first solder ball; (c) reflowing the first solder ball; (d) placing a second solder ball over the reflowed first solder ball; and (e) reflowing the second solder ball to attach the second solder ball to the reflowed first solder ball. The reflowed first solder ball and the reflowed second solder ball form a ground via connection to the ground plane of the TBGA.

Abstract: A method and apparatus for connecting a lead of a lead frame to a contact pad of a semiconductor chip using a laser or other energy beam are herein disclosed. The lead may be wire bonded to the contact pad by heating the ends of a wire until the wire fuses to the contact pad and lead or an energy-fusible, electrically conductive material may be used to bond the ends of the wire to the contact pad and lead. In addition, this invention has utility for both conventional lead frame/semiconductor chip configurations and lead-over-chip configurations. In addition, with a lead-over-chip configuration, the lead may be directly bonded to the contact pad with a conductive material disposed between the lead and the contact pad.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are farmed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.

Abstract: The package-side land 3a of a semiconductor package P1 is wholly exposed into the opening 5a of a solder resist layer 5. The board-side land 12a of the mount board B1 is also wholly exposed into the opening 13a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14a, the soldering layer 14a is brought into contact to both the lands 3a and 12a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3a and 12a are set to be equal to each other in dimension and shape, the soldering layer 14a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress.

Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternately, a connector may contact a portion of the conductive trace to make contact therewith.

Abstract: A substrate for a plurality of electronic assemblies includes a strip of printed circuit board (PCB) material including a surface and a plurality of segments. Each segment is adapted to receive at least one electronic component and is arranged to be singulated into a plurality of individual electronic assemblies. Each segment has a perimeter portion located generally about the periphery of the segment, with the surface being covered with a solder mask, except for the perimeter portion.

Abstract: A method and apparatus for dissipating heat from an electrical component. The method includes providing a planar element including a first electrically and thermally conductive region and a second electrically and thermally conductive region, such that the first and second regions define a spacing therebetween, and wherein the planar element includes at least one mechanically stabilizing tie connected between the first and second regions across the spacing, directly connecting a first terminal of an electrical component to the first region, directly connecting a second terminal of the electrical component to the second regions, such that the electrical component bridges the spacing, and removing the at least one mechanically stabilizing tie from between the first and second regions.

Abstract: Providing a method of producing a semiconductor device wherein semiconductor element are sealed with a resin by using the same lead and other means regardless of the specifications of the semiconductor elements, and a semiconductor device which can be reduced in size and weight and has good heat dissipation performance and high-frequency performance. The semiconductor devices can be produced by mounting a plurality of the semiconductor elements on the lead frame having leads disposed substantially parallel to each other, sealing the whole with a resin, and cutting off the individual semiconductor devices.

Abstract: This invention provides a method of forming an electrode section on the inner surface of the transparent, electromagnetic wave shielding plate, composed of a transparent substrate coated with an electroconductive member and transparent film in this order. These are laminated into a monolithic structure via a heat-bond film. (a) The components of the transparent, electromagnetic wave shielding plate are laminated by hot pressing into the monolithic structure, after replacing the perimeter or part of the heat-bond film corresponding to the electrode section by a frame member almost as thick as the heat-bond film. (b) The frame member and part of the outer transparent film are removed. Both of these correspond to the electrode section, or only the outer transparent film for the part corresponds to the electrode section. (c) The electroconductive section of the electroconductive member is exposed to the surface layer section by the above steps (a) and (b).

Abstract: A method of decapsulating a packaged die includes removing packaging material from the bottom section of a die-containing package to expose a die pan, removing the die pan, removing material between the die pan and the bottom surface of the die, using the bottom surface of the die to determine a grind plane substantially parallel to the top surface of the die, and removing packaging material from the top section of the die-containing package to form a top surface substantially planar to the grind plane, preferably intersecting the wire bonds on the face of the die.

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate and in electrical communication with the patterned bond pad layer a patterned redistribution layer, wherein the patterned redistribution layer is formed employing a plating method. The method is particularly economical for fabricating the microelectronic fabrication.

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: In the known method, a semiconductor element (1) is provided with two connecting conductors (2, 3) by arranging, preferably a large number of elements (1) between first and a second conductive plate (5, 6), the two connecting conductors (2, 3) secured at the upper surface and lower surface of an element (1) being formed from the two plates (5, 6). The first connecting conductor (5) is formed from a part (2) of the first plate (5) which borders on an opening (7), and the element (1) is covered with a protective envelope (4). The known method has the drawback that the devices obtained are not always directly suitable for surface mounting. Furthermore, the reliability of the device is sub-optimal.

Abstract: A multi-die semiconductor encapsulation method, which includes the steps of (1) preparing a lead-frame having a center open area and parallel rows of pins around said center open area, (2) preparing a substrate having a plurality of die positioning zones at the center area of the back side wall thereof, a window respectively disposed at the center of each die positioning zone, conductor elements respectively disposed at the top side wall thereof around each window, and peripheral rows of terminals, (3) preparing a plurality of dies each having a plurality of solder tips and then fastening the dies to the die positioning zones at the substrate, (4) using conductor wires to connect the solder tips at the dies to the conductor elements at the substrate, (5) mounting the substrate in the center open area at the lead-frame and then connecting the terminals at the substrate to the pins at the lead frame respectively, and (6) encapsulating the assembly of the substrate, the lead-frame and the die into a multi-die se

Abstract: A method for making a semiconductor package firstly provides a lead frame having a first surface and a corresponding second surface. The lead frame includes at least a package unit that further includes a die pad, and a plurality of leads disposed on the periphery of the die pad where each of the leads further includes a neck portion. The method then attaches the second surface of the lead frame to a tape, and performs a punching process to cut off the neck portion of the lead so as to form a plurality of conductive blocks disposed independently on the periphery of the die pad. The method further provides a chip having its back surface attach to the first surface of the die pad, and provides electrical connection between the bonding pad and the first surface of the conductive block by using a plurality of bonding wires. Further, the method performs an encapsulating process to encapsulate the chip, the bonding wires, the die pad, and the first surface of the conductive block.

Abstract: The present invention provides a semiconductor package in which a semiconductor chip, a die pad, an adhesive, metal wires, LOC type inner and standard type inner leads are sealed with a sealing resin. The LOC type inner leads and the standard type inner leads are arranged on a same plane and mixedly arranged along a side of the semiconductor chip. Clearance between the inner leads and the die pad is set to be larger than a sum of thickness of the semiconductor chip and the bonding material. Thus, a semiconductor chip having electrode pads broadly distributed and arranged thereon can be employed and the modulus of section of the semiconductor package can be enhanced.

Abstract: After a trench 54 is formed in a conductive foil 60, a circuit element is mounted in a flip chip method. Then, an insulating resin 50 is covered on the conductive foil 60 as a support substrate. After reversion, the conductive foil 60 is polished over the insulating resin 50 as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths 51 and the circuit elements 52 supported by the insulating resin 50 can be produced without employing the support substrate.

Abstract: The present invention discloses a method of manufacturing a dual chip package using tape wiring boards. According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are prepared. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad.